Sparse augmented KAN network based analog circuit multi-objective optimization method and system

Abstract

The application provides a sparse enhanced KAN network-based analog circuit multi-objective optimization method and system, relates to the technical field of analog integrated circuit design optimization, and comprises the following steps: sampling initial design parameters, performing circuit simulation, and constructing a training set; constructing a sparse enhanced KAN agent model and training based on the training set; calculating design parameter sensitivity and performing normalization processing; starting iteration by using a decomposition-based multi-objective optimization algorithm, calculating a comprehensive sensitivity vector; calculating an adaptive mutation step length according to the comprehensive sensitivity vector, performing differential mutation based on the adaptive mutation step length to obtain a candidate solution, and updating a neighborhood population; repeating iteration until a preset convergence condition is met or a maximum iteration number is reached, and outputting a Pareto optimal solution set corresponding to a current population. The application effectively improves the efficiency, solution set quality and interpretability of analog circuit multi-objective optimization.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design optimization technology, and in particular to a multi-objective optimization method and system for analog circuits based on sparse enhanced KAN networks. Background Technology

[0002] With the continuous evolution of semiconductor process nodes, the design complexity and multi-dimensional performance constraints of analog integrated circuits have increased significantly, making multi-objective optimization a core aspect of automated analog circuit design. Early analog circuit optimization heavily relied on iterative manual experience from designers, resulting in long design cycles and extremely low efficiency. Later, automated optimization schemes based on evolutionary algorithms were gradually applied, but the high computational cost of circuit simulation limited the convergence speed to meet engineering requirements. In recent years, surrogate model-assisted optimization schemes have become a research hotspot, and the rise of the Kolmogorov-Arnold network (KAN) has provided a new technical path for constructing high-precision surrogate models.

[0003] Existing multi-objective optimization techniques for analog circuits still suffer from several core shortcomings, failing to balance optimization efficiency, solution quality, and solution interpretability. First, existing surrogate models often employ traditional neural networks and Gaussian processes, struggling to balance fitting accuracy and generalization ability. They lack sufficient fitting capability for the strongly nonlinear mappings in the high-dimensional design space of analog circuits, and their black-box structure prevents them from automatically extracting the sensitivity of design parameters to performance indicators, thus failing to provide interpretable quantitative guidance for optimization searches. Second, existing evolutionary algorithms often employ a uniform search strategy with fixed step sizes, failing to differentiate searches based on parameter importance. Insufficient fine-tuning of high-sensitivity parameters and inadequate global exploration of low-sensitivity parameters result in slow convergence speeds and poor Pareto solution set distribution and convergence. Third, existing surrogate models are prone to localized accuracy degradation during optimization iterations, suffer from high computational overhead for full retraining, and are susceptible to catastrophic forgetting in incremental update schemes. They cannot maintain model prediction accuracy with low computational costs, making them ill-suited for the engineering optimization needs of large-scale complex analog circuits.

[0004] How to solve the above-mentioned technical problems is the challenge facing this invention. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and system for multi-objective optimization of analog circuits based on sparse augmented KAN networks, which effectively improves the efficiency, solution quality, and interpretability of multi-objective optimization of analog circuits.

[0006] The technical solution adopted by this invention to solve its technical problem is as follows: This invention provides a multi-objective optimization method for analog circuits based on sparse enhanced KAN networks, comprising the following steps: S1. Define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. Sample the initial design parameters based on the design parameter constraint range, and perform circuit simulation on the initial design parameters to obtain the simulation performance index. Summarize the initial design parameters and the simulation performance index to obtain the training set. S2. Construct a sparse augmented KAN surrogate model. Train the sparse augmented KAN surrogate model based on the training set to obtain the trained sparse augmented KAN surrogate model. Based on the trained sparse augmented KAN surrogate model, calculate the design parameter sensitivity corresponding to the multi-objective optimization index, and normalize the design parameter sensitivity to obtain the normalized sensitivity vector. S3. Using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm, generate a weight vector and initialize the neighborhood set and ideal point; start the iteration using a decomposition-based multi-objective optimization algorithm, and calculate the comprehensive sensitivity vector for each sub-problem based on the normalized sensitivity vector, weight vector and the current population. S4. For each sub-problem, calculate the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and perform differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. Obtain the predicted performance index through the trained sparse augmented KAN surrogate model, calculate the aggregation function value based on the candidate solutions and the predicted performance index, and update the neighborhood population based on the aggregation function value. S5. Repeat steps S3-S4 until the preset convergence condition is met or the maximum number of iterations is reached. Output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized.

[0007] Preferably, in step S1, the initial design parameters are generated using the Latin hypercube sampling method, and the SPICE simulator is used to perform circuit simulation on the initial design parameters to obtain the simulation performance indicators; the simulation performance indicators are then correlated with the corresponding initial design parameters to obtain the training set.

[0008] Preferably, the sparse augmented KAN proxy model in step S2 adopts a shared backbone network and a multi-output head architecture, and introduces a sparse activation gating function at the network edges; the multi-output head architecture includes several lightweight output heads; the sparse activation gating function is expressed as follows:

[0009] in, For Heaviside step function, For learnable threshold parameters, For historical activation intensity, This represents the number of training steps for the network. The training of the sparse augmented KAN surrogate model based on the training set includes: using design parameters as network input, using predicted circuit performance indicators as network output, using the loss function as the weighted sum of mean square error and sparse regularization term, and using continuous approximation technique and pass-through estimator for training. The formula for calculating the sensitivity of the design parameters is as follows:

[0010] in This represents the number of nodes in the first hidden layer. After the model training converges, the input layer's... The node is connected to the first hidden layer. The final steady-state sparse gated state of each node. Output head weight vector The Each component.

[0011] Preferably, the step S3 of calculating the comprehensive sensitivity vector for each sub-problem includes: For each subproblem, the weight vector of each component is weighted and summed with the normalized sensitivity vector corresponding to each multi-objective optimization index to obtain the comprehensive sensitivity vector of the subproblem.

[0012] Preferably, the calculation formula for the adaptive variable asynchronous length in step S4 is expressed as follows:

[0013] in As the baseline scaling factor, For adjustment coefficients, For the first Under the multi-objective optimization sub-problem, the first... The overall sensitivity of each design parameter; The calculation formula for performing differential mutations is expressed as follows:

[0014] in, This indicates element-wise multiplication. These are distinct parent individuals randomly selected from the neighborhood set of the subproblem. For individual indexes, For adaptive scaling factor vector; The PBI function is used to calculate the aggregation function value.

[0015] Preferably, the repetition of steps S3-S4 in step S5 until a preset convergence condition is met or the maximum number of iterations is reached specifically includes: After each iteration, calculate the hypervolume value of the current population. If the relative change in hypervolume value is less than the preset change threshold for several consecutive iterations, it is determined to be premature convergence and the optimization is terminated. Otherwise, continue to execute steps S3-S4 until the maximum number of iterations is reached.

[0016] Preferably, the multi-objective optimization method for analog circuits based on sparse reinforced KAN networks further includes: At a preset verification time, the model parameters are updated using an incremental learning mechanism to obtain the updated sparse augmented KAN proxy model, and the normalized sensitivity vector is updated based on the updated sparse augmented KAN proxy model; the specific steps of updating the model parameters using the incremental learning mechanism include: At a preset verification time, a preset proportion of individuals are uniformly drawn from the current population, and circuit simulation is performed on the individuals to obtain the verification set. The sparse augmented KAN surrogate model performs incremental learning based on the validation set, specifically including: freezing the weights of the basic functions in the sparse augmented KAN surrogate model, and enabling gradient updates for the spline coefficients corresponding to the network edges that are still active, as well as the weights and bias parameters of each output head.

[0017] This invention also provides a multi-objective optimization system for analog circuits based on sparse reinforced KAN networks, comprising: The training set construction module is used to define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. It samples the initial design parameters based on the design parameter constraint range, performs circuit simulation on the initial design parameters, obtains the simulation performance index, and summarizes the initial design parameters and simulation performance index to obtain the training set. The model building and training module is used to build a sparse augmented KAN proxy model, train the sparse augmented KAN proxy model based on the training set, and obtain the trained sparse augmented KAN proxy model. The sensitivity extraction module is used to calculate the sensitivity of design parameters corresponding to multi-objective optimization indicators based on the trained sparse augmented KAN surrogate model, and to normalize the sensitivity of design parameters to obtain a normalized sensitivity vector; based on the normalized sensitivity vector, weight vector and current population, a comprehensive sensitivity vector is calculated for each sub-problem. The multi-objective optimization execution module is used to generate a weight vector and initialize the neighborhood set and ideal point using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm. It starts the iteration with a decomposition-based multi-objective optimization algorithm. For each sub-problem, it calculates the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and performs differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. It obtains the predicted performance index through the trained sparse augmented KAN surrogate model, calculates the aggregation function value based on the candidate solutions and the predicted performance index, and updates the neighborhood population based on the aggregation function value. The iterative control and result output module is used to repeatedly iterate until the preset convergence condition is met or the maximum number of iterations is reached, and output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized; at the preset verification time, the model parameters are updated using an incremental learning mechanism to obtain the updated sparse augmented KAN surrogate model, and the normalized sensitivity vector is updated based on the updated sparse augmented KAN surrogate model.

[0018] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the above-described multi-objective optimization method for analog circuits based on sparse augmented KAN networks.

[0019] The present invention also provides a computer storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described multi-objective optimization method for analog circuits based on sparse augmented KAN networks.

[0020] The beneficial effects of this invention are as follows: it effectively improves the efficiency, solution set quality, and interpretability of multi-objective optimization of analog circuits. A sparse augmented KAN network is used to construct a surrogate model. Through a sparse gating mechanism with learnable thresholds and an architecture design of a shared backbone + multiple lightweight output heads, the fitting accuracy and generalization ability for strongly nonlinear mappings of high-dimensional design spaces of analog circuits are significantly improved. Simultaneously, the sensitivity information of design parameters to each optimization objective can be directly extracted from the trained model, breaking the black-box limitation of traditional surrogate models and providing interpretable quantitative guidance for optimization search. Based on the comprehensive sensitivity vector specific to sub-problems, a dimension-adaptive variable-asynchronous length is generated and a differential mutation operation is performed. Small step sizes are used for fine-tuning of high-sensitivity parameters, while large step sizes are used for global exploration of low-sensitivity parameters. This achieves optimal allocation of search resources, significantly accelerates the algorithm's convergence speed, and effectively improves the convergence and distribution uniformity of the Pareto optimal solution set. A hierarchical incremental learning mechanism is adopted to periodically update the surrogate model during the iteration process. By freezing the weights of the model's basic functions and updating only the activation edge spline coefficients and output head parameters, a lightweight update strategy is adopted. This avoids catastrophic forgetting of the model and solves the problem of local accuracy degradation of the surrogate model during the iteration process with extremely low computational overhead. Attached Figure Description

[0021] Figure 1 This is a diagram illustrating the method steps of the present invention.

[0022] Figure 2 This is a system module diagram of the present invention.

[0023] Figure 3 This is a schematic diagram of the network architecture of the present invention.

[0024] Figure 4 This is a circuit topology diagram of a two-stage operational amplifier (TSOA) according to Embodiment 3 of the present invention.

[0025] Figure 5 This is a circuit topology diagram of a fully differential operational amplifier (FDOA) according to Embodiment 3 of the present invention.

[0026] Figure 6 This is a diagram of the internal structure of a computer device according to Embodiment 4 of the present invention. Detailed Implementation

[0027] To clearly illustrate the technical features of this solution, the following detailed implementation method will be used to explain the solution.

[0028] Example 1: See Figure 1 , 3 As shown, this embodiment is a multi-objective optimization method for analog circuits based on sparse reinforced KAN networks, including the following steps: S1. Define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. Sample the initial design parameters based on the design parameter constraint range, and perform circuit simulation on the initial design parameters to obtain the circuit performance index. Summarize the initial design parameters and the simulation performance index to obtain the training set. It should be noted that design parameters are independently adjustable physical variables in analog circuit design, including but not limited to: channel width, channel length, cross exponent, multi-exponent, bias current multiple, compensation capacitor value, and compensation resistor value of MOS transistors. Each design parameter has a preset lower and upper bound, the range of which is determined by the design rules of the selected process and engineering conditions such as the circuit's operating voltage and power consumption budget. Circuit performance indicators are key parameters for measuring the quality of circuit performance, including but not limited to: DC gain, gain-bandwidth product, phase margin, power consumption, output reference noise, and layout area. These indicators are usually obtained through measurement or calculation using circuit simulation tools.

[0029] Furthermore, after determining the design parameter constraints, the Latin hypercube sampling method is used to generate initial design parameter samples. Latin hypercube sampling is a hierarchical random sampling technique that divides the value range of each design parameter into several equal intervals and samples independently within each interval, thereby achieving uniform coverage of the high-dimensional design space with a smaller number of samples. It should be noted that the sampling scale (i.e., the number of initial design parameter samples) can be determined comprehensively based on the dimension of the design parameters, the number of indicators to be optimized, and the sample size required for subsequent surrogate model training.

[0030] Then, circuit simulation is performed on each initial design parameter sample to obtain the corresponding circuit performance index vector. Circuit simulation is performed using industry-standard circuit simulation tools (such as SPICE, Spectre, HSPICE, etc.).

[0031] Furthermore, each set of initial design parameter vectors and its corresponding circuit performance index vectors are summarized to form an initial training set, which is used to train the sparse augmented KAN surrogate model in subsequent steps.

[0032] It should also be noted that after the initial sampling and simulation are completed, all simulation data is stored in the memory module. In the middle. This memory module. This is used to reuse existing simulation results in subsequent incremental learning steps, avoiding repeated simulations of the same design parameters and thus reducing computational overhead. Memory module This can be implemented using hash tables or key-value databases, storing design parameter vectors as keys and corresponding circuit performance index vectors as values.

[0033] Through the above operations, step S1 completes the construction of the initial training set, providing a high-quality data foundation for the subsequent training of the sparse augmented KAN proxy model.

[0034] S2. Construct a sparse augmented KAN surrogate model. Train the sparse augmented KAN surrogate model based on the training set to obtain the trained sparse augmented KAN surrogate model. Based on the trained sparse augmented KAN surrogate model, calculate the design parameter sensitivity corresponding to the multi-objective optimization index, and normalize the design parameter sensitivity to obtain the normalized sensitivity vector. The core task of this step is to use the training set constructed in step S1 to establish a high-precision surrogate model from design parameters to circuit performance indicators, and to extract the sensitivity information of each design parameter to each optimization indicator from the trained model, so as to provide guidance for subsequent differentiated evolution search.

[0035] (1) Constructing a sparse augmented KAN (SEKAN) surrogate model like Figure 3 As shown, the proxy model constructed in this step is a sparse augmented Kolmogorov model. The Arnold network (SEKAN) introduces two core improvements on the standard KAN: first, it sets a sparse gating mechanism with learnable thresholds on the network edges; second, it sets multiple lightweight output heads on a shared backbone network to simultaneously fit multiple circuit performance metrics.

[0036] Furthermore, the SEKAN network structure includes: an input layer with the same number of nodes as the design parameters; at least one hidden layer, where each node performs feature transformation using a learnable spline basis function and a nonlinear activation function; and an output feature layer for generating shared high-dimensional feature representations. An adaptive gating function is introduced at each edge of the network layer. This gating function determines whether the edge participates in the forward computation based on a comparison between historical activation strengths and the current threshold, thereby achieving sparse activation of the network. Defined as:

[0037] in, For Heaviside step function, For learnable threshold parameters, For historical activation intensity, This represents the number of training steps for the network. The historical activation strength is updated using an exponential moving average that introduces a probe-resurrection mechanism:

[0038] in, As a smoothing factor, This is the resurrection strength coefficient. The detection probability is related to the number of training steps. This indicates the number of consecutive steps the network edge remains inactive. Probability of detection. Follow The increase is linear (e.g.: This means that the longer an edge is closed, the stronger the system's willingness to "probe and restart" it. Its direct purpose is to prevent critical network edges from being incorrectly closed for a long time, thereby maintaining the network's feature exploration capability during the optimization process.

[0039] This is the output of the parameterized spline activation function on this network edge. The output of the sparsified edge is... .

[0040] It should also be noted that the multi-output head architecture adopts a "shared backbone + task-specific head" design: all optimization metrics share the feature vector output by the same backbone network. Each optimization metric has an objective function corresponding to an independent linear output header:

[0041] in and The first The weight vector and bias of the output head corresponding to the objective function of each optimization metric. The multi-objective prediction vector is:

[0042] This architecture enables different targets to share underlying feature representations while allowing each target to have an independent linear mapping, thus balancing fitting accuracy and parameter efficiency.

[0043] (2) Training the SEKAN proxy model Furthermore, the SEKAN model is trained using the training set constructed in step S1. During training, the network input is the design parameter vector. The output is a vector of predicted performance metrics. The loss function is a weighted sum of mean squared error (MSE) and a sparse regularization term:

[0044] The first item is the prediction error. The first term represents the true multi-objective performance index vector obtained through circuit simulation; the second term is the sparsity penalty. is the regularization coefficient. Training is performed using continuous approximation techniques and a straight-through estimator (STE) until the loss function converges or the preset maximum number of training rounds is reached.

[0045] Furthermore, during training, the threshold parameter of the gating function... The data is updated synchronously. When the historical activation strength of an edge falls below its learnable threshold, the edge is temporarily turned off, i.e., the corresponding gating output is zero; otherwise, the edge remains active. This mechanism enables the network to automatically identify a few critical paths that are essential to the prediction task, thereby achieving a sparse representation of the design space and interpretably revealing which design parameters dominate which performance metrics.

[0046] (3) Extracting target-specific parameter sensitivity It should be noted that after the model is trained, the sparse gating states and output head parameters within the network contain information about the sensitivity of the design parameters to various optimization metrics. This invention extracts this information from the trained SEKAN model using the following method: For the The optimization metric, the first Sensitivity of each design parameter Defined as:

[0047] in This represents the number of nodes in the first hidden layer. After the model training converges, the input layer's... The node is connected to the first hidden layer. The final steady-state sparse gated state of each node. Output head weight vector The The formula has several components. The physical meaning of this formula is that this design parameter is only highly sensitive to the current target when the edges are gated and retained in the first layer, and the absolute value of their corresponding output head weights is large.

[0048] Furthermore, the calculated sensitivity is normalized to eliminate the influence of differences in the dimensions of the objective function for different optimization indices:

[0049] in, This is the minimum value of sensitivity. The maximum value in sensitivity. For a very small positive number (e.g.) This is used to prevent the denominator from being zero. After normalization, all sensitivity values ​​are mapped to... The larger the value in the range, the more important the design parameter is to the first... The more significant the impact of each optimization indicator, the better.

[0050] Furthermore, the first All normalized sensitivities corresponding to each optimization metric are combined into a vector:

[0051] This vector is the core information used to guide the differential mutation operation in subsequent steps. It should be noted that this sensitivity vector is extracted all at once after the initial model training is completed, and in subsequent hierarchical incremental learning steps, the sensitivity vector is extracted again whenever the model is updated to ensure that the search guidance information is always synchronized with the current surrogate model state.

[0052] Through the above operations, step S2 completed the construction and training of the SEKAN surrogate model and obtained the normalized sensitivity vector of each optimization index with respect to each design parameter, laying the foundation for the sensitivity-based differential evolution search in steps S3 and S4.

[0053] S3. Using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm, generate a weight vector and initialize the neighborhood set and ideal point; start the iteration using a decomposition-based multi-objective optimization algorithm, and calculate the comprehensive sensitivity vector for each sub-problem based on the normalized sensitivity vector, weight vector and the current population. The core task of this step is to use the initial design parameters sampled in step S1 as the initial population of the multi-objective evolutionary algorithm, and to generate a comprehensive sensitivity vector for each sub-problem based on the normalized sensitivity vector extracted in step S2, thereby laying the foundation for subsequent differential mutation operations.

[0054] (1) Initialize the population and weight vector It should be noted that this step employs a decomposition-based multi-objective evolutionary algorithm (MOEA / D) framework. The initial design parameter samples generated in step S1 through Latin hypercube sampling are directly used as the initial population. Population size is denoted as Each individual corresponds to a design parameter vector. .

[0055] Furthermore, a set of uniformly distributed weight vectors is generated. Each weight vector satisfy The number of weight vectors is equal to the population size; that is, each subproblem corresponds to one weight vector, and each individual in the population serves as the initial solution for that subproblem. Specifically, uniformly distributed weight vectors are generated using a Simplex lattice or a random generation method.

[0056] It should also be noted that a neighborhood set is determined for each subproblem. Specifically, for the first Sub-problems (corresponding weight vectors) ), calculate the Euclidean distance between the weight vector and all other weight vectors, and select the closest one. The sub-problem indices corresponding to each weight vector constitute its neighborhood set. Neighborhood size These are preset parameters, typically taken as a fraction of the population size. about.

[0057] (2) Initialize the ideal point Furthermore, initialize the ideal point for multi-objective optimization. The ideal point records the optimal value achieved for each optimization metric in the current population. Specifically, for the ... If the optimization direction is minimization, then... If the optimization direction is maximization, then the objective function is first negativeened and transformed into a minimization problem for unified processing. The initial ideal point is based on the initial population. The actual simulation performance index of all individuals in the model was calculated.

[0058] (3) Calculate the comprehensive sensitivity vector of each sub-problem It should be noted that in order to apply the normalized sensitivity vectors of each target extracted in step S2 to different sub-problems, it is necessary to perform weighted aggregation of the sensitivity of each target according to the weight vector of the sub-problem to obtain the comprehensive sensitivity vector of the sub-problem.

[0059] Specifically, for the first The weight vector of each sub-problem is: The normalized sensitivity vectors of each optimization index are: (Each one is) (Dimensional vector). The comprehensive sensitivity vector of this subproblem. Calculate using the following formula:

[0060] in It is A dimensional vector, whose dimensional vector is the first dimensional vector. Each component Indicates the first Under the weighted preferences represented by each sub-problem, the first The overall sensitivity of each design parameter.

[0061] Furthermore, the comprehensive sensitivity vector Each component value is located in The range. The larger the value, the more significant the impact of changes in the corresponding design parameters on the weighted overall performance under the preferences of this subproblem; the closer the value is to 0, the weaker the contribution of this parameter to the optimization index of the current subproblem. This information will be directly used in step S4 to generate the adaptive variable asynchronous length.

[0062] Through the above operations, step S3 completes the initialization of the multi-objective evolution algorithm and generates a comprehensive sensitivity vector for each sub-problem, providing search guidance information that matches the preferences of the sub-problems for subsequent differential mutation operations.

[0063] S4. For each sub-problem, calculate the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and perform differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. Obtain the predicted performance index through the trained sparse augmented KAN surrogate model, calculate the aggregation function value based on the candidate solutions and the predicted performance index, and update the neighborhood population based on the aggregation function value. The core task of this step is to use the comprehensive sensitivity vector of each sub-problem generated in step S3 to guide the differential mutation operation to generate candidate solutions, quickly predict the performance of the candidate solutions through the trained SEKAN surrogate model, and complete the population update based on the prediction results.

[0064] (1) Generate adaptive variable asynchronous length It should be noted that, in order to apply differentiated search intensity across different design parameter dimensions, a variable step size (scaling factor) needs to be adaptively generated for each dimension based on the comprehensive sensitivity vector of the subproblem. Dimensions with higher sensitivity indicate that the design parameter has a more significant impact on the comprehensive performance under the current subproblem's preference, and should be searched with a smaller step size; dimensions with lower sensitivity can be explored globally with a larger step size.

[0065] Furthermore, regarding the first Each sub-problem has a combined sensitivity vector of: No. Adaptive scaling factor for each design dimension Calculate using the following formula:

[0066] in The base scaling factor (usually 0.5) This is the adjustment coefficient (usually ranging from 0.5 to 1.0). For the first The comprehensive sensitivity of each design parameter. This formula guarantees that when the sensitivity is... As the value approaches 1, the scaling factor approaches 1. (Smaller step size); as sensitivity approaches 0, the scaling factor approaches... (Larger step size). The scaling factors of all dimensions form a vector. .

[0067] (2) Perform differential mutation to generate candidate solutions Furthermore, from the current sub-problem neighborhood set Three distinct individual indexes are randomly selected from the data. The corresponding design parameter vectors are respectively Perform a differential mutation operation to generate candidate solution vectors. :

[0068] in This indicates element-wise multiplication. It should be noted that this mutation operator generates new solutions using the difference information of individuals within the neighborhood, while simultaneously using a dimension-adaptive scaling factor. To achieve differentiated perturbation of different design parameters, the search behavior is matched with the parameter sensitivity.

[0069] Furthermore, regarding the generated candidate solutions Boundary handling: If the value of a certain dimension exceeds the design parameter constraint range defined in step S1, it is corrected to the nearest boundary value to ensure the engineering feasibility of the candidate solution.

[0070] (3) Proxy model prediction and population update It should be noted that, in order to avoid performing time-consuming circuit simulations for each candidate solution, this invention utilizes the SEKAN surrogate model trained in step S2 to quickly predict the performance of the candidate solutions.

[0071] Specifically, candidate solutions Input the SEKAN model to obtain the predicted multi-objective performance vector. At the same time, based on the current ideal point Update the ideal point with the predicted values ​​of the candidate solutions: for each objective ,like Better than the current (For minimization problems, smaller values ​​are better), then update .

[0072] Furthermore, the neighborhood population is updated based on the prediction results. For the neighborhood set... For each individual, candidate solutions are computed using the PBI (Penalized Boundary Crossing) aggregation function. With the current individual The fitness value. If the PBI value of a candidate solution is less than the PBI value of the current individual, then the candidate solution is used. Replace the current individual .

[0073] Furthermore, perform the above operation sequentially on all subproblems (i.e., traverse) This completes a full cycle of population renewal.

[0074] Through the above operations, step S4 achieves sensitivity-guided differential mutation generation and rapid evaluation assisted by surrogate models, effectively improving the generation efficiency of high-quality candidate solutions and the convergence speed of the population.

[0075] S5. Repeat steps S3-S4 until the preset convergence condition is met or the maximum number of iterations is reached. Output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized. The multi-objective optimization method for analog circuits based on sparse augmented KAN networks also includes updating the model parameters using an incremental learning mechanism at a preset verification time to obtain an updated sparse augmented KAN surrogate model, and updating the normalized sensitivity vector based on the updated sparse augmented KAN surrogate model.

[0076] This step sets the termination condition for the optimization algorithm and outputs the final Pareto optimal solution set. On the other hand, it introduces a hierarchical incremental learning mechanism during the iteration process to maintain the prediction accuracy of the surrogate model with low computational cost and prevent model degradation.

[0077] (1) Iteration Termination and Result Output It should be noted that steps S3 to S4 are repeated until a preset convergence condition is met or the maximum number of iterations is reached. The preset convergence condition may be: in several consecutive iterations, the relative change in the hypervolume (HV) index of the current population is less than a preset threshold, indicating that the population has converged to a stable Pareto front. The maximum number of iterations is a pre-set upper limit for algorithm termination, used to ensure that the algorithm can terminate within limited computational resources.

[0078] Furthermore, when the termination condition is met, the Pareto optimal solution set corresponding to the current population is output. Each solution in the Pareto optimal solution set is a design parameter vector, representing a design scheme that achieves the optimal trade-off among multiple conflicting circuit performance metrics. This solution set can be directly used by designers for reference or for subsequent circuit implementation.

[0079] (2) Hierarchical incremental learning mechanism Furthermore, in order to avoid the accuracy degradation of the surrogate model due to the accumulation of prediction bias during the iteration process, this invention triggers a hierarchical incremental learning mechanism at a preset verification time to update the SEKAN model at low cost.

[0080] It should be noted that the preset verification time can be triggered at fixed stages based on the total simulation budget (such as 25%, 50%, and 75% of the preset maximum number of iterations), or it can be triggered dynamically based on conditions such as model prediction error (such as when the model prediction error exceeds a threshold). At each verification time, the following operations are performed: ① Extracting validation samples: A certain proportion (e.g., 20%) of individuals are uniformly drawn from the current population to form the validation set. Prioritize memory modules. Individuals that already have real simulation data can be reused to reduce additional simulation overhead.

[0081] ② Obtain real performance data: For individuals in the validation set that have not yet undergone real simulation, perform circuit simulation (e.g., SPICE simulation) to obtain their real circuit performance index vectors, and store the newly obtained simulation data into the memory module. .

[0082] ③ Freeze basic parameters and update some parameters: Freeze all weights of the basic functions in the SEKAN network (i.e., the core parameters of the spline basis functions), and only update the spline coefficients corresponding to the edges that are still active, as well as the weights of each output head. With bias This enables gradient updates. This hierarchical update strategy significantly reduces the number of parameters that need to be optimized, thereby reducing the sample size and computation time required for model updates.

[0083] ④ Perform incremental training: Use validation set data (including newly added real simulation data) to train the above updatable parameters for a small number of rounds (e.g., 10 to 20 rounds) to enable the model to quickly adapt to the latest search region.

[0084] ⑤ Re-extract the sensitivity vector: Based on the updated SEKAN model, recalculate the normalized sensitivity vector of each optimization objective according to the method in step S2. And simultaneously update the comprehensive sensitivity vector of each sub-problem in step S3. This ensures that the guidance information for subsequent differential mutation operations is consistent with the current model state.

[0085] It should also be noted that this hierarchical incremental learning mechanism does not require a complete retraining of the SEKAN model, but only performs local fine-tuning of key parameters, while retaining the global feature mapping capabilities learned in the initial training. By periodically triggering this mechanism, the prediction accuracy of the surrogate model can be maintained throughout the optimization process with low computational overhead, effectively preventing the negative impact of model degradation on the quality of the final solution set.

[0086] Through the above steps S1 to S5, the present invention fully realizes the multi-objective optimization of analog circuits based on the sparse augmented KAN proxy model, which significantly improves the quality and interpretability of the final solution set while ensuring optimization efficiency.

[0087] Example 2: See Figure 2 As shown, this embodiment is a multi-objective optimization system for analog circuits based on sparse reinforced KAN networks, including... The training set construction module is used to define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. It samples the initial design parameters based on the design parameter constraint range, performs circuit simulation on the initial design parameters, obtains the simulation performance index, and summarizes the initial design parameters and simulation performance index to obtain the training set. The model building and training module is used to build a sparse augmented KAN proxy model, train the sparse augmented KAN proxy model based on the training set, and obtain the trained sparse augmented KAN proxy model. The sensitivity extraction module is used to calculate the sensitivity of design parameters corresponding to multi-objective optimization indicators based on the trained sparse augmented KAN surrogate model, and to normalize the sensitivity of design parameters to obtain a normalized sensitivity vector; based on the normalized sensitivity vector, weight vector and current population, a comprehensive sensitivity vector is calculated for each sub-problem. The multi-objective optimization execution module is used to generate a weight vector and initialize the neighborhood set and ideal point using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm. It starts the iteration with a decomposition-based multi-objective optimization algorithm. For each sub-problem, it calculates the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and performs differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. It obtains the predicted performance index through the trained sparse augmented KAN surrogate model, calculates the aggregation function value based on the candidate solutions and the predicted performance index, and updates the neighborhood population based on the aggregation function value. The iterative control and result output module is used to repeatedly iterate until the preset convergence condition is met or the maximum number of iterations is reached, and output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized; at the preset verification time, the model parameters are updated using an incremental learning mechanism to obtain the updated sparse augmented KAN surrogate model, and the normalized sensitivity vector is updated based on the updated sparse augmented KAN surrogate model.

[0088] Example 3: To verify the effectiveness of the multi-objective optimization method for analog circuits based on sparse augmented KAN networks proposed in this invention, this embodiment takes the optimization of a two-stage operational amplifier and the optimization of a fully differential operational amplifier as examples to optimize the design parameters.

[0089] The effectiveness and efficiency of the proposed method will be illustrated next using the optimization of a two-stage operational amplifier as an example. Figure 4 The diagram shown is of a two-stage operational amplifier (TSOA). This circuit employs a classic two-stage Miller compensated topology, includes 17 design parameters, and is connected between the global power supply positive rail VDD and ground. The specific circuit connections and the correspondence between the four functional modules are as follows: (1) Bias circuit: including transistors M8~M13 and bias resistor RB, used to provide stable bias voltage and current for the entire operational amplifier (corresponding parameters bias_p_m, bias_p_nf, bias_n_m, bias_n_nf).

[0090] (2) First stage differential amplifier module: including PMOS tail current transistor M5 (whose gate is controlled by the bias circuit), and PMOS differential input pair transistors M1 and M2 (corresponding parameters in_fw, in_l, in_m, in_nf), the gates of M1 and M2 are respectively connected to the inverting input terminal VN and the non-inverting input terminal VP, and their sources are connected to the drain of tail current transistor M5; and a current mirror active load composed of NMOS transistors M3 and M4 (corresponding parameter load_m).

[0091] (3) Second stage amplification module: including NMOS transistor M6 as a common source amplifier and PMOS transistor M7 as an active load (corresponding parameters o_fw, o_l, o_m, o_nf and bias parameters ibias_m, ibias_nf). The gate of M6 is connected to the first stage output node (i.e. the drain connection of M2 and M4), and the drain is connected to the output terminal and the load capacitor CL.

[0092] (4) Miller compensation network: includes a compensation capacitor Cc connected between the first stage output and the second stage output and a zero-adjustment transistor M14 (M14 is equivalent to a zero-adjustment resistor), and the gate of M14 is connected to the bias circuit to obtain a steady-state bias for adjusting the phase margin of the system.

[0093] There are 17 decision variables for this circuit, and 5 optimization objectives: low-frequency gain Gain@10Hz (dB), gain-bandwidth product UGBW (MHz), and phase margin PM (°) obtained through STB analysis; output reference noise out_noise@100Hz (nV / √Hz) obtained through noise analysis; and power consumption Power (mW) calculated through current integration.

[0094] Table 1 compares the optimization results of each algorithm on the TSOA circuit:

[0095] As shown in Table 1, this invention achieves optimal performance in four out of five metrics: DC gain reaches 84.7 dB, a 1.9% improvement over the second-best KIDEA algorithm; power consumption is reduced to 3.38 mW, an 11.3% reduction compared to KIDEA; noise is optimized to 22.8 nV / √Hz, a 9.9% improvement compared to the second-best S-MOEA / D algorithm; and phase margin reaches 48.8°. In terms of overall performance, the HV index reaches 0.887, surpassing the second-best algorithm KIDEA by 4.0% (Wilcoxon test p < 0.05). Regarding computational efficiency, this invention requires only 1501 simulations to converge, saving 23.5% compared to KAN-EA and 12.3% compared to KIDEA.

[0096] Furthermore, the SEKAN network of this invention automatically identifies nine highly important parameters. Among them, the Miller compensation capacitor Cm has the most significant impact on the phase margin PM; the differential input width in_fw is extremely important for both gain and noise; the output stage width o_fw has the greatest impact on the gain-bandwidth product; and the bias current multiple ibias_m has the strongest impact on power consumption. This significant hierarchical characteristic of parameter sensitivity provides effective guidance for differentiated variation strategies.

[0097] When this method is used to optimize a fully differential operational amplifier, the results demonstrate the effectiveness and efficiency of the method proposed in this invention. For example... Figure 5 The diagram shown is of a fully differential operational amplifier (FDOA). This circuit employs a fully differential folded cascaded architecture, featuring a two-stage amplification design and incorporating 24 design parameters. The entire circuit is connected between the positive rail VDD and the negative rail VSS of the global power supply. The specific circuit connections and the correspondence between the four functional modules are as follows: (1) First-stage input module: includes a differential input pair consisting of PMOS transistors M1 and M2 (corresponding parameters m_vin1, fn_vin1), whose gates are connected to the non-inverting input terminal VIP and the inverting input terminal VIN respectively; and a PMOS tail current source transistor M0 (corresponding parameters m_tail, fn_tail), whose gate is connected to the bias voltage Vtail.

[0098] (2) Two-layer cascaded network (folded cascaded load): It includes a PMOS cascaded branch composed of PMOS transistors M3, M5 and M4, M6 (corresponding parameters m_VB1 / VB2, fn_VB1 / VB2, with the gates connected to bias voltages VB1 and VB2 respectively); and an NMOS cascaded branch composed of NMOS transistors M9, M10 and M11, M12 (corresponding parameters m_VB3 / VB4, fn_VB3 / VB4, with the gates connected to bias voltages VB3 and VB4 respectively). The drains of the first-stage differential pair M1 and M2 are connected to the low-impedance nodes of the folded cascaded network respectively, and the connection between the drains of the PMOS cascaded branch and the NMOS cascaded branch forms the two differential output nodes Voln and Volp of the first stage.

[0099] (3) Second-stage amplification module: includes PMOS output transistors M22 and M23 (corresponding parameters m_vin2 and fn_vin2), whose gates are connected to the first-stage output nodes Voln and Volp respectively; PMOS common-mode feedback control transistors M18 and M19 (corresponding parameters m_vfb and fn_vfb), whose gates are controlled by the common-mode feedback signal vfb; and NMOS transistors M13 and M14 (corresponding parameters m_vol and fn_vol) as output loads, whose gates are connected to the bias voltage VB5. The fully differential output terminals of the second stage are VOP and VON respectively, and four Miller compensation capacitors (Cc1, Cc2, Cc3, and Cc4) are connected between the first-stage output nodes (Voln and Volp) and VOP and VON respectively.

[0100] (4) Common-mode feedback network (CMFB): This includes a resistor network (composed of common-mode sampling resistors R1 and R2) for sampling the common-mode levels of the output VOP and VON respectively, a differential pair of error amplifiers composed of PMOS transistors M16 and M17 (M17 receives the common-mode reference voltage VREF, while M16 receives the sampling voltage through the STB stability simulation probe IPROB), PMOS tail current transistor M15 (whose gate is also connected to the bias voltage Vtail), and an active load composed of NMOS transistors M20 and M21. The feedback control signal vfb generated by this network is connected to the gates of M18 and M19 in the second stage to stabilize the output common-mode level.

[0101] There are 24 decision variables for this circuit, and 5 optimization objectives: open-loop gain (dB), unity-gain bandwidth (MHz), and phase margin (°) obtained through STB analysis, and power consumption (mW) and layout area (μm²) calculated through current integration and device size.

[0102] Table 2 compares the optimization results of each algorithm on the HGOA circuit:

[0103] As shown in Table 2, this invention achieves optimal performance in four out of five metrics: DC gain reaches 47.2 dB, a 6.6% improvement over the second-best KIDEA algorithm; phase margin reaches 49.1°; power consumption is reduced to 11.1 mW, a 4.3% reduction compared to the second-best S-MOEA / D algorithm; and area is controlled at 140.8 μm². The overall HV index reaches 0.692, surpassing the second-best KIDEA algorithm by 3.6% (Wilcoxon test p < 0.05). In terms of computational efficiency, this invention achieves convergence with 2095 simulations, saving approximately 9%–10% of simulation overhead compared to the comparison algorithms.

[0104] The SEKAN network of this invention achieves a sparse activation rate of 44.2% in this circuit, meaning only about 11 core parameters need to be considered. Among these, the first-stage input has the most significant impact on the gain due to the number of fingers fn_vin1; the second-stage input has the greatest impact on the gain-bandwidth product due to the number of fingers fn_vin2; the NMOS cascaded finger number fn_VB3 has the strongest impact on the phase margin; and the tail current multiple m_tail has the greatest impact on power consumption.

[0105] As the circuit complexity increases from TSOA (17 parameters) to HGOA (24 parameters), this invention automatically compresses the proportion of key parameters through a sparse activation mechanism, further increasing the optimization advantage and demonstrating that the method proposed in this invention has good scalability.

[0106] Example 4: This embodiment provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0107] This computer device can be a server, and its internal structure diagram can be as follows: Figure 6 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores server data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a multi-objective optimization method for analog circuits based on sparse augmented KAN networks.

[0108] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0109] Example 5: This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0110] If the functions implemented by the method are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art or the current technical solution, can be embodied in the form of a software product. This current computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0112] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0113] The technical features of this invention not described can be implemented by or using existing technology, and will not be repeated here. Of course, the above description is not a limitation of this invention, and this invention is not limited to the examples above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of this invention should also be within the protection scope of this invention.

Claims

1. A multi-objective optimization method for analog circuits based on sparse reinforced KAN networks, characterized in that, Includes the following steps: S1. Define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. Sample the initial design parameters based on the design parameter constraint range, and perform circuit simulation on the initial design parameters to obtain the simulation performance index. Summarize the initial design parameters and the simulation performance index to obtain the training set. S2. Construct a sparse augmented KAN surrogate model. Train the sparse augmented KAN surrogate model based on the training set to obtain the trained sparse augmented KAN surrogate model. Based on the trained sparse augmented KAN surrogate model, calculate the design parameter sensitivity corresponding to the multi-objective optimization index, and normalize the design parameter sensitivity to obtain the normalized sensitivity vector. S3. Using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm, generate a weight vector and initialize the neighborhood set and ideal point; start the iteration using a decomposition-based multi-objective optimization algorithm, and calculate the comprehensive sensitivity vector for each sub-problem based on the normalized sensitivity vector, weight vector and the current population. S4. For each sub-problem, calculate the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and perform differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. Obtain the predicted performance index through the trained sparse augmented KAN surrogate model, calculate the aggregation function value based on the candidate solutions and the predicted performance index, and update the neighborhood population based on the aggregation function value. S5. Repeat steps S3-S4 until the preset convergence condition is met or the maximum number of iterations is reached. Output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized.

2. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 1, characterized in that, In step S1, the initial design parameters are generated using the Latin hypercube sampling method, and the SPICE simulator is used to perform circuit simulation on the initial design parameters to obtain the simulation performance indicators; the simulation performance indicators are then correlated with the corresponding initial design parameters to obtain the training set.

3. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 2, characterized in that, The sparse augmented KAN proxy model in step S2 adopts a shared backbone network and a multi-output head architecture, and introduces a sparse activation gating function at the network edges; the multi-output head architecture includes several lightweight output heads; the sparse activation gating function is expressed as follows: in, For Heaviside step function, For learnable threshold parameters, For historical activation intensity, This represents the number of training steps for the network. The training of the sparse augmented KAN surrogate model based on the training set includes: using design parameters as network input, using predicted circuit performance indicators as network output, using the loss function as the weighted sum of mean square error and sparse regularization term, and using continuous approximation technique and pass-through estimator for training. The formula for calculating the sensitivity of the design parameters is as follows: in This represents the number of nodes in the first hidden layer. After the model training converges, the input layer's... The node is connected to the first hidden layer. The final steady-state sparse gated state of each node. Output head weight vector The Each component.

4. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 3, characterized in that, The step S3, which involves calculating the comprehensive sensitivity vector for each sub-problem, includes: For each subproblem, the weight vector of each component is weighted and summed with the normalized sensitivity vector corresponding to each multi-objective optimization index to obtain the comprehensive sensitivity vector of the subproblem.

5. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 4, characterized in that, The calculation formula for the adaptive variable asynchronous length in step S4 is expressed as follows: in As the baseline scaling factor, For adjustment coefficients, For the first Under the multi-objective optimization sub-problem, the first... The overall sensitivity of each design parameter; The calculation formula for performing differential mutations is expressed as follows: in, This indicates element-wise multiplication. These are distinct parent individuals randomly selected from the neighborhood set of the subproblem. For individual indexes, For adaptive scaling factor vector; The PBI function is used to calculate the aggregation function value.

6. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 5, characterized in that, The repetition of steps S3-S4 in step S5 until the preset convergence condition is met or the maximum number of iterations is reached specifically includes: After each iteration, calculate the hypervolume value of the current population. If the relative change in hypervolume value is less than the preset change threshold for several consecutive iterations, it is determined to be premature convergence and the optimization is terminated. Otherwise, continue to execute steps S3-S4 until the maximum number of iterations is reached.

7. The multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to claim 6, characterized in that, The multi-objective optimization method for analog circuits based on sparse augmented KAN networks further includes updating the model parameters using an incremental learning mechanism at a preset verification time to obtain an updated sparse augmented KAN surrogate model, and updating the normalized sensitivity vector based on the updated sparse augmented KAN surrogate model. The incremental learning mechanism for updating model parameters specifically includes: At a preset verification time, a preset proportion of individuals are uniformly drawn from the current population, and circuit simulation is performed on the individuals to obtain the verification set. The sparse augmented KAN surrogate model performs incremental learning based on the validation set, specifically including: freezing the weights of the basic functions in the sparse augmented KAN surrogate model, and enabling gradient updates for the spline coefficients corresponding to the network edges that are still active, as well as the weights and bias parameters of each output head.

8. A multi-objective optimization system for analog circuits based on sparse reinforced KAN networks, characterized in that, The steps for performing the multi-objective optimization method for analog circuits based on sparse reinforced KAN networks according to any one of claims 1 to 7 include: The training set construction module is used to define the design parameter constraint range and multi-objective optimization index of the analog circuit to be optimized. It samples the initial design parameters based on the design parameter constraint range, performs circuit simulation on the initial design parameters, obtains the simulation performance index, and summarizes the initial design parameters and simulation performance index to obtain the training set. The model building and training module is used to build a sparse augmented KAN proxy model, train the sparse augmented KAN proxy model based on the training set, and obtain the trained sparse augmented KAN proxy model. The sensitivity extraction module is used to calculate the sensitivity of design parameters corresponding to multi-objective optimization indicators based on the trained sparse augmented KAN surrogate model, and to normalize the sensitivity of design parameters to obtain a normalized sensitivity vector; based on the normalized sensitivity vector, weight vector and current population, a comprehensive sensitivity vector is calculated for each sub-problem. The multi-objective optimization execution module is used to generate a weight vector and initialize the neighborhood set and ideal point using the initial design parameters sampled in step S1 as the initial population of the multi-objective evolution algorithm. It starts the iteration with a decomposition-based multi-objective optimization algorithm. For each sub-problem, it calculates the adaptive variable asynchronous length based on the comprehensive sensitivity vector, and performs differential mutation based on the adaptive variable asynchronous length to obtain candidate solutions. It obtains the predicted performance index through the trained sparse augmented KAN surrogate model, calculates the aggregation function value based on the candidate solutions and the predicted performance index, and updates the neighborhood population based on the aggregation function value. The iterative control and result output module is used to repeatedly iterate until the preset convergence condition is met or the maximum number of iterations is reached, and output the Pareto optimal solution set corresponding to the current population, which is the multi-objective optimal design parameter set of the analog circuit to be optimized; at the preset verification time, the model parameters are updated using an incremental learning mechanism to obtain the updated sparse augmented KAN surrogate model, and the normalized sensitivity vector is updated based on the updated sparse augmented KAN surrogate model.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the multi-objective optimization method for analog circuits based on sparse augmented KAN networks as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the multi-objective optimization method for analog circuits based on sparse augmented KAN networks as described in any one of claims 1 to 7.

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