Design method of integrated circuit, electronic device, and storage medium

Abstract

The application discloses a design method of an integrated circuit, an electronic device and a storage medium, and belongs to the technical field of integrated circuit design automation. The method performs congestion optimization on initial hardware description information based on physical design constraint data in a constraint data set of the integrated circuit, to obtain first hardware description information. The physical design constraint data includes standard cell characteristic constraint data, macro cell layout constraint data and layout planning constraint data. The method performs MCMM optimization on the first hardware description information based on MCMM constraint data in the constraint data set, to obtain second hardware description information. The method performs congestion optimization on the second hardware description information after optimization based on the physical design constraint data, to obtain third hardware description information. The method performs layout simulation and deviation calibration based on the third hardware description information and the optimized physical design constraint data, to obtain target hardware description information and target physical guidance information, and thus the design efficiency of the integrated circuit can be improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design automation technology, and in particular relates to an integrated circuit design method, electronic device and storage medium. Background Technology

[0002] Physical implementation awareness is a core technology that connects the front-end Register Transfer Level (RTL) logic synthesis of integrated circuits with the back-end physical implementation. Its core value lies in integrating physical design constraints into the logic synthesis process in advance, providing precise physical guidance for back-end placement and routing tools, reducing front-end and back-end design iterations, and improving the overall efficiency of integrated circuit design.

[0003] In the process of integrated circuit design, traditional logic synthesis technology based on physical realization has not achieved fine-grained optimization for the two core synthesis objects, standard cells and macro cells, which leads to a large number of secondary adjustments required by the back-end placement and routing tools, resulting in low design efficiency. Summary of the Invention

[0004] The embodiments of this application provide an integrated circuit design method, an electronic device, and a storage medium, which can at least to some extent optimize the standard cells and macro cells in the hardware description information of the integrated circuit, avoiding a large number of secondary adjustments by the back-end placement and routing tools and improving the design efficiency of the integrated circuit.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0006] According to a first aspect of the embodiments of this application, a method for designing an integrated circuit is provided, comprising: Based on the physical design constraint data in the constraint dataset of integrated circuits, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information. The physical design constraint data includes standard cell characteristic constraint data, macro cell layout constraint data, and layout planning constraint data. The hardware description information is used to characterize the connection relationship between circuit elements, and the circuit elements include standard cells and macro cells. Based on the MCMM constraint data of multiple process angles and multiple working modes in the constraint dataset, the first hardware description information is optimized by MCMM to obtain the second hardware description information. Optimization is performed based on physical design constraint data to obtain optimized physical design constraint data; Based on the optimized physical design constraint data, congestion optimization is performed on the second hardware description information to obtain the third hardware description information. Layout simulation and deviation calibration are performed based on the third hardware description information and optimized physical design constraint data to obtain target hardware description information and target physical guidance information, which are then used to design integrated circuits.

[0007] In some embodiments, based on physical design constraint data in the constraint dataset of integrated circuits, congestion optimization is performed on the initial hardware description information to obtain first hardware description information, including: Based on standard cell characteristic constraint data, macro cell layout constraint data, standard cell layout density, and macro cell interface pin density, the standard cell cost coefficient model and the macro cell cost coefficient model are determined. Based on the layout planning constraint data, standard cell characteristic constraint data, macro cell layout constraint data, standard cell cost coefficient model and macro cell cost coefficient model, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information.

[0008] In some embodiments, the standard cell cost coefficient model and the macro cell cost coefficient model are determined based on standard cell characteristic constraint data, macro cell layout constraint data, standard cell layout density, and macro cell interface pin density, including: Based on standard cell characteristic constraint data, standard cell driving capability, standard cell leakage current and standard cell layout density, a standard cell cost coefficient model is determined. Based on macrocell layout constraint data, macrocell layout location, macrocell wiring channel width, and macrocell interface pin density, a macrocell cost coefficient model is determined.

[0009] In some embodiments, based on layout planning constraint data, standard cell characteristic constraint data, macro cell layout constraint data, standard cell cost coefficient model, and macro cell cost coefficient model, congestion optimization is performed on the initial hardware description information to obtain first hardware description information, including: Based on the standard unit cost coefficient model, the macro unit cost coefficient model, and the voltage drop of the power distribution network, the voltage drop cost coefficient model is determined. Virtual global cabling is performed based on standard cell characteristic constraint data, macro cell layout constraint data, and layout planning constraint data to determine the signal congestion cost coefficient model of the area surrounding the macro cell power supply interface and the densely interconnected area of ​​standard cells. Based on the voltage drop cost coefficient model, signal congestion cost coefficient model, standard cell cost coefficient model and macro cell cost coefficient model, the power distribution network-cell-signal coordination cost coefficient model is determined. Based on the signal congestion cost coefficient model and the power distribution network-unit-signal coordination cost coefficient model, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information.

[0010] In some embodiments, based on the signal congestion cost coefficient model and the power distribution network-unit-signal coordination cost coefficient model, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information, including: Based on the signal congestion cost coefficient model, congestion hotspots are identified in the area surrounding the macrocell power supply interface and in the densely interconnected area of ​​standard cells. Based on the power distribution network-unit-signal collaborative cost coefficient model, the congested sub-regions are determined in the area surrounding the macro-unit power supply interface and the densely interconnected area of ​​standard units; At least one congestion optimization operation is performed on the macrocells and standard cells corresponding to congestion hotspots and congestion sub-regions in the initial hardware description information until the optimized hardware description information meets a first preset condition. The optimized hardware description information is then used as the first hardware description information. The congestion optimization operation includes: Obtain the current hardware description information corresponding to the current congestion optimization operation, wherein the current hardware description information corresponding to the first congestion optimization operation is the initial hardware description information; Incremental optimization is performed on the macrocells and standard cells corresponding to congestion hotspots and congestion sub-regions in the current hardware description information to obtain candidate hardware description information. Update congestion hotspots and congestion sub-regions based on candidate hardware description information; If the updated congestion hotspots or updated congestion sub-regions are not eliminated, the macrocells and standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information are restructured respectively, and the resulting hardware description information is used as the current hardware description information for the next congestion optimization operation.

[0011] In some embodiments, structural reconstruction is performed on the macrocells and standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information, including: For the macrocells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information, the surrounding wiring channels are widened and / or the layout positions are adjusted. The standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information are disassembled and / or their layout density is reduced.

[0012] In some embodiments, optimization is performed based on physical design constraint data to obtain optimized physical design constraint data, including: Define the optimization space for physical design constraint data; Based on the macrocell layout adjustment cost, standard cell density adjustment cost, power distribution network-cell-signal collaborative cost coefficient model, power distribution network voltage drop and standard cell area, the optimization objective function is determined. The value of the objective function is calculated within the optimization space, and the physical design constraint data corresponding to the minimum objective function value is used as the optimized physical design constraint data.

[0013] In some embodiments, the physical design constraint data further includes power distribution network metal layer constraint data, and the method further includes: Based on the constraint data of the metal layer of the power distribution network and the resistance and capacitance of the metal layer of the power distribution network, a model for the cost coefficient of the metal layer resistance and capacitance is determined. Based on the cost coefficient model of metal layer resistance and capacitance, standard unit cost coefficient model and macro unit cost coefficient model, a unit-metal layer fusion cost coefficient model is obtained. Based on the multi-process angle and multi-operating mode MCMM constraint data in the constraint dataset, the first hardware description information is optimized using MCMM to obtain the second hardware description information, including: Based on the MCMM constraint data, macrocell cost coefficient model, standard cell cost coefficient model and cell-metal layer fusion cost coefficient model in the constraint dataset, the first hardware description information is optimized by MCMM to obtain the second hardware description information.

[0014] In some embodiments, based on MCMM constraint data, macrocell cost coefficient model, standard cell cost coefficient model, and cell-metal layer fusion cost coefficient model in the constraint dataset, the first hardware description information is optimized using MCMM to obtain the second hardware description information, including: Based on the MCMM constraint data in the constraint dataset, determine multiple MCMM combinations; A global optimization objective function is constructed based on standard cell timing margin, standard cell leakage current, standard cell area, macro cell cost coefficient model, and standard cell cost coefficient model. Based on the unit-metal layer fusion cost coefficient model, the unit-metal layer fusion cost coefficient corresponding to each MCMM combination is determined; Based on the unit-metal layer fusion cost coefficients corresponding to each MCMM combination, a cost coefficient linkage matrix is ​​determined. The first hardware description information is optimized at least once using the cost coefficient linkage matrix until the value of the global optimization objective function corresponding to the optimized first hardware description information is minimized. Then, the optimized first hardware description information is used as the second hardware description information.

[0015] In some embodiments, layout simulation and deviation calibration are performed based on third hardware description information and optimized physical design constraint data to obtain target hardware description information and target physical guidance information, including: Based on the third hardware description information and the optimized physical design constraint data, the initial physical guidance information is determined; Import the initial physical guidance information into the placement and routing tool to perform placement simulation and obtain the simulation timing, simulation area and simulation power consumption. Determine the actual timing, actual area, and actual power consumption of the third hardware description information; If the second preset condition is met based on the first deviation value between the actual timing and the simulated timing, the second deviation value between the actual area and the simulated area, and the third deviation value between the actual power consumption and the simulated power consumption, then the third hardware description information is used as the target hardware description information, and the initial physical guidance information is used as the target physical guidance information.

[0016] In some embodiments, the integrated circuit design method further includes: If it is determined that the second preset condition is not met based on the first deviation value, the second deviation value, and the third deviation value, then the unit-metal layer fusion cost coefficient model is adjusted based on the first deviation value, the second deviation value, and the third deviation value. The third hardware description information is optimized based on the adjusted unit-metal layer fusion cost coefficient model and the optimized physical design constraint data to obtain the target hardware description information and the target physical guidance information.

[0017] In some embodiments, the integrated circuit design method further includes: Based on standard cell timing criticality and macrocell layout constraint data, the optimization task is divided into critical subtasks and non-critical subtasks. Among them, the optimization task includes congestion optimization and MCMM optimization. Execute at least one subtask operation to obtain the result quality corresponding to the optimized hardware description information, until the result quality meets the third preset condition. The subtask operations include: Based on the hardware description information and unit-metal layer fusion cost coefficient model corresponding to the current subtask operation, the unit-metal layer fusion cost coefficient library for the current operation is obtained. The unit-metal layer fusion cost coefficient library is used to characterize the correspondence between standard units, macro units, metal layers and unit-metal layer fusion cost coefficients. Based on the current unit-metal layer fusion cost coefficient library, key sub-tasks are executed in the first processing core, non-key sub-tasks are executed in parallel in multiple second processing cores, and the result quality corresponding to the current optimized hardware description information is determined. If the quality of the result corresponding to the current optimized hardware description information does not meet the third preset condition, then the current optimized hardware description information will be used as the hardware description information corresponding to the next subtask operation.

[0018] According to a second aspect of the embodiments of this application, an electronic device is provided, including a processor and a memory, wherein the memory stores computer program instructions that can be executed by the processor, and when the processor executes the computer program instructions, it implements the steps of the method as described in any of the first aspects above.

[0019] According to a third aspect of the embodiments of this application, a computer-readable storage medium is provided, which stores computer program instructions that, when executed by a processor, cause the processor to perform the steps of the method as described in any of the first aspects above.

[0020] In this application, physical design constraint data, including standard cell characteristic constraint data, macrocell layout constraint data, and layout planning constraint data, is set in the constraint dataset of the integrated circuit. Based on this physical design constraint data, congestion optimization is performed on the standard cells and macrocells in the hardware description information, improving the relevance between front-end logic synthesis and back-end physical implementation. By setting MCMM constraint data in the constraint dataset, MCMM optimization is performed on the first hardware description information after congestion optimization, so that the second hardware description information after MCMM optimization can meet the stringent requirements of advanced manufacturing processes. By automatically optimizing the physical design constraint data and then performing congestion optimization on the second hardware description information, the reliance on the designer's physical design experience is reduced, and the design convergence efficiency is improved. By performing layout simulation and deviation calibration on the third hardware description information after further congestion optimization and the optimized physical design constraint data, accurate hardware description information and physical guidance information can be obtained, thereby avoiding a large number of secondary adjustments by the back-end placement and routing tools and improving the design efficiency of the integrated circuit.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 A flowchart illustrating a method for designing an integrated circuit according to some embodiments of this application is shown; Figure 2 A block diagram of an integrated circuit design system according to some embodiments of this application is shown; Figure 3 A schematic diagram of the structure of an electronic device according to some embodiments of this application is shown. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0026] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0027] Figure 1 A flowchart illustrating an integrated circuit design method according to some embodiments of this application is shown. Figure 1 As shown, an integrated circuit design method is provided, which may include the following steps: Step 101: Based on the physical design constraint data in the constraint dataset of the integrated circuit, perform congestion optimization on the initial hardware description information to obtain the first hardware description information. The physical design constraint data includes standard cell characteristic constraint data, macro cell layout constraint data, and layout planning constraint data. The hardware description information is used to characterize the connection relationship between circuit elements. The circuit elements include standard cells and macro cells. Step 102: Based on the multi-corner multi-mode (MCMM) constraint data in the constraint dataset, perform MCMM optimization on the first hardware description information to obtain the second hardware description information; Step 103: Optimize based on physical design constraint data to obtain optimized physical design constraint data; Step 104: Perform congestion optimization on the second hardware description information based on the optimized physical design constraint data to obtain the third hardware description information; Step 105: Based on the third hardware description information and the optimized physical design constraint data, perform layout simulation and deviation calibration to obtain target hardware description information and target physical guidance information, so as to design integrated circuits based on target hardware description information and target physical guidance information.

[0028] In step 101, the physical design constraint data is constraint data related to the back-end physical implementation, which may include standard cell characteristic constraint data, macro cell layout constraint data, layout planning constraint data, power distribution network metal layer constraint data, etc.

[0029] Among them, the standard cell characteristic constraint data is the constraint data related to the characteristics of the standard cell, which may include constraint data related to the standard cell's drive capability, timing, area, leakage current, and gate load.

[0030] Macrocell layout constraint data is the constraint data related to the layout of macrocells, which may include macrocell layout size, layout location, interface pin definition, wiring channel width, and power distribution network (PDN) power supply interface related constraint data.

[0031] Floorplan constraint data, also known as floorplan constraint data, can include constraint data related to the division of unit layout areas and unit density.

[0032] The power distribution network metal layer constraint data is constraint data related to the power distribution network metal layer, which may include constraint data related to the allocation of the power distribution network metal layer and IR voltage drop.

[0033] Hardware description information is used to characterize the connection relationships between circuit elements, including standard cells, macro cells, etc. The initial hardware description information can be synthesizable RTL code or an initial netlist. The first hardware description information to the target hardware description information can be an optimized netlist.

[0034] During implementation, RTL code, Liberty standard cell library, Liberty macro cell library, Milkyway physical library, basic constraint data (including SDC design constraints and UPF power constraints), standard cell characteristic constraint data, macro cell layout constraint data, power distribution network metal layer constraint data, layout planning constraint data, and MCMM constraint data can be imported through the interface. Then, all constraint data are format-validated and normalized to generate a constraint dataset and store it in the global data bus for subsequent steps to call.

[0035] It is understood that, in the logic synthesis process of this application embodiment, physical design constraint data related to the back-end physical implementation is added on the basis of the basic constraint data. Therefore, these physical design constraint data can be used to perform targeted congestion optimization on the standard cells and macro cells in the initial hardware description information, so that the optimized hardware description information is more in line with the needs of the back-end physical implementation.

[0036] In some embodiments, step 101 may include the following sub-steps: Step 1011: Based on the standard cell characteristic constraint data, macro cell layout constraint data, standard cell layout density, and macro cell interface pin density, determine the standard cell cost coefficient model and the macro cell cost coefficient model. Step 1012: Based on the layout planning constraint data, standard cell characteristic constraint data, macro cell layout constraint data, standard cell cost coefficient model and macro cell cost coefficient model, perform congestion optimization on the initial hardware description information to obtain the first hardware description information.

[0037] In step 1011, the standard cell cost coefficient model can be determined based on the standard cell characteristic constraint data, standard cell driving capability, standard cell leakage current, and standard cell layout density, respectively; and the macro cell cost coefficient model can be determined based on the macro cell layout constraint data, macro cell layout location, macro cell wiring channel width, and macro cell interface pin density.

[0038] Specifically, the standard unit cost coefficient model can refer to the following formula: Formula 1; in, The standard unit cost coefficient. This is a normalized value for the driving capability of the standard unit. This is the normalized value of the leakage current of the standard cell. This is the normalized value of the standard cell layout density. These are the weighting coefficients.

[0039] It should be noted that the normalized value of the standard unit driving capability in Formula 1... Normalized value of leakage current of standard unit It should meet the corresponding threshold specified in the standard unit characteristic constraint data.

[0040] The macro-unit cost coefficient model can refer to the following formula two: Formula 2; in, This is the cost coefficient for macrocells. This is the normalized value for the macrocell layout position. This is the normalized value for the macrocell interface pin density. This is the normalized value for the macrocell routing channel width. These are the weighting coefficients.

[0041] It should be noted that the normalized value of the macrocell layout position in Formula 2... Normalized value of macro unit wiring channel width The corresponding threshold specified in the macrocell layout constraint data should be met.

[0042] In some embodiments, the physical design constraint data may also include power distribution network metal layer constraint data. Based on the power distribution network metal layer constraint data, the resistance and capacitance of the power distribution network metal layer, a metal layer resistance and capacitance cost coefficient model can be determined. Based on the metal layer resistance and capacitance cost coefficient model, the standard cell cost coefficient model, and the macro cell cost coefficient model, a cell-metal layer fusion cost coefficient model can be obtained.

[0043] The cost coefficient model for the metal layer resistance and capacitance can be referenced from the following formula three: Formula 3; in, This represents the cost coefficient for the metal layer's resistance and capacitance. For the first The resistance of the layer metal, For the first The capacitance value of the layer metal, Resistance weighting coefficients for process adaptation. The capacitor weighting coefficient is adapted to the process.

[0044] It should be noted that in Formula 3, the first... Resistance of the layer metal and the capacitance of the layer metal The corresponding threshold specified in the power distribution network metal layer constraint data should be met.

[0045] The cost coefficient model for unit-metal layer fusion can refer to the following formula four: Formula 4; in, The cost coefficient for unit-metal layer fusion. This is a weighting factor for the cost coefficient of the metal layer resistance and capacitance. The weighting factor for the standard unit cost coefficient. This is the weighting factor for the macro-unit cost coefficient. , , , The specific value can be configured based on various factors, such as dynamic configuration based on MCMM optimization objectives (timing / leakage current / area).

[0046] The cost coefficient of unit-metal layer fusion By associating with the corresponding standard cells, macrocells, and metal layers, a cell-metal layer fusion cost coefficient library that incorporates physical effects can be generated. This library can be stored on the global data bus for later use.

[0047] In step 1012, a voltage drop cost coefficient model can be determined based on the standard cell cost coefficient model, the macro cell cost coefficient model, and the power distribution network voltage drop; virtual global routing can be performed based on standard cell characteristic constraint data, macro cell layout constraint data, and layout planning constraint data to determine the signal congestion cost coefficient model for the area surrounding the macro cell power supply interface and the densely interconnected area of ​​standard cells; a power distribution network-cell-signal coordination cost coefficient model can be determined based on the voltage drop cost coefficient model, the signal congestion cost coefficient model, the standard cell cost coefficient model, and the macro cell cost coefficient model; and congestion optimization can be performed on the initial hardware description information based on the signal congestion cost coefficient model and the power distribution network-cell-signal coordination cost coefficient model to obtain the first hardware description information.

[0048] The voltage drop cost coefficient model can refer to the following formula five: Formula 5; in, This is the voltage drop cost factor. The normalized value for the voltage drop across the power distribution network (i.e., the IR drop value of the PDN). Weighting factors for voltage drop in power distribution networks. The weighting factor for the macro-unit cost coefficient. This is the weighting factor for the standard unit cost coefficient.

[0049] The signal congestion cost coefficient model can refer to the following formula six: Formula Six; in, This is the signal congestion cost coefficient. Number of cabling requirements Number of available cabling resources This is the congestion adaptation coefficient.

[0050] The power distribution network-unit-signal coordination cost coefficient model can refer to the following formula seven: Formula 7; in, The cost factor for power distribution network-unit-signal coordination. The weighting factor is the standard unit cost coefficient. The weighting factor for the macro-unit cost coefficient. .

[0051] You can set the threshold for the power distribution network-unit-signal coordination cost coefficient. ,when The area was identified as a region of congestion.

[0052] Understandably, the power distribution network-cell-signal co-cost coefficient model integrates the coupling relationship between the dynamic IR voltage drop, macrocell layout, and standard cell density of 3D PDN, thus enabling more accurate identification of congestion superposition areas in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells.

[0053] In some embodiments, congestion hotspots in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells can be determined based on a signal congestion cost coefficient model; congestion sub-regions in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells can be determined based on a power distribution network-cell-signal coordination cost coefficient model; at least one congestion optimization operation is performed on the macrocells and standard cells corresponding to the congestion hotspots and congestion sub-regions in the initial hardware description information until the optimized hardware description information meets a first preset condition, and then the optimized hardware description information is used as the first hardware description information. The congestion optimization operation includes: obtaining the congestion optimization operation corresponding to the current operation. The current hardware description information is used, where the current hardware description information corresponding to the first congestion optimization operation is the initial hardware description information. Incremental optimization is performed on the macrocells and standard cells corresponding to the congestion hotspots and congestion sub-regions in the current hardware description information to obtain candidate hardware description information. The congestion hotspots and congestion sub-regions are updated based on the candidate hardware description information. If the updated congestion hotspots or updated congestion sub-regions are not eliminated, the macrocells and standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information are restructured, and the resulting hardware description information is used as the current hardware description information for the next congestion optimization operation.

[0054] Specifically, based on finite element analysis, the dynamic IR voltage drop of 3D PDN under different macrocell layouts and standard cell densities can be simulated, and the corresponding voltage drop cost coefficient can be obtained using a voltage drop cost coefficient model. By employing virtual global cabling technology and a signal congestion cost coefficient model, the signal congestion cost coefficients are calculated for the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells. The congestion hotspots in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells are marked according to the signal congestion cost coefficient. Then, the signal congestion cost coefficients in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​standard cells are calculated. and voltage drop cost coefficient Substituting into the power distribution network-unit-signal coordination cost coefficient model, we obtain the corresponding power distribution network-unit-signal coordination cost coefficient. ,if Power distribution network - unit - signal coordination cost coefficient threshold If the floorplan, macrocell layout, or standard cell density are adjusted, the IR drop can be re-simulated and updated. It also redefines and labels congestion hotspots and congestion sub-regions, and stores the labeling results to the global data bus.

[0055] After identifying congestion hotspots and congestion sub-regions, incremental optimization can be performed on the macrocells and standard cells corresponding to the congestion hotspots and congestion sub-regions in the current hardware description information to obtain candidate hardware description information. Specifically, for standard cells, incremental optimization can be performed through cell mapping → gate-level optimization → layer-aware buffer insertion. For macrocells, incremental optimization can be performed through peripheral routing channel adjustment → interface pin optimization → layout boundary adaptation. Cell mapping optimization can be: mapping logic cells in the current hardware description information to standard cells in the physical implementation. There can be multiple types of standard cells as candidates. Gate-level optimization can be: selecting the most suitable standard cell from the standard cell library to replace or map logic functions based on the optimization goals and constraints of PPA (performance, power, area). Layer-aware buffer insertion optimization can be: predicting latency by pre-setting the metal layer allocation. Inserting buffers based on latency will be more accurate. It should be noted that traditional logic synthesis tools do not consider the metal layer allocation during physical implementation, so the synthesized result differs significantly from the physical implementation result. This application reduces the difference between the synthesized result and the physical implementation result by inserting layer-aware buffers.

[0056] After obtaining the candidate hardware description information, virtual global routing can be re-executed and the calculations can be recalculated. The congestion hotspots and congestion sub-regions are updated. If the updated congestion hotspots or congestion sub-regions are not eliminated, the macrocells corresponding to the updated congestion hotspots or congestion sub-regions in the candidate hardware description information can be widened in terms of surrounding wiring channels and / or their layout positions adjusted. The standard cells corresponding to the updated congestion hotspots or congestion sub-regions in the candidate hardware description information can be disassembled and / or their layout density reduced. If all the updated congestion hotspots and congestion sub-regions are eliminated, the optimized hardware description information is used as the first hardware description information. Otherwise, the congestion optimization operation is repeated until all the updated congestion hotspots or congestion sub-regions are eliminated.

[0057] By updating congestion hotspots and congestion sub-regions in real time during the comprehensive optimization process, and performing dynamic congestion adaptation for standard cell interconnection topology and macro cell peripheral wiring based on the updated congestion hotspots and congestion sub-regions, dynamic closed-loop optimization of congestion is achieved, reducing the physical implementation risk of hardware description information.

[0058] In step 102, MCMM optimization can be performed on the standard cells and macro cells in the first hardware description information based on the MCMM constraint data, macro cell cost coefficient model, standard cell cost coefficient model and cell-metal layer fusion cost coefficient model in the constraint dataset.

[0059] Understandably, the unit-metal layer fusion cost coefficient model quantitatively integrates the core characteristics of standard units and macro units with the physical characteristics of metal layers, and this model has a higher degree of matching with the actual physical characteristics under advanced processes.

[0060] In some embodiments, multiple MCMM combinations can be determined based on MCMM constraint data in the constraint dataset; a global optimization objective function can be constructed based on standard cell timing margin, standard cell leakage current, standard cell area, macrocell cost coefficient model, and standard cell cost coefficient model; the cell-metal layer fusion cost coefficient corresponding to each MCMM combination can be determined based on the cell-metal layer fusion cost coefficient model; a cost coefficient linkage matrix can be determined based on the cell-metal layer fusion cost coefficient corresponding to each MCMM combination; and the first hardware description information can be optimized by MCMM at least once based on the cost coefficient linkage matrix until the value of the global optimization objective function corresponding to the optimized first hardware description information is minimized, at which point the optimized first hardware description information is used as the second hardware description information.

[0061] Among them, the MCMM combination is a combination of the number of modes and the number of process corners. Taking the modes including m1 and m2 and the process corners including c1, c2 and c3 as an example, the MCMM combination can be m1c1, m1c2, m1c3, m2c1, m2c2, m2c3.

[0062] The global optimization objective function can be referenced from the following formula eight: Formula 8; in, This is the normalized value of the timing margin of the standard cell. This is the normalized value of the leakage current of the standard cell. This is the normalized value of the area of ​​a standard unit. These are configurable weighting coefficients. .

[0063] The cost coefficient linkage matrix can be referenced from the following formula nine: Formula Nine; in, For the number of patterns, This refers to the number of process corners. For the first Type of mode, first The unit-metal layer fusion cost coefficient for each process corner can be dynamically weighted across modes and process corners through coupling coefficients between matrix elements.

[0064] Specifically, the standard cell timing margin T and standard cell leakage current of each MCMM combination can be... Standard unit area A, macro unit cost coefficient Standard unit cost coefficient The values ​​are normalized to the interval [0,1] and a global optimization objective function is constructed based on the normalized values; a cost coefficient linkage matrix M is established based on MCMM constraint data. m×c When performing optimization of a certain MCMM combination, through M m×c Simultaneously adjust the unit-metal layer fusion cost coefficient C of other MCMM combinations. UMRC For standard cells, the timing and leakage current characteristics of multiple process corners are optimized. For macro cells, the layout constraints of multiple modes are adapted. Based on the global optimization objective function F, the optimization is iteratively optimized until F reaches its minimum value. The first hardware description information optimized by MCMM is used as the second hardware description information.

[0065] Through the process of "target normalization → construction of linkage matrix → dynamic optimization", global optimization of standard cells and macro cells across modes and process corners is achieved, so that the second hardware description information can achieve a global optimal balance of timing, leakage current and area under advanced process.

[0066] In step 103, the physical design constraint data can be optimized using an optimization function.

[0067] In some embodiments, an optimization space for physical design constraint data can be defined; an optimization objective function is determined based on macrocell layout adjustment cost, standard cell density adjustment cost, power distribution network-cell-signal collaborative cost coefficient model, power distribution network voltage drop, and standard cell area; the value of the optimization objective function is calculated within the optimization space, and the physical design constraint data corresponding to the minimum value of the optimization objective function is used as the optimized physical design constraint data.

[0068] Specifically, the adjustable range of each constraint data in the physical design constraint data can be determined, which can be used as the optimization space. An optimization objective function with congestion elimination, minimum IR voltage drop, and optimal area as the core can be constructed, and the unit adjustment cost can be included in the penalty term.

[0069] The following formula (Formula 10) can be used as a reference for finding the optimal objective function: Formula 10; in, The cost factor for power distribution network-unit-signal coordination. This is the normalized value of the IR dropout of the PDN. This is the normalized value of the area of ​​a standard unit. This is the area weighting coefficient. To reduce the cost of macrocell layout adjustments, This is a weighting factor for the cost of macrocell layout adjustments. Adjusting costs for standard cell density, This is the weighting factor for adjusting the cost of standard unit density.

[0070] Genetic algorithms can be used to iteratively optimize within the optimization space. In each iteration, the value of the optimization objective function is calculated, focusing on matching the fit between the macrocell layout position and the density of the surrounding standard cells, until the global optimal solution with the minimum value of the optimization objective function is found. The physical design constraint data corresponding to the optimal solution is then used as the optimized physical design constraint data.

[0071] By designing an optimization objective function aimed at congestion elimination, minimizing IR voltage drop, and optimizing area, an intelligent algorithm is used to achieve iterative optimization of multiple parameters, replacing the traditional manual floorplan exploration and reducing reliance on the physical design experience of designers.

[0072] In some embodiments, the optimization task can be divided into critical subtasks and non-critical subtasks based on standard cell timing criticality and macrocell layout constraint data. The optimization task includes congestion optimization and MCMM optimization. At least one subtask operation is performed to obtain the result quality corresponding to the optimized hardware description information until the result quality meets a third preset condition. The subtask operation includes: obtaining a current unit-metal layer fusion cost coefficient library based on the hardware description information corresponding to the current subtask operation and the unit-metal layer fusion cost coefficient model. This unit-metal layer fusion cost coefficient library is used to characterize the correspondence between standard cells, macrocells, metal layers, and unit-metal layer fusion cost coefficients. Based on the current unit-metal layer fusion cost coefficient library, critical subtasks are executed in a first processing core, and non-critical subtasks are executed in parallel in multiple second processing cores. The result quality corresponding to the current optimized hardware description information is determined. If the result quality corresponding to the current optimized hardware description information does not meet the third preset condition, the current optimized hardware description information is used as the hardware description information corresponding to the next subtask operation.

[0073] It is understandable that after each critical or non-critical subtask is completed, the hardware description information will change, and the parameters of the unit-metal layer fusion cost coefficient model (metal layer resistance and capacitance cost coefficient, standard unit cost coefficient, and macro unit cost coefficient) obtained based on the hardware description information will also change. This will cause the unit-metal layer fusion cost coefficient to change, and consequently the unit-metal layer fusion cost coefficient library will also change.

[0074] The timing critical path in the standard unit and the optimization tasks of the core interface in the macro unit can be divided into critical subtasks. The optimization tasks for non-critical paths in standard cells and peripheral routing outside the core of macrocells are divided into non-critical subtasks. Key sub-tasks Non-critical subtasks will be assigned to independent cores for execution. The optimization is distributed across multiple cores for parallel execution. Each core can access the cell-metal layer fusion cost coefficient library corresponding to the current subtask operation from the global data bus. It synchronously executes differentiated optimization strategies for standard cells and macrocells with the goal of minimizing the cell-metal layer fusion cost coefficient, and the optimization data from each core is synchronized to the global data bus in real time. After each critical subtask is executed in an independent core or a non-critical subtask in multiple cores, the optimized hardware description information is obtained, and the corresponding Quality of Results (QoR) is calculated. This QoR typically includes multiple metrics such as timing, power consumption, and area. If the QoR meets a third preset condition (e.g., the deviation from the timing, power consumption, and area calculated by the backend physical routing tool is less than a preset threshold), the optimization results from the multiple cores are fused, and the optimized hardware description information is output. If the QoR does not meet the third preset condition, the subtask needs to be re-executed based on the cell-metal layer fusion cost coefficient library corresponding to the optimized hardware description information.

[0075] By dividing the optimization tasks based on standard cell timing criticality and macrocell layout constraints, the rationality of the optimization task division is improved. By using multi-core parallel execution of non-critical sub-tasks, the execution time of the optimization tasks is effectively shortened. QoR verification ensures that the various indicators of the optimized hardware description information do not exceed the expected deviation range.

[0076] In step 104, congestion optimization is performed on the second hardware description information based on the optimized physical design constraint data until congestion is completely eliminated. This yields the third hardware description information and the optimal parameters (i.e., backend placement and routing adaptation parameters) corresponding to the optimized physical design constraint data. The specific congestion optimization steps can be found in the preceding description and will not be repeated here.

[0077] In step 105, the physical guidance information may include basic information (target hardware description information, fusion cost coefficient library, power distribution network-cell-signal co-cost coefficient model) and cell-level fine-grained information (standard cell optimization characteristic table, macro cell layout constraint table). The standard cell optimization characteristic table includes optimization results such as the driving capability, timing / leakage current, and layout density of standard cells, while the macro cell layout constraint table includes constraint data such as macro cell layout position, interface pins, and routing channels.

[0078] In some embodiments, performing layout simulation and deviation calibration based on third hardware description information and optimized physical design constraint data to obtain target hardware description information and target physical guidance information may include: determining initial physical guidance information based on third hardware description information and optimized physical design constraint data; importing the initial physical guidance information into a placement and routing tool for layout simulation to obtain simulation timing, simulation area, and simulation power consumption; determining the actual timing, actual area, and actual power consumption of the third hardware description information; if a second preset condition is met based on a first deviation value between the actual timing and the simulation timing, a second deviation value between the actual area and the simulation area, and a third deviation value between the actual power consumption and the simulation power consumption, then the third hardware description information is used as the target hardware description information, and the initial physical guidance information is used as the target physical guidance information.

[0079] During implementation, initial physical guidance information can be extracted from the third hardware description information and the optimized physical design constraint data. The initial physical guidance information is then imported into a backend placement and routing tool (such as IC Compiler) to perform rapid placement simulation, obtaining simulation timing, simulation area, and simulation power consumption. By performing timing, area, and power consumption analysis on the third hardware description information, the actual timing, actual area, and actual power consumption can be obtained. The difference between the actual timing and the simulation timing is then used as the first deviation value, the difference between the actual area and the simulation area is used as the second deviation value, and the difference between the actual power consumption and the simulation power consumption is used as the third deviation value.

[0080] The second preset condition can be designed according to the actual situation. For example, it can be that the first deviation value is less than the first threshold, the second deviation value is less than the second threshold, and the third deviation value is less than the third threshold, or the first deviation value, the second deviation value, and the third deviation value are all less than the same threshold.

[0081] Taking a threshold of 3% as an example, if the first deviation value, the second deviation value, and the third deviation value are all less than 3%, then the second preset condition can be determined to be met. If any one of the deviation values ​​is greater than or equal to 3%, then the second preset condition is determined not to be met.

[0082] If the second condition is met, the third hardware description information and the initial physical guidance information are used as the final result; otherwise, further optimization is required.

[0083] In some embodiments, if it is determined that the second preset condition is not met based on the first deviation value, the second deviation value, and the third deviation value, the unit-metal layer fusion cost coefficient model is adjusted based on the first deviation value, the second deviation value, and the third deviation value; the third hardware description information is optimized based on the adjusted unit-metal layer fusion cost coefficient model and the optimized physical design constraint data to obtain the target hardware description information and the target physical guidance information.

[0084] Understandably, if it is determined that the second preset condition is not met, the first deviation value, the second deviation value, and the third deviation value can be fed back to the unit-metal layer fusion cost coefficient model, and the weight coefficients in the unit-metal layer fusion cost coefficient model can be adjusted based on the deviation values. Then, by using the adjusted unit-metal layer fusion cost coefficient model and optimized physical design constraint data, congestion optimization and MCMM optimization are performed on the third hardware description information to obtain the final results, namely the target hardware description information, the target physical guidance information, and the back-end layout and routing adaptation parameters.

[0085] The input data for the integrated circuit design method of this application may include advanced process RTL code, cell libraries, physical libraries, and various design constraints. The output may include target hardware description information, target physical guidance information, and back-end placement and routing adaptation parameters. During the logic synthesis stage of the digital EDA front-end tool, these parameters are used for refined mapping of standard cells and macrocells. The output information can be passed as input to the back-end placement and routing tool to accurately guide the physical implementation process of the integrated circuit.

[0086] By designing a refined physical guidance information output specification and a deviation closed-loop calibration mechanism for synthesis and physical implementation, refined physical guidance information including a standard cell optimization characteristic table and a macro cell placement constraint table is output. Furthermore, an execution process for deviation quantification and model correction is designed, which significantly reduces the timing, area, and power consumption correlation between synthesis and placement.

[0087] This application improves the relevance between front-end logic synthesis and back-end physical implementation by setting physical design constraint data, including standard cell characteristic constraint data, macrocell layout constraint data, and layout planning constraint data, in the constraint dataset of integrated circuits. Based on this physical design constraint data, congestion optimization is performed on standard cells and macrocells in the hardware description information. By setting MCMM constraint data in the constraint dataset and performing MCMM optimization on the congestion-optimized first hardware description information, the MCMM-optimized second hardware description information can meet the stringent requirements of advanced manufacturing processes. By automatically optimizing the physical design constraint data before performing congestion optimization on the second hardware description information, the reliance on the designer's physical design experience is reduced, improving design convergence efficiency. By performing layout simulation and deviation calibration on the congestion-optimized third hardware description information and the optimized physical design constraint data, accurate hardware description information and physical guidance information can be obtained, thereby avoiding a large number of secondary adjustments in the back-end placement and routing tools and improving the design efficiency of integrated circuits.

[0088] The following describes an apparatus embodiment of this application, which can be used to execute the integrated circuit design method in the above embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the integrated circuit design method described above.

[0089] See Figure 2 This illustrates a block diagram of an integrated circuit design system according to an embodiment of this application. Figure 2 As shown, the integrated circuit design system of this application embodiment includes: a first optimization module 201, used to perform congestion optimization on initial hardware description information based on physical design constraint data in the constraint dataset of the integrated circuit to obtain first hardware description information, wherein the physical design constraint data includes standard cell characteristic constraint data, macrocell layout constraint data and layout planning constraint data, and the hardware description information is used to characterize the connection relationship between circuit elements, and the circuit elements include standard cells and macrocells; a second optimization module 202, used to perform MCMM optimization on the first hardware description information based on multi-process corner and multi-operating mode MCMM constraint data in the constraint dataset to obtain second hardware description information; an automatic optimization module 203, used to perform optimization based on the physical design constraint data to obtain optimized physical design constraint data; the first optimization module 201 is also used to perform congestion optimization on the second hardware description information based on the optimized physical design constraint data to obtain third hardware description information; and a deviation calibration module 204, used to perform layout simulation and deviation calibration based on the third hardware description information and the optimized physical design constraint data to obtain target hardware description information and target physical guidance information, so as to design the integrated circuit based on the target hardware description information and target physical guidance information.

[0090] Each module can share information in real time through a global data bus. The entire process uses standard units and macro units as the core operation objects and can be seamlessly integrated into existing EDA toolchains.

[0091] Based on the same inventive concept, this application also provides an electronic device, see reference. Figure 3 The diagram shows a schematic of the structure of an electronic device according to an embodiment of this application. The electronic device includes one or more memories 304, one or more processors 302, and at least one computer program (computer program instruction) stored in the memory 304 and executable on the processor 302. When the processor 302 executes the computer program, it implements the method described above.

[0092] Among them, Figure 3In this document, a bus architecture (represented by bus 300) is used. Bus 300 may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 302 and memory represented by memory 304. Bus 300 may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 305 provides an interface between bus 300 and receiver 301 and transmitter 303. Receiver 301 and transmitter 303 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 302 is responsible for managing bus 300 and general processing, while memory 304 can be used to store data used by processor 302 during operation.

[0093] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the method described above.

[0094] Based on the same inventive concept, embodiments of this application provide a computer program product, including a computer program, which, when executed by a processor, causes the processor to perform the steps of the method described above.

[0095] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Furthermore, the functional units may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0097] The units described as separate components may or may not be physically separate. Similarly, the components of the control device may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0098] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program instructions, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0099] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for designing an integrated circuit, characterized in that, include: Based on the physical design constraint data in the constraint dataset of integrated circuits, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information. The physical design constraint data includes standard cell characteristic constraint data, macro cell layout constraint data, and layout planning constraint data. The hardware description information is used to characterize the connection relationship between circuit elements, and the circuit elements include standard cells and macro cells. Based on the MCMM constraint data of multiple process angles and multiple working modes in the constraint dataset, the first hardware description information is optimized by MCMM to obtain the second hardware description information. Optimization is performed based on the physical design constraint data to obtain optimized physical design constraint data; Based on the optimized physical design constraint data, the second hardware description information is congested to obtain the third hardware description information. Based on the third hardware description information and the optimized physical design constraint data, layout simulation and deviation calibration are performed to obtain target hardware description information and target physical guidance information, so as to design the integrated circuit based on the target hardware description information and target physical guidance information.

2. The integrated circuit design method according to claim 1, characterized in that, The physical design constraint data in the integrated circuit-based constraint dataset is used to perform congestion optimization on the initial hardware description information to obtain the first hardware description information, including: Based on the standard cell characteristic constraint data, the macro cell layout constraint data, the standard cell layout density, and the macro cell interface pin density, the standard cell cost coefficient model and the macro cell cost coefficient model are determined. Based on the layout planning constraint data, the standard cell characteristic constraint data, the macro cell layout constraint data, the standard cell cost coefficient model, and the macro cell cost coefficient model, congestion optimization is performed on the initial hardware description information to obtain the first hardware description information.

3. The integrated circuit design method according to claim 2, characterized in that, The process of determining the standard cell cost coefficient model and the macro cell cost coefficient model based on the standard cell characteristic constraint data, the macro cell layout constraint data, the standard cell layout density, and the macro cell interface pin density includes: Based on the standard cell characteristic constraint data, standard cell driving capability, standard cell leakage current and standard cell layout density, the standard cell cost coefficient model is determined. Based on the macrocell layout constraint data, macrocell layout position, macrocell wiring channel width, and macrocell interface pin density, the macrocell cost coefficient model is determined.

4. The integrated circuit design method according to claim 2, characterized in that, The first hardware description information is obtained by performing congestion optimization on the initial hardware description information based on the layout planning constraint data, the standard cell characteristic constraint data, the macro cell layout constraint data, the standard cell cost coefficient model, and the macro cell cost coefficient model, including: Based on the standard unit cost coefficient model, the macro unit cost coefficient model, and the voltage drop of the power distribution network, the voltage drop cost coefficient model is determined. Virtual global cabling is performed based on the standard unit characteristic constraint data, the macro unit layout constraint data, and the layout planning constraint data to determine the signal congestion cost coefficient model of the area surrounding the macro unit power supply interface and the dense interconnection area of ​​standard units. Based on the voltage drop cost coefficient model, the signal congestion cost coefficient model, the standard cell cost coefficient model, and the macro cell cost coefficient model, the power distribution network-cell-signal coordination cost coefficient model is determined. Based on the signal congestion cost coefficient model and the power distribution network-unit-signal coordination cost coefficient model, the initial hardware description information is optimized for congestion to obtain the first hardware description information.

5. The integrated circuit design method according to claim 4, characterized in that, The initial hardware description information is congestion optimized based on the signal congestion cost coefficient model and the power distribution network-unit-signal coordination cost coefficient model to obtain the first hardware description information, including: Based on the signal congestion cost coefficient model, the congestion hotspots in the area surrounding the macrocell power supply interface and the densely interconnected area of ​​the standard cells are determined. Based on the power distribution network-unit-signal collaborative cost coefficient model, the congested sub-regions in the area surrounding the macro unit power supply interface and the densely interconnected area of ​​the standard unit are determined. At least one congestion optimization operation is performed on the macrocells and standard cells corresponding to the congestion hotspots and congestion sub-regions in the initial hardware description information until the optimized hardware description information meets a first preset condition. Then, the optimized hardware description information is used as the first hardware description information. The congestion optimization operation includes: Obtain the current hardware description information corresponding to the current congestion optimization operation, wherein the current hardware description information corresponding to the first congestion optimization operation is the initial hardware description information; Incremental optimization is performed on the macrocells and standard cells corresponding to congestion hotspots and congestion sub-regions in the current hardware description information to obtain candidate hardware description information. The congestion hotspots and congestion sub-regions are updated based on the candidate hardware description information; If the updated congestion hotspot or the updated congestion sub-region is not eliminated, the macrocells and standard cells corresponding to the updated congestion hotspots or the updated congestion sub-regions in the candidate hardware description information are restructured respectively, and the resulting hardware description information is used as the current hardware description information for the next congestion optimization operation.

6. The integrated circuit design method according to claim 5, characterized in that, The structural reconstruction of the macrocells and standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information includes: The macrocells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information are widened in terms of surrounding wiring channels and / or their layout positions are adjusted. The standard cells corresponding to the updated congestion hotspots or updated congestion sub-regions in the candidate hardware description information are disassembled and / or their layout density is reduced.

7. The integrated circuit design method according to claim 4, characterized in that, The optimization based on the physical design constraint data to obtain optimized physical design constraint data includes: Define the optimization space for the physical design constraint data; Based on the macrocell layout adjustment cost, standard cell density adjustment cost, the power distribution network-cell-signal collaborative cost coefficient model, the power distribution network voltage drop, and the standard cell area, the optimization objective function is determined. The value of the objective function is calculated within the optimization space, and the physical design constraint data corresponding to the minimum objective function value is used as the optimized physical design constraint data.

8. The integrated circuit design method according to claim 2, characterized in that, The physical design constraint data also includes power distribution network metal layer constraint data, and the method further includes: Based on the power distribution network metal layer constraint data, the resistance and capacitance of the power distribution network metal layer, determine the metal layer resistance and capacitance cost coefficient model; Based on the metal layer resistance-capacitance cost coefficient model, the standard unit cost coefficient model, and the macro unit cost coefficient model, a unit-metal layer fusion cost coefficient model is obtained. The first hardware description information is optimized using MCMM constraints based on the multi-process angle and multi-operating mode constraints in the constraint dataset to obtain the second hardware description information, including: Based on the MCMM constraint data in the constraint dataset, the macrocell cost coefficient model, the standard cell cost coefficient model, and the cell-metal layer fusion cost coefficient model, the first hardware description information is optimized using MCMM to obtain the second hardware description information.

9. The integrated circuit design method according to claim 8, characterized in that, The second hardware description information is obtained by performing MCMM optimization on the first hardware description information based on the MCMM constraint data in the constraint dataset, the macrocell cost coefficient model, the standard cell cost coefficient model, and the cell-metal layer fusion cost coefficient model, including: Based on the MCMM constraint data in the constraint dataset, multiple MCMM combinations are determined; A global optimization objective function is constructed based on the standard cell timing margin, standard cell leakage current, standard cell area, the macro cell cost coefficient model, and the standard cell cost coefficient model. Based on the unit-metal layer fusion cost coefficient model, determine the unit-metal layer fusion cost coefficient corresponding to each MCMM combination; Based on the unit-metal layer fusion cost coefficients corresponding to each MCMM combination, a cost coefficient linkage matrix is ​​determined. Based on the cost coefficient linkage matrix, the first hardware description information is optimized at least once using MCMM until the value of the global optimization objective function corresponding to the optimized first hardware description information is minimized. Then, the optimized first hardware description information is used as the second hardware description information.

10. The integrated circuit design method according to claim 8, characterized in that, The layout simulation and deviation calibration based on the third hardware description information and optimized physical design constraint data yield target hardware description information and target physical guidance information, including: Based on the third hardware description information and the optimized physical design constraint data, the initial physical guidance information is determined; The initial physical guidance information is imported into the placement and routing tool for placement simulation to obtain simulation timing, simulation area and simulation power consumption. Determine the actual timing, actual area, and actual power consumption of the third hardware description information; If, based on the first deviation value between the actual timing and the simulated timing, the second deviation value between the actual area and the simulated area, and the third deviation value between the actual power consumption and the simulated power consumption, it is determined that the second preset condition is met, then the third hardware description information is used as the target hardware description information, and the initial physical guidance information is used as the target physical guidance information.

11. The integrated circuit design method according to claim 10, characterized in that, Also includes: If it is determined that the second preset condition is not met based on the first deviation value, the second deviation value, and the third deviation value, then the unit-metal layer fusion cost coefficient model is adjusted based on the first deviation value, the second deviation value, and the third deviation value. The third hardware description information is optimized based on the adjusted unit-metal layer fusion cost coefficient model and the optimized physical design constraint data to obtain the target hardware description information and target physical guidance information.

12. The integrated circuit design method according to claim 8, characterized in that, Also includes: Based on the timing criticality of standard cells and the macrocell layout constraint data, the optimization task is divided into critical subtasks and non-critical subtasks, wherein the optimization task includes congestion optimization and MCMM optimization. Execute at least one subtask operation to obtain the result quality corresponding to the optimized hardware description information, until the result quality meets a third preset condition, wherein the subtask operation includes: Based on the hardware description information corresponding to the current subtask operation and the unit-metal layer fusion cost coefficient model, the unit-metal layer fusion cost coefficient library for the current operation is obtained. The unit-metal layer fusion cost coefficient library is used to characterize the correspondence between standard units, macro units, metal layers and unit-metal layer fusion cost coefficients. Based on the current unit-metal layer fusion cost coefficient library, key sub-tasks are executed in the first processing core, non-key sub-tasks are executed in parallel in multiple second processing cores, and the result quality corresponding to the current optimized hardware description information is determined. If the quality of the result corresponding to the current optimized hardware description information does not meet the third preset condition, then the current optimized hardware description information will be used as the hardware description information corresponding to the next subtask operation.

13. An electronic device comprising a processor and a memory, characterized in that, The memory stores computer program instructions that can be executed by the processor, and when the processor executes the computer program instructions, it implements the steps of the method as described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, cause the processor to perform the steps of the method as described in any one of claims 1 to 12.

Images