FPGA / CPLD-based LED matrix electronic sand table technology demonstration system and method

Abstract

The application relates to an FPGA / CPLD-based LED matrix electronic sand table technology demonstration system, which is constructed as a modular hardware system supporting multi-field technology demonstration content visualization presentation and physical construction, and comprises a power supply module, a communication module, an input module and a pure combinational logic circuit. The pure combinational logic circuit generates multi-dimensional space coordinates in parallel according to input data, and synchronously outputs addressing signals and driving signals for multiple target display units in an LED matrix. The system and method realize multi-dimensional orthogonal parallel addressing of the pure combinational logic, and realize spatial-time dual embodiment presentation of underlying mechanisms such as instruction execution, data flow and algorithm process.

Description

Technical Field

[0001] This invention relates to the field of electronic information, and specifically to an LED matrix electronic sand table technology demonstration system and method based on FPGA / CPLD. Background Technology

[0002] In fields such as digital circuits, FPGA (Field-Programmable Gate Array) programming, CPLD (Complex Programmable Logic Device), microcomputer principles (including RISC-V architecture), and image processing, technology demonstration devices are important tools and carriers for scientific and technological research and development. Currently, the industry commonly adopts technical approaches such as modular experimental boxes, FPGA development boards, CPU technology platforms, or PC software simulation systems. Traditional digital circuit experimental boxes are based on discrete components or small- to medium-scale integrated circuits with fixed functions. They verify basic units such as logic gates, flip-flops, and counters by connecting wires. Mainstream FPGA technology demonstration platforms are based on FPGA chips and integrate basic peripherals such as LEDs, buttons, digital tubes, and seven-segment displays. Operators observe the functional output after writing Verilog / VHDL code and burning it. RISC-V technology demonstration equipment mostly adopts soft-core or hard-core IP integration solutions, relying on development boards to run instruction set simulators or lightweight operating systems, and using serial port printing or waveform viewing tools to present the execution results. Technology demonstrations in the field of image processing mainly rely on software environments such as Matlab and OpenCV to complete algorithm modeling and simulation. Some hardware platforms support mapping algorithms to FPGA acceleration, but ultimately only display static images or video frames before and after processing on an LCD screen.

[0003] However, all of the aforementioned technology demonstration devices share a common technical limitation: their hardware structure and information presentation methods cannot support a comprehensive expression of the macroscopic, dynamic, spatial, and visual technical attributes of the underlying technological processes. Specifically, this manifests in several ways: digital circuit experimental boxes lack spatial mapping capabilities for signal timing and node states; while FPGA development boards are programmable, their internal logic construction process is invisible, and peripheral control relationships are opaque; RISC-V technology demonstration platforms struggle to physically separate and present pipeline stages such as instruction fetching, decoding, execution, and write-back, requiring observers to infer instruction flow indirectly through abstract logs or waveforms; and image processing systems cannot demonstrate key hardware execution processes such as neighborhood sliding window construction, pixel data transfer, and parallel computing paths, leaving the technology demonstration at the "input-output" black box level, failing to establish a complete chain from "code → hardware circuit → physical phenomenon." Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an LED matrix electronic sand table technology demonstration system and method based on FPGA / CPLD, which can support a new curvature compensation mechanism for single-temperature high-efficiency calibration.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An LED matrix electronic sand table technology demonstration system based on FPGA / CPLD is disclosed. The system is configured as a modular hardware system supporting the visualization and physical construction of multi-domain technology demonstration content. The system includes a power supply module, a communication module, an input module, and a pure combinational logic circuit. The pure combinational logic circuit generates multi-dimensional spatial coordinates in parallel based on input data and synchronously outputs addressing signals and driving signals for multiple target display units in the LED matrix.

[0007] The core components of the system include at least a RISC-V processor physical core unit, which includes at least four functional modules: an instruction fetch module, a decode module, an execution module, and a write-back module. These four functional modules are independently packaged and physically connectable. Each of the four functional modules has built-in soft or hard core logic and is equipped with a visual indicator component corresponding to each instruction pipeline stage. The indicator component includes a color LED array and a digital tube, used to synchronously display in real time the instruction field, operand address, ALU operation type, and target register identifier processed in the current stage. By connecting the four modules and using a clock, the pipelined operation of each instruction under clock support can be confirmed, and the perpendicular orthogonality between the data pipeline and the instruction pipeline can be achieved.

[0008] A method for demonstrating LED matrix electronic sand table technology based on FPGA / CPLD is used for technology demonstrations in the fields of digital circuits, FPGA programming, RISC-V microprocessor principles, and image processing. The method is characterized by generating multi-dimensional spatial coordinates in parallel based on input data using pure combinational logic circuits, synchronously outputting addressing and driving signals for multiple target display units in the LED matrix, and achieving perpendicular orthogonality between the data pipeline and the instruction pipeline. The method includes the following collaboratively executed steps:

[0009] (1) Physical construction technology demonstration topology: At least one module of the multi-dimensional LED visualization array unit, TCON timing-decoding co-control unit, RISC-V processor physical core unit and input unit are detachably spliced ​​by magnetic attraction or snap-fit ​​to form a hardware architecture for technology demonstration in a specific field;

[0010] (2) Configure the visual mapping relationship: Write pixel data corresponding to the spatial coordinates of the LED beads to the coordinate pool of the TCON timing-decoding co-control unit through the host computer software, and set the scanning cycle parameters; at the same time, burn the corresponding function code to each module of the RISC-V processor physical core unit, so that the instruction fetch module, decoding module, execution module and write-back module respectively establish the real-time mapping of instruction field, operand address, ALU operation status and target register identifier with their respective LED beads / digital tubes;

[0011] (3) Start the dynamic demonstration process: Under the clock drive, the TCON unit generates a logical coordinate sequence according to the coordinate pool data and outputs a strobe signal after static decoding, driving the LED array to light up point by point; each module of RISC-V runs synchronously, and its LED beads and digital tubes are displayed in high brightness level by level as the instruction stream progresses, realizing the spatialization, timing and visualization of the instruction execution process;

[0012] (4) Interactive intervention and feedback: The LED array and the visualization components of each of the four modules respond synchronously by adjusting the scanning frequency, switching the coordinate sequence, triggering instruction jumps or updating cache pool data through the input unit.

[0013] This application achieves a good spatial-temporal visualization of core technology processes in the field of electronic information by constructing a deeply integrated system of modular and reconfigurable hardware architecture and multi-dimensional LED matrix visualization mapping. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall system architecture of this application.

[0015] Figure 2 This is a schematic diagram of the electronic circuit connection of the two-dimensional lamp array in this application.

[0016] Figure 3 This is a schematic diagram of the electronic circuit connection of the three-dimensional lamp array in this application.

[0017] Figure 4 This is a schematic diagram of the lamp array control component TCON of this application.

[0018] Figure 5 This is a circuit diagram showing a 12-bit output generated by cascading three 74LS161 cores to adapt to two-dimensional lamp array addressing.

[0019] Figure 6 This is a circuit diagram showing a 12-bit output generated by cascading three 74LS161 cores to adapt to three-dimensional lamp array addressing.

[0020] Figure 7 This is a parameter diagram of the example color to be presented.

[0021] Figure 8 This is a schematic diagram of a lightweight RISC-V physical core.

[0022] Figure 9 This is a diagram showing the instruction field division of the decoding module.

[0023] Figure 10 is a schematic diagram of a single-core RISC-V signal processing system.

[0024] Figure 11 This is a schematic diagram of a multi-core RISC-V signal processing system. Detailed Implementation

[0025] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] In existing technologies, current industry solutions employ sequential logic for serial gating (including clock, enable, and master-slave control), which is a "pseudo-high-dimensional low-dimensional stack." Furthermore, the industry commonly uses fixed topologies and unidirectional functional verification modes, preventing technicians from intuitively understanding core mechanisms such as digital circuit signal transmission paths, FPGA internal logic construction processes, how RISC-V instructions are progressively implemented in hardware, and how the underlying data flow of image processing algorithms slides and operates in space. Especially in multi-domain integrated technology demonstration scenarios, a single device struggles to meet the requirements of different domains regarding visualization granularity, interaction depth, and architectural flexibility.

[0027] The technical solution of this invention truly achieves "logically orthogonal high-dimensionality," achieving innovative breakthroughs in the technical solution itself, core logic, and technical effects. Specifically, this invention uses pure combinational logic without clocks, registers, or enable signals to realize multi-dimensional addressing. All dimension decoders work in parallel and synchronously based on a unified address bus, and the output signals have no sequential timing relationship. Multi-dimensional address information is input in parallel at once through a single address bus, and the address bits of each dimension are independently orthogonally distributed on the bus, without a batch or staged address transmission process. Each addressing dimension (layer / row / column / scheduling / heat dissipation, etc.) is an equal and orthogonal logical dimension, without master-slave control or enable dependency. Dimension expansion is achieved only by increasing the number of address bus bits and decoders, without changing the core logic of combinational parallelism.

[0028] An LED matrix electronic sand table technology demonstration system based on FPGA / CPLD is disclosed. The system is configured as a modular hardware system supporting the visualization and physical construction of multi-domain technology demonstration content. The system includes a power supply module, a communication module, an input module, and a pure combinational logic circuit. The pure combinational logic circuit generates multi-dimensional spatial coordinates in parallel based on input data and synchronously outputs addressing signals and driving signals for multiple target display units in the LED matrix.

[0029] The core components of the system include at least a RISC-V processor physical core unit, which comprises at least four functional modules: an instruction fetch module, a decode module, an execution module, and a write-back module. These four functional modules are independently packaged and physically interconnected. Each module has built-in soft or hard core logic and is equipped with a visual indicator component corresponding to each instruction pipeline stage. The indicator component includes a color LED array and a digital tube, used to synchronously display in real time the instruction fields, operand addresses, ALU operation types, and target register identifiers processed in the current stage. By connecting the four modules and using a clock, the pipelined operation of each instruction under clock support can be confirmed, and the data pipeline and instruction pipeline can be perpendicularly orthogonal.

[0030] In addition to the RISC-V processor physical core unit, the core components of the system include at least the following functional units coupled to the RISC-V processor physical core unit: a multi-dimensional LED visualization array unit, a TCON timing-decoding co-control unit, a modular physical reconfiguration interface unit, and a host computer co-programming unit. Specifically:

[0031] (1) Multi-dimensional LED visualization array unit (referred to as lamp array, acting as an output peripheral), which includes LED bead units. See [link to relevant documentation] Figure 2 and Figure 3It is configured as a two-dimensional, three-dimensional or N-dimensional topology, and each lamp unit contains at least two independently driveable light-emitting sub-pixels for mapping digital circuit status, instruction address, register data, neighboring pixel values ​​or algorithm intermediate results into visible light points with spatial coordinates and color / grayscale attributes, wherein the spatial coordinates are X / Y / Z coordinates;

[0032] Preferably, in the multi-dimensional LED visualization array unit, each LED bead unit includes no less than two independently driven light-emitting sub-pixels; the driving signal of each sub-pixel is directly controlled by the data bits stored in the buffer pool of the TCON timing-decoding co-control unit corresponding to the spatial coordinates, so that the same LED bead unit can synchronously present multiple technical demonstration semantic information in the same scanning cycle, wherein at least one sub-pixel is used to display the register address identifier, another sub-pixel is used to display the data value corresponding to the address, and a third sub-pixel is used to display the data valid status flag.

[0033] Preferably, the multi-dimensional LED visualization array unit supports N-dimensional expansion, where N is an integer greater than or equal to 2; the TCON timing-decoding co-control unit is configured with N independent static decoding sub-units, each corresponding to the coordinate decoding output of N orthogonal dimensions; when N=2, the N static decoding sub-units are row decoders and column decoders; when N=3, the N static decoding sub-units are layer decoders, row decoders, and column decoders; when N>3, each additional dimension adds a corresponding set of static decoding sub-units, and the outputs of all N sets of decoding sub-units jointly complete the unique selection of a single LED unit.

[0034] See Figure 2 The number of color LED units is calculated as follows: (R×C = 64×64 = 4096 units). Each unit integrates three LED chips with red, green, and blue primary colors respectively. Figure 2 Taking the scale shown as an example, when the COM terminal is high and at least one of the red, green, and blue primary color terminals is low, it indicates that this LED unit is... Figure 1 The decoder output is selected, and component analysis begins. This is to ensure that the selected LED can continuously measure for a period of time without affecting other LED units. [The following is a separate, unrelated instruction:] ... Figure 2 A common diode is connected in series between the positive terminal of the LED and the decoding output, and a charging and discharging capacitor is connected in parallel across each LED chip.

[0035] Each LED unit has one group (3 LEDs per group) of tri-color taps controlled by the Y-axis and one group (only one COM terminal tap per group) of taps controlled by the X-axis. A two-dimensional LED array of this scale has:

[0036] 64 groups (3 taps per group, used to control red, green and blue lights respectively) of row taps connected to the output of the row decoder (Y-axis decoder);

[0037] 64 groups (1 tap per group) of column taps that connect to the output of the column decoder (X-axis decoder).

[0038] The principle of lighting the lamp is as follows: (where 0≤i≤63; 0≤j≤63)

[0039] When all three outputs in the j-th group of the row decoder are active low, and only one output in the i-th group of the column decoder is active high, the LED units in the j-th row and i-th column are lit up, emitting white light;

[0040] When only the red terminal of the red, green, and blue control terminals in the j-th group of the row decoder is at a valid low level (the others are at a high level), and only one output in the i-th group of the column decoder is at a valid high level, the LED units in the j-th row and i-th column are lit up, emitting red light.

[0041] See Figure 3 The number of color LED units is calculated as follows: (R×C = 64×64 = 4096 units). Each unit integrates three LED chips with red, green, and blue primary colors respectively. Figure 2 Taking the scale shown as an example, when the COM terminal is high and at least one of the red, green, and blue primary color terminals is low, it indicates that this LED unit is... Figure 1 The decoder output is selected, and component analysis begins. This is to ensure that the selected LED can continuously measure for a period of time without affecting other LED units. [The following is a separate, unrelated instruction:] ... Figure 2 A common diode is connected in series between the positive terminal of the LED and the decoding output, and a charging and discharging capacitor is connected in parallel across each LED chip.

[0042] Each LED unit has one group (3 LEDs per group) of tri-color taps controlled by the Y-axis and one group (only one COM terminal tap per group) of taps controlled by the X-axis. A two-dimensional LED array of this scale has:

[0043] 64 groups (3 taps per group, used to control red, green and blue lights respectively) of row taps connected to the output of the row decoder (Y-axis decoder);

[0044] 64 groups (1 tap per group) of column taps that connect to the output of the column decoder (X-axis decoder).

[0045] The principle of lighting the lamp is as follows: (where 0≤i≤63; 0≤j≤63)

[0046] When all three outputs in the j-th group of the row decoder are active low, and only one output in the i-th group of the column decoder is active high, the LED units in the j-th row and i-th column are lit up, emitting white light;

[0047] When only the red terminal of the red, green, and blue control terminals in the j-th group of the row decoder is at a valid low level (the others are at a high level), and only one output in the i-th group of the column decoder is at a valid high level, the LED units in the j-th row and i-th column are lit up, emitting red light.

[0048] (2) The TCON timing-decoding co-control unit, integrated in the programmable logic device, includes a dynamic timing generation subunit and a static decoding subunit. The dynamic timing generation subunit contains a counter, a coordinate pool, and a buffer pool, used to generate scan cycles, logical coordinate sequences, and corresponding pixel data. The static decoding subunit responds to the logical coordinates and outputs row, column, and layer strobe signals, using a small number of standardized general-purpose I / O interfaces to achieve precise addressing and time-division lighting of an exponential number of LED beads in the multi-dimensional LED visualization array unit. The TCON timing-decoding co-control unit can be spliced ​​and finally fixed to the main body of the device by magnetic attraction (or some kind of snap-fit). The ports in the module can also be connected by flying wires to achieve different functions. New target code can be downloaded and burned to the host computer to change the internal circuit of each module unit.

[0049] (a) Dynamic timing generation subunit

[0050] The dynamic timing generation subunit consists of three parts: a counter, a coordinate pool, and a buffer pool. Each module and submodule can be spliced ​​together and finally fixed to the main body of the device by magnetic attraction (or some kind of snap-fit), and the ports in the module can also be connected by flying wires.

[0051] The counter can be composed of several sub-counting modules (this embodiment uses the 74LS161 core, but other models or custom cores can also be used) and a small amount of glue logic (this embodiment uses AND gates) cascaded together.

[0052] Furthermore, the coordinate pool in the dynamic timing generation subunit is a dual-port synchronous RAM structure. Its write port is connected to the host computer collaborative programming unit via the communication module, and its read port is connected to the input terminal of the static decoding subunit. The address depth of the coordinate pool is equal to the total number of pixels in the multi-dimensional LED visualization array unit. Each address unit stores no less than one byte of data, which is used to define the grayscale values ​​of the red, green, and blue components of the corresponding pixel, or for one or more of the following: status identifiers, neighborhood sliding window identifiers, and input unit event types in the encoding instruction pipeline stage.

[0053] Figure 5 and Figure 6The 12-bit output is generated by cascading three 74LS161 cores. From the most significant bit to the least significant bit, they correspond to cnt[11:0]. This 12-bit address space can be adapted to address two types of two-dimensional and three-dimensional light arrays using the coordinate pool output:

[0054] Form 1 (two-dimensional), see Figure 5 This adapts to addressing 64 × 64 = 4096 LED units (rows × columns):

[0055] cnt[5:0] corresponds to X[5:0], the total addressing depth is 64, and X_pos[63:0] is addressed;

[0056] cnt[11 : 6] corresponds to Y[5 : 0], the total addressing depth is 64, and Y_pos[63 : 0] is addressed.

[0057] Form 2 (three-dimensional), see Figure 6 This adapts to addressing 16×16×16 = 4096 LED units (layer × row × column).

[0058] cnt[3:0] corresponds to X[3:0], the total addressing depth is 16, and X_pos[15:0] is addressed;

[0059] cnt[7:4] corresponds to Y[3:0], the total addressing depth is 16, and Y_pos[15:0] is addressed;

[0060] cnt[15 : 8] corresponds to Z[3 : 0], the total addressing depth is 16, and Z_pos[15 : 0] is addressed.

[0061] The cache pool caches the data that needs to be displayed for each pixel corresponding to cnt [11 : 0]. Each pixel is composed of three sub-pixels: red, green, and blue. Each color sub-pixel can be represented by a single bit to achieve equal brightness color (by arranging a total of 8 colors: black, white, red, green, blue, red-green, red-blue, green-blue), or by multiple bits to achieve richer colors (for example, to present the orange of Figure J, each sub-pixel is represented by 8 bits). At this time, R[7 : 0] = 239, G[7 : 0] = 133, B[7 : 0] = 17. Then R[7 : 0], G[7 : 0], and B[7 : 0] are converted into PWM waves with duty cycles of 239 / 256≈0.94, 133 / 256≈0.52, and 17 / 256≈0.07, respectively, and then output to the R, G, and B terminals of the LED unit through three lines.

[0062] (b) Static decoding subunit

[0063] Each output port of the static decoding subunit is connected to the LED bead driving circuit of the corresponding dimension by a level shaping circuit. The level shaping circuit includes a silicon diode connected in series with the output signal line and an electrolytic capacitor connected in parallel with the anode-cathode of the LED bead. The forward voltage drop of the diode is not less than 0.6V, which is used to block the cross conduction current between non-target rows / columns / layers. The capacitance of the electrolytic capacitor is 10μF±20%, which is used to maintain the voltage fluctuation across the LED bead within 10% of the rated value in a single scan cycle, thereby ensuring the brightness consistency under human visual observation.

[0064] Figure 4 COL decoding, ROW decoding, and LVL decoding respectively decode the column coordinates, row coordinates, and layer coordinates into values ​​that point to the specific location of the LED unit. The output bit width is exactly a multiple of 2 to the power of n. For example,

[0065] For form one above, to decode row 15 and column 9, the inputs for ROW decoding and COL decoding are as follows:

[0066] Y[5 : 0]=15, X[5 : 0]= 9; At this time,

[0067] In Y_pos[63 : 0], the 15th signal line is valid, and the other signal lines are invalid;

[0068] In X_pos[63 : 0], the 9th signal line is valid, and the other signal lines are invalid.

[0069] For form two above, if we want to decode the 11th layer, the 15th row, and the 9th column, the inputs for ROW decoding and COL decoding are as follows:

[0070] Z[3 : 0]=11, Y[3 : 0]=15, X[3 : 0]= 9; At this time,

[0071] In Z_pos[15 : 0], the 11th signal line is valid, and the other signal lines are invalid;

[0072] In Y_pos[15 : 0], the 15th signal line is valid, and the other signal lines are invalid;

[0073] In X_pos[15 : 0], the 9th signal line is valid, and the other signal lines are invalid.

[0074] (3) The RISC-V processor physical core unit consists of four independently packaged and physically connectable functional modules: instruction fetch module, decoding module, execution module, and write-back module. See [link to relevant documentation]. Figure 8 Each module has a built-in lightweight RISC-V soft core or hard core logic, and is equipped with a visual indicator component that corresponds one-to-one with the instruction pipeline stage. The indicator component includes a color LED array and a digital tube, which are used to display in real time the instruction field, operand address, ALU operation type and target register identifier processed in the current stage.

[0075] Preferably, the instruction fetch module, decoding module, execution module, and write-back module of the RISC-V processor physical core unit are each packaged in an independent physical housing; each housing has 32 colored LED beads arranged in a 4x8 matrix on the front, and a set of 8 seven-segment digital tubes; each housing has a standardized mechanical and electrical composite interface on the back, with a pin pitch of 2.54mm and a 3.3V TTL compatible level standard, and supports precise alignment and splicing with adjacent modules through magnetic array or snap-fit ​​structure; the signal pins between modules allow users to make arbitrary cross-module connections through external flying wires.

[0076] Preferably, each module is physically detachable. They can be assembled and ultimately fixed to the main body of the device via magnetic attraction (or some kind of snap-fit). The ports within the modules can also be connected by jumper wires to achieve different functions. New target code can be downloaded and programmed into a host computer to modify the internal circuitry of each module. (Note: A single device can contain multiple physical cores as described above, thus achieving a "many-core parallel" architecture.)

[0077] Preferably, the casing of each module includes the following display components: 32 colored LED beads, a grid-like filament surrounding each LED bead, and a set of eight seven-segment displays [d3.1]. In addition to displaying numbers, the seven-segment displays can also display English letters. For example, the ADD instruction will display "Add".

[0078] (a) Instruction fetch module

[0079] The instruction fetch module divides the lower 7-bit OPCODE area and other areas according to the RISC-V protocol, using a grid of fine filaments surrounding each LED bead. Inside the value fetch module, besides the necessary display control section, there is only one 32-bit D flip-flop. The 32 color LED beads and one group of eight seven-segment displays [d4.1] show the output results of the D flip-flops.

[0080] (b) Decoding module:

[0081] The decoding circuit in the decoding module decodes the opcode. For example, if the decoded instruction is an R-class instruction [d5.1], then it is executed according to... Figure 9The areas are divided as shown.

[0082] For example (using the addition instruction add x5, x1, x2):

[0083] • opcode = 0110011 (indicates this is an R class instruction);

[0084] •rs1 = 00001 (corresponding to source operand register x1, the first operand);

[0085] •rs2 = 00010 (corresponds to source operand register x2, the second operand);

[0086] • funct3 = 000 (in conjunction with opcode, it represents "addition and subtraction operations");

[0087] • funct7 = 0000000 (used with funct3 to represent "addition");

[0088] •rd = 00101 (corresponds to destination operand register x5, the result is written to x5).

[0089] (c) Execution module:

[0090] The execution module uses LEDs and a seven-segment display to highlight the addresses of rs1 and rs2 according to the decoding result from the decoding module in the previous cycle. It then addresses these addresses in the general-purpose registers and performs the corresponding operation by calling the ALU. The values ​​of the 32 32-bit general-purpose registers are mapped one-to-one with a specific area in the cache pool mentioned above, allowing them to be displayed in a specific area of ​​the LED array.

[0091] Preferably, the output of the arithmetic logic unit (ALU) of the execution module is directly connected to the input of the target register address decoder in the write-back module via a 32-bit parallel data bus; each signal line of the 32-bit parallel data bus corresponds to an LED on the front of the execution module housing, used to synchronously display the binary bit status of the ALU output result in real time; the seven-segment display of the write-back module synchronously displays the target register number written to by the current ALU operation result, which is generated by decoding the rd field output by the decoding module.

[0092] (d) Write-back module:

[0093] The write-back module uses LED beads and seven-segment displays to highlight the address of rd based on the decoding results from the decoding module in the first two cycles. Simultaneously, it addresses 32 32-bit general-purpose registers and writes the results calculated by the ALU into the relevant areas of these registers. The results can then be displayed in a specific area of ​​the LED array.

[0094] By correctly connecting the four modules and the clock, users can observe the pipelined operation of each instruction under the support of the clock. If a data stream flows through all 32 32-bit general-purpose registers at this time, the data pipeline and the instruction pipeline can be vertically orthogonal.

[0095] (e) Communication module:

[0096] This refers to the data transmission part with the host computer software. The host computer software can monitor the entire device via a data cable, and can also burn the compiled target code into the device to change its functionality. After the device is updated with the new target code, it can be used independently of the host computer software.

[0097] (4) Modular physical reconstruction interface unit, configured as magnetic, snap-on or plug-in mechanical connection structure, so that the multi-dimensional LED visualization array unit, TCON timing-decoding co-control unit, RISC-V processor physical core unit and input unit can be physically spliced ​​in a detachable, rearrangeable and fly-wire-expandable manner to construct a topology for technical demonstration of different technical principles;

[0098] Furthermore, the mechanical connection form of the modular physical reconfiguration interface unit can also be selected from one of the following: bolt fastening type, guide rail sliding type, flexible printed circuit board plug-in type, or near-field resonant wireless coupling type; when using near-field resonant wireless coupling type, each module has a built-in LC resonant coil with an operating frequency of 6.78MHz±10kHz, which transmits electrical energy and low-speed control signals simultaneously through electromagnetic induction, with a control signal rate of not less than 115.2kbps, and can complete module power supply and command synchronization without any physical wire connection.

[0099] Buttons and knobs serve as input units. The default functions are adjustment of direction, reset, and clock frequency. Users can also program the internal circuitry of the FPGA (CPLD) to achieve other functions.

[0100] (5) The host computer collaborative programming unit receives and synchronously burns the target configuration code to at least two functional modules in the TCON timing-decoding collaborative control unit and the RISC-V processor physical core unit through the communication module, so that the internal logic of each module can be dynamically reconfigured, and after the burning is completed, the technology demonstration system can run the configured technology demonstration function independently without the host computer.

[0101] Among them, the host computer software is a software similar to Xilinx's Vivado, which can monitor the status of each module in the device in real time and download the target code to multiple modules.

[0102] Taking FPGA as an example, the working principle is as follows: After the system is powered on, the FPGA completes the configuration, the TCON unit starts the dynamic timing generation subunit, the counter outputs cnt[11:0] in a loop, the coordinate pool outputs the corresponding pixel data to the buffer pool according to the current address, the static decoding subunit decodes the high bits (Z / Y) and low bits (X) of cnt into layer / row / column strobe signals respectively, driving the LED array to light up point by point in the ZYX order; at the same time, each module of RISC-V runs according to its own clock domain, the instruction fetch module reads the 32-bit instruction from the instruction memory and sends it to the LED array for display, and the decoding module highlights the rs1 / rs2 / rd fields after parsing the OPCODE. In response to the LED, the execution module selects the ALU operation based on function 3 / function 7 and outputs the result to the LED array. The write-back module writes the ALU result to the target register and displays the rd number on the digital tube. The user sends direction commands via the steering wheel buttons. After parsing, the TCON unit updates the cursor position coordinates in the coordinate pool, and the LED array highlights the new coordinate point in real time. The knob adjusts the encoder output frequency, and the TCON unit dynamically adjusts the counter division ratio, thereby changing the scan frame rate. The host computer sends new configuration codes via USB / Ethernet. Each module controller receives and reloads its internal logic, realizing the function switching from adder to multiplier and from single-cycle to four-stage pipeline.

[0103] Furthermore, a method for demonstrating LED matrix electronic sand table technology based on FPGA / CPLD is provided for demonstrating technologies in the fields of digital circuits, FPGA programming, RISC-V microprocessor principles, and image processing. The method is characterized by generating multi-dimensional spatial coordinates, completing synchronous addressing and execution signal output for multiple target display units in the LED matrix within the same system clock cycle, and achieving perpendicular orthogonality between the data pipeline and the instruction pipeline. The method also includes the following collaboratively executed steps:

[0104] (1) Physical construction technology demonstration topology: At least one module of the multi-dimensional LED visualization array unit, TCON timing-decoding co-control unit, RISC-V processor physical core unit and input unit are detachably spliced ​​by magnetic attraction or snap-fit ​​to form a hardware architecture for technology demonstration in a specific field;

[0105] (2) Configure the visual mapping relationship: Write pixel data corresponding to the spatial coordinates of the LED beads to the coordinate pool of the TCON timing-decoding co-control unit through the host computer software, and set the scanning cycle parameters; at the same time, burn the corresponding function code to each module of the RISC-V processor physical core unit, so that the instruction fetch module, decoding module, execution module and write-back module respectively establish the real-time mapping of instruction field, operand address, ALU operation status and target register identifier with their respective LED beads / digital tubes;

[0106] (3) Start the dynamic demonstration process: Under the clock drive, the TCON unit generates a logical coordinate sequence according to the coordinate pool data and outputs a strobe signal after static decoding, driving the LED array to light up point by point; each module of RISC-V runs synchronously, and its LED beads and digital tubes are displayed in high brightness level by level as the instruction stream progresses, realizing the spatialization, timing and visualization of the instruction execution process;

[0107] (4) Interactive intervention and feedback: The LED array and the visualization components of each of the four modules respond synchronously by adjusting the scanning frequency, switching the coordinate sequence, triggering instruction jumps or updating cache pool data through the input unit.

[0108] In step (1), when the multidimensional LED visualization array unit is a two-dimensional structure, the row decoder and column decoder are spliced ​​together; when the multidimensional LED visualization array unit is a three-dimensional structure, the row decoder, column decoder and layer decoder are spliced ​​together, and the outputs of the three sets of decoders are used to complete the unique selection of a single LED unit; in the N-dimensional structure, each additional dimension adds a set of decoder modules corresponding to the dimension.

[0109] The pixel data written to the coordinate pool in step (2) contains multi-channel grayscale information, wherein the red channel data is mapped to the register address encoding, the green channel data is mapped to the general-purpose register value, and the blue channel data is mapped to the valid flag bit, so that the same LED unit can synchronously present the address, data and status triple technical demonstration semantics in the same scanning cycle.

[0110] The ALU operation result output by the execution module of the RISC-V processor physical core unit in step (3) is directly connected to the input of the target register address decoder of the write-back module through a 32-bit parallel bus, and each bit of the bus signal illuminates the corresponding LED bead on the LED array of the execution module in real time; the digital tube of the write-back module synchronously refreshes the target register number written.

[0111] In step (3), the dynamic timing generation subunit of the TCON timing-decoding cooperative control unit generates a non-sequential coordinate sequence, enabling the LED array to perform out-of-order scanning display, which is used to demonstrate asynchronous timing, race conditions, or nondeterministic system behavior.

[0112] The interactive intervention in step (4) includes adjusting the counter clock frequency by turning a knob to make the LED array scanning frame rate continuously adjustable within a preset frequency range, and simultaneously observing the visual persistence effect critical point and pipeline throughput changes.

[0113] The output signal of the input unit in step (4) is decoded by the TCON unit and used to dynamically update the current cursor position coordinates in the coordinate pool, drive the corresponding pixel of the LED array to be highlighted with a specified color, and realize the demonstration of spatial coordinate mapping technology under human-machine collaboration.

[0114] In step (2), the host computer software can download and burn new target code to change the internal circuit of each module unit.

[0115] The dynamic demonstration process in step (3) supports dual pipeline orthogonal collaboration: the TCON unit drives the LED array to build a data pipeline and executes neighborhood sliding window data transfer; the RISC-V processor physical core unit synchronously executes image processing instructions; the two pipelines are perpendicular and orthogonal in space and periodically aligned in time, and the LED array synchronously displays the original image area and the processing result area, presenting a parallel computing mechanism.

[0116] Furthermore, the technical solution of this invention relates to some typical business processes, see [link to relevant documentation]. Figure 10 , Figure 11 The following description uses examples.

[0117] Experiment 01: Line-by-line scanning and random scanning of light arrays

[0118] Step 1: The two-dimensional / three-dimensional light array, the light array control component TCON, the power supply module and the communication connector are assembled by magnetic attraction / snap fastening, and the hardware operates independently;

[0119] Step 2: Burn the scanning control code into the TCON module via the host computer software, or configure the parameters directly via buttons / knobs;

[0120] Step 3: Inject data into the TCON coordinate pool in the same order as the counter, and the light array will be displayed line by line.

[0121] Step 4: Inject data into the coordinate pool that is different from the counter's counting order, and the light array will achieve randomized scanning and display;

[0122] Step 5: Adjust the counter clock frequency by turning the knob, observe the changes in scanning speed, and demonstrate the timing control principle in real time.

[0123] Experiment 02: Controlling the movement of the light array cursor with the steering wheel

[0124] Step 1: Assemble the light array, TCON, input unit (steering wheel), power supply module, and communication section;

[0125] Step 2: The host computer programs the cursor control code, defining the coordinate adjustment logic for the eight directions of the steering wheel (↑, ↓, ←, →, ↖, ↗, ↙, ↘);

[0126] Step 3: Press a direction key on the steering wheel to input the control signal from the unit to TCON;

[0127] Step 4: After receiving the signal, TCON adjusts the coordinates of the target pixel in the coordinate pool (increasing / decreasing in the corresponding direction).

[0128] Step 5: After the coordinates are updated, the TCON drives the corresponding pixels of the light array to light up, realizing the cursor movement demonstration and intuitively showing the relationship between input control and coordinate mapping.

[0129] Experiment 03: Loading files using a cache pool to display dynamic images

[0130] Step 1: Connect the LED array, TCON, power supply module, and communication module to the host computer;

[0131] Step 2: Import dynamic image files (such as GIFs or video frame sequences) into the host computer, and divide and encode the image pixel data according to the size of the light array;

[0132] Step 3: Write the encoded pixel data into the TCON buffer pool via the host computer and update it frame by frame;

[0133] Step 4: TCON drives the light array to display frame by frame according to the data in the cache pool, realizing dynamic image playback and demonstrating the principle of data caching and frame refresh;

[0134] Step 5: Adjust the playback frame rate using the buttons, observe the changes in the smoothness of the light array display, and understand the relationship between buffering and display speed.

[0135] Experiment 04: Constructing a Data Pipeline Neighborhood Sliding Window by Scanning Line by Line of a Light Array

[0136] Step 1: Assemble the LED array, TCON, RISC-V core (single core), power supply module, and communication module;

[0137] Step 2: The host computer programs the neighborhood sliding window control code and configures the sliding window size (e.g., 3×3) and scanning step size;

[0138] Step 3: Start progressive scan, the TCON counter generates coordinate signals, and the coordinate pool outputs coordinates in the scan order;

[0139] Step 4: The buffer pool caches the current pixel and neighboring pixel data according to the sliding window size, forming a data pipeline;

[0140] Step 5: The RISC-V kernel reads the sliding window data, performs simple operations (such as mean filtering), and writes the results back to the cache pool;

[0141] Step 6: The light array synchronously displays the original scanned image and the filtered image, intuitively demonstrating the data pipeline and the neighborhood sliding window construction process.

[0142] Experiment 05: Building a four-stage pipeline for single-core and multi-core RISC-V (see...) Figure 10-11 )

[0143] Step 1: Assemble the four modules of the RISC-V core: instruction fetch, decode, execute, and write back. Connect the power supply module and communication module. For single-core architecture, simply assemble the modules. For multi-core architecture, multiple core modules need to be added and connected to the coordination signal.

[0144] Step 2: The host computer programs the pipeline control code and configures the clock frequency and instruction sequence (such as the add, sub, and and instruction combinations).

[0145] Step 3: Start the system and observe the instruction flow through the LEDs and digital tubes of each module: the fetch module displays the current fetch result → the decode module highlights the decode area → the execution module indicates the operand address and ALU operation → the write-back module indicates the target register and the write result;

[0146] Step 4: Adjust the clock frequency and observe the changes in pipeline throughput; under a multi-core architecture, display the instruction execution status of each core through an LED array to demonstrate the multi-core collaboration mechanism.

[0147] Experiment 06: Building a Dual Pipeline Signal Processing System with Data Stream and Instruction Stream

[0148] Step 1: Assemble the RISC-V core (multi-core), TCON, LED array, input unit, power supply module, and communication module;

[0149] Step 2: The host computer programs the dual-pipeline control code and configures the collaborative logic between the instruction pipeline (RISC-V kernel executes arithmetic instructions) and the data pipeline (TCON processes LED array pixel data);

[0150] Step 3: The input unit (camera) acquires image data and transmits it to the TCON buffer pool to form a data stream;

[0151] Step 4: The RISC-V kernel executes image processing instructions (such as edge detection), with the instruction stream and data stream perpendicular and orthogonal, and processed in parallel;

[0152] Step 5: The processing results are displayed through an LED array. The LED beads of each module and the digital tube synchronously display the collaborative process of the dual pipeline, demonstrating the principle of parallel processing.

[0153] It should be understood that any business process descriptions provided above are intended to exemplify the technical solutions of the present invention, rather than to exhaustively list all application scenarios of the present invention. Those skilled in the art, based on an understanding of the core ideas of the present invention, can fully conceive of other variations of these examples or apply them to other business types not explicitly listed.

[0154] Furthermore, for some modules of the technical demonstration system of the present invention, there are also feasible alternative solutions, and all of these alternative solutions can achieve the core objective of the present invention.

[0155] 1. Alternatives for LED array size and type: This solution uses a 64×64 two-dimensional LED array and a 16×16×16 three-dimensional LED array. Alternative solutions can be adjusted to 32×32 or 128×128 two-dimensional LED arrays, or 8×8×8 or 32×32×32 three-dimensional LED arrays, depending on the technical demonstration requirements. Alternatively, a monochrome LED array (suitable for basic technical demonstrations) or an RGBW four-primary-color LED array (to enhance color richness) can be used. As long as pixel-level visual display can be achieved, any form of LED array implementation is acceptable.

[0156] 2. Counter Core Alternatives: This solution uses the 74LS161 core. Alternative solutions include other counter cores such as the 74LS163 and CD4060, or custom logic counters. As long as the coordinate signals that can be adapted to the lamp array addressing can be used as the implementation form of the counter.

[0157] 3. Replacement of RISC-V kernel module: This solution adopts a four-stage pipeline (fetch, decode, execute, write back). The alternative solution can be adjusted to a three-stage or five-stage pipeline. The number of kernels can be increased or decreased according to the technical demonstration needs. It can realize RISC-V instruction execution and visualization demonstration, and can be used as an implementation form of RISC-V kernel.

[0158] 4. Alternatives to module connection methods: This solution uses magnetic and snap-fit ​​connections. Alternative solutions include bolt fixing, slot connections, etc. As long as the module can be detached and reconfigured, it can be used as a module connection method.

[0159] 5. Input module type alternatives: This solution includes buttons, knobs, and cameras. Alternative solutions can include touchpads, voice modules, infrared sensors, etc. As long as human-computer interaction and data input can be achieved, they can be used as input peripherals.

[0160] 6. Alternatives for host computer communication methods: This solution uses USB / Ethernet communication. Alternative solutions can use wireless communication methods such as Bluetooth and WiFi. As long as code burning and status monitoring can be achieved, they can be used as the implementation form of the communication part.

[0161] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An LED matrix electronic sand table technology demonstration system based on FPGA / CPLD, wherein the system is configured as a modular hardware system supporting the visualization and physical construction of multi-domain technology demonstration content, the system including a power supply module, a communication module, an input module, and pure combinational logic circuits, characterized in that, The pure combinational logic circuit generates multi-dimensional spatial coordinates in parallel based on the input data, and synchronously outputs addressing signals and driving signals for multiple target display units in the LED matrix. The core components of the system include at least a RISC-V processor physical core unit, which includes at least four functional modules: an instruction fetch module, a decode module, an execution module, and a write-back module. These four functional modules are independently packaged and physically connectable. Each of the four functional modules has built-in soft or hard core logic and is equipped with a visual indicator component corresponding to each instruction pipeline stage. The indicator component includes a color LED array and a digital tube, used to synchronously display in real time the instruction field, operand address, ALU operation type, and target register identifier processed in the current stage. By connecting the four modules and using a clock, the pipelined operation of each instruction under clock support can be confirmed, and the perpendicular orthogonality between the data pipeline and the instruction pipeline can be achieved.

2. The LED matrix electronic sand table technology demonstration system as described in claim 1, characterized in that, The core components of the system include at least the following functional units coupled to the physical core unit of the RISC-V processor: (1) A multi-dimensional LED visualization array unit, comprising multiple LED units and configured in a two-dimensional, three-dimensional or N-dimensional topology, wherein each LED unit contains at least two independently driveable light-emitting sub-pixels for mapping digital circuit states, instruction addresses, register data, neighboring pixel values ​​or intermediate algorithm results into visible light points with spatial coordinates and color / grayscale attributes, wherein the spatial coordinates are X / Y / Z coordinates; (2) TCON timing-decoding co-control unit, integrated in the programmable logic device, includes a dynamic timing generation subunit and a static decoding subunit; the dynamic timing generation subunit includes a counter, a coordinate pool and a buffer pool, used to generate scan clock, logical coordinate sequence and corresponding pixel data; The static decoding subunit responds to the logical coordinates and outputs row, column and layer selection signals to achieve precise addressing and time-division lighting of an exponential number of LED beads in the multi-dimensional LED visualization array unit with a small number of standardized general-purpose IO interfaces. (3) Modular physical reconstruction interface unit, configured as magnetic, snap-on or plug-in mechanical connection structure, so that the multi-dimensional LED visualization array unit, TCON timing-decoding co-control unit, RISC-V processor physical core unit and input unit can be physically spliced ​​in a detachable, rearrangeable and fly-wire-expandable manner to construct a topology for technical demonstration of different technical principles; (4) The host computer collaborative programming unit receives and synchronously burns the target configuration code to at least two functional modules in the TCON timing-decoding collaborative control unit and the RISC-V processor physical core unit through the communication module, so that the internal logic of each module can be dynamically reconfigured, and after the burning is completed, the technology demonstration system can run the configured technology demonstration function independently without the host computer.

3. The LED matrix electronic sand table technology demonstration system as described in claim 1, characterized in that, In the multi-dimensional LED visualization array unit, each LED bead unit contains no less than two independently driven light-emitting sub-pixels; the driving signal of the light-emitting sub-pixels is directly controlled by the data bits stored in the buffer pool of the TCON timing-decoding co-control unit corresponding to the spatial coordinates, so that the same LED bead unit can synchronously present multiple technical demonstration semantic information in the same scanning cycle, wherein at least one light-emitting sub-pixel is used to display the register address identifier, another light-emitting sub-pixel is used to display the data value corresponding to the address, and a third light-emitting sub-pixel is used to display the data valid status flag.

4. The LED matrix electronic sand table technology demonstration system as described in claim 1, characterized in that, The multi-dimensional LED visualization array unit supports N-dimensional expansion, where N is an integer greater than or equal to 2. The TCON timing-decoding co-control unit is configured with N independent static decoding sub-units, each corresponding to the coordinate decoding output of N orthogonal dimensions. When N=2, the N static decoding sub-units are row decoders and column decoders. When N=3, the N static decoding sub-units are layer decoders, row decoders, and column decoders. When N>3, each additional dimension adds a corresponding set of static decoding sub-units, and the outputs of all N sets of decoding sub-units work together to uniquely select a single LED unit.

5. The LED matrix electronic sand table technology demonstration system as described in claim 1, characterized in that, The instruction fetch module, decoding module, execution module, and write-back module of the RISC-V processor physical core unit are each encapsulated in an independent physical housing; each housing has a matrix of colored LED beads, a grid of fine filaments surrounding each bead, and a seven-segment digital tube on the front; each housing has a standardized mechanical and electrical composite interface on the back, which supports precise alignment and splicing with adjacent modules through magnetic arrays or snap-fit ​​structures; the signal pins between modules allow users to make arbitrary cross-module connections through external flying wires.

6. A method for demonstrating LED matrix electronic sand table technology based on FPGA / CPLD, used for demonstrating technologies in the fields of digital circuits, FPGA programming, RISC-V microprocessor principles, and image processing, characterized in that... The method uses pure combinational logic circuits to generate multi-dimensional spatial coordinates in parallel based on input data, and synchronously outputs addressing signals and driving signals for multiple target display units in the LED matrix. It also enables the data pipeline and instruction pipeline to be perpendicularly orthogonal. The method includes the following collaboratively executed steps: (1) Physical construction technology demonstration topology: At least one module of the multi-dimensional LED visualization array unit, TCON timing-decoding co-control unit, RISC-V processor physical core unit and input unit are detachably spliced ​​by magnetic attraction or snap-fit ​​to form a hardware architecture for technology demonstration in a specific field; (2) Configure the visual mapping relationship: Write pixel data corresponding to the spatial coordinates of the LED beads to the coordinate pool of the TCON timing-decoding co-control unit through the host computer software, and set the scanning cycle parameters; at the same time, burn the corresponding function code to each module of the RISC-V processor physical core unit, so that the instruction fetch module, decoding module, execution module and write-back module respectively establish the real-time mapping of instruction field, operand address, ALU operation status and target register identifier with their respective LED beads / digital tubes; (3) Start the dynamic demonstration process: Under the clock drive, the TCON unit generates a logical coordinate sequence according to the coordinate pool data and outputs a strobe signal after static decoding, driving the LED array to light up point by point; each module of RISC-V runs synchronously, and its LED beads and digital tubes are displayed in high brightness level by level as the instruction stream progresses, realizing the spatialization, timing and visualization of the instruction execution process; (4) Interactive intervention and feedback: The LED array and the visualization components of each of the four modules respond synchronously by adjusting the scanning frequency, switching the coordinate sequence, triggering instruction jumps or updating cache pool data through the input unit.

7. The method as described in claim 6, characterized in that, In step (1), when the multidimensional LED visualization array unit is a two-dimensional structure, the row decoder and column decoder are spliced ​​together; when the multidimensional LED visualization array unit is a three-dimensional structure, the row decoder, column decoder and layer decoder are spliced ​​together, and the outputs of the three sets of decoders are used to complete the unique selection of a single LED unit. In an N-dimensional structure, each additional dimension adds a new set of decoder modules for that dimension.

8. The method as described in claim 6, characterized in that, The pixel data written to the coordinate pool in step (2) contains multi-channel grayscale information, wherein the red channel data is mapped to the register address encoding, the green channel data is mapped to the general-purpose register value, and the blue channel data is mapped to the valid flag bit, so that the same LED unit can synchronously present the address, data and status triple technical demonstration semantics in the same scanning cycle.

9. The method as described in claim 6, characterized in that, The dynamic demonstration process in step (3) supports dual pipeline orthogonal collaboration: the TCON unit drives the LED array to build a data pipeline and executes neighborhood sliding window data transfer; the RISC-V processor physical core unit synchronously executes image processing instructions; the two pipelines are perpendicular and orthogonal in space and periodically aligned in time, and the LED array synchronously displays the original image area and the processing result area, presenting a parallel computing mechanism.

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