Memory device

Abstract

The present disclosure relates to memory devices. The memory devices include strings, control circuitry, and peripheral circuitry. Each of the strings includes a drain select transistor, a source select transistor, a plurality of memory cell groups disposed between the drain select transistor and the source select transistor, and an intermediate portion disposed between the plurality of memory cell groups. The control circuitry determines a selected memory cell group including a target memory cell, and one or more unselected memory cell groups. The peripheral circuitry applies an intermediate select voltage to a first intermediate select line coupled to a first intermediate select transistor adjacent to one or both ends of each of the unselected memory cell groups, and applies a first pass voltage to a second intermediate select line coupled to a second intermediate select transistor adjacent to one or both ends of the selected memory cell group.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0185083, filed on December 12, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to memory devices. Background Technology

[0004] Semiconductor devices are key components of electronic devices and have a wide range of modern applications, such as in technologies like computing, communications, artificial intelligence, and storage. Semiconductor devices can be composed of components such as transistors, diodes, and integrated circuits (ICs).

[0005] When a memory device, as a type of semiconductor device, performs programming operations, it may encounter interference that causes the stored data to be disturbed and corrupted. To reduce interference and improve the stability and reliability of memory cells, dummy word lines can be used. However, increasing the number of dummy word lines can be disadvantageous in terms of manufacturing cost, power consumption, and memory capacity. Therefore, a method that can effectively suppress interference using a smaller number of dummy word lines may be needed. Summary of the Invention

[0006] In one embodiment, a memory device may include a string, control circuitry, and peripheral circuitry. The string may be coupled between a bit line and a source line. Each string may include a drain select transistor coupled to the bit line, a source select transistor coupled to the source line, a plurality of memory cell groups disposed between the drain select transistor and the source select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups. Each of the one or more intermediate portions may include a plurality of intermediate select transistors series coupled between adjacent memory cell groups. The control circuitry may be configured to determine selected memory cell groups and one or more unselected memory cell groups within the selected string, the selected memory cell group including the target memory cell in which a programming operation is to be performed, and the one or more unselected memory cell groups not being selected memory cell groups. The selected string may be a string that includes the target memory cell. The peripheral circuitry can be configured to operate under the control of the control circuitry, and can be configured to apply an intermediate selection voltage to one or more first intermediate selection lines coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups, and can be configured to apply a first pass voltage to one or more second intermediate selection lines coupled to one or more second intermediate selection transistors adjacent to one or both ends of the selected memory cell group.

[0007] In one embodiment, a memory device may include strings, control circuitry, and peripheral circuitry. Each string may include a drain-select transistor coupled to a bitline, a source-select transistor coupled to a source bitline, a plurality of memory cell groups disposed between the drain-select transistor and the source-select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups. Each of the plurality of memory cell groups may include a plurality of memory cells coupled in series, and one or more dummy memory cells disposed at one or both ends of the plurality of memory cells. Each of the one or more intermediate portions may include a plurality of intermediate select transistors coupled in series between adjacent memory cell groups. The control circuitry may be configured to determine selected memory cell groups and one or more unselected memory cell groups within the selected strings, the selected memory cell group including the target memory cell in which a programming operation is to be performed, and the one or more unselected memory cell groups not being selected memory cell groups. The selected string may be a string that includes the target memory cell. The peripheral circuitry can be configured to operate under the control of the control circuitry, and can be configured to apply an intermediate selection voltage to one or more first intermediate selection transistors coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups, and can be configured to apply a first pass voltage to one or more first dummy word lines coupled to one or more first dummy memory cells included in the one or more unselected memory cell groups.

[0008] In one embodiment, a memory device may include strings, control circuitry, and peripheral circuitry. Each string may include a drain-select transistor coupled to a bitline, a source-select transistor coupled to a source bitline, a plurality of memory cell groups disposed between the drain-select transistor and the source-select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups. Each of the plurality of memory cell groups may include a plurality of memory cells coupled in series, and one or more dummy memory cells disposed at one or both ends of the plurality of memory cells. Each of the one or more intermediate portions may include a plurality of intermediate select transistors coupled in series between adjacent memory cell groups. The control circuitry may be configured to determine selected memory cell groups and one or more unselected memory cell groups within the selected strings, the selected memory cell group including the target memory cell in which a programming operation is to be performed, and the one or more unselected memory cell groups not being selected memory cell groups. The selected string may be a string that includes the target memory cell. The peripheral circuitry can be configured to operate under the control of the control circuitry, and can be configured to apply a first pass voltage to one or more intermediate select lines coupled to one or more intermediate select transistors adjacent to one or both ends of the selected memory cell group, and can be configured to apply a second pass voltage higher than the first pass voltage to one or more dummy word lines coupled to one or more dummy memory cells included in the selected memory cell group. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram illustrating a string according to an embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating the voltage applied to the row lines and channels of an unselected string during programming operations according to an embodiment of the present disclosure.

[0012] Figure 4 This is a timing diagram of one embodiment of programming operations, where the second stack is as follows: Figure 3 The selected stack in the example.

[0013] Figure 5 This is a diagram illustrating the voltage applied to the row lines and channels of an unselected string during programming operations according to an embodiment of the present disclosure.

[0014] Figure 6 This is a timing diagram of one embodiment of programming operations, where the third stack is as follows: Figure 5 The selected stack in the example.

[0015] Figure 7 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In some embodiments, terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element.

[0017] Figure 1 This is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0018] refer to Figure 1 The memory device 100 can operate in response to a control signal CTR from an external controller (not shown). The memory device 100 can store data DATA received from the controller by performing a programming operation, and can output the stored data DATA to the controller by performing a read operation.

[0019] The memory device 100 may include a control circuit 110, a peripheral circuit 120, and a memory cell array 130.

[0020] Control circuit 110 can control the operation of voltage generation circuit 121, buffer circuit 122, and decoder 123 to perform memory cell operations, such as programming, reading, and erasing operations, under the control of the controller. For example, to control voltage generation circuit 121, control circuit 110 can generate a voltage control signal VCS and output it to voltage generation circuit 121. To control buffer circuit 122, control circuit 110 can generate a buffer control signal BCS and output it to buffer circuit 122. To control decoder 123, control circuit 110 can generate a decoder control signal DCS and output it to decoder 123. In one embodiment, control circuit 110 can operate in response to a control signal CTR from an external controller (not shown).

[0021] The peripheral circuit 120 can store data in the memory cell array 130 and read data from the memory cell array 130 under the control of the control circuit 110. The peripheral circuit 120 may include a voltage generation circuit 121, a buffer circuit 122, and a decoder 123.

[0022] The voltage generation circuit 121 can generate various operating voltages VO in response to the voltage control signal VCS, and can pass the operating voltages VO to the decoder 123 and the buffer circuit 122.

[0023] Buffer circuit 122 can be coupled to memory cell array 130 via bit lines BL1 to BLm. Buffer circuit 122 may include sub-buffers BF1 to BFm, respectively coupled to bit lines BL1 to BLm. Sub-buffers BF1 to BFm can be coupled to memory cells (not shown) included in memory cell array 130 via bit lines BL1 to BLm. Sub-buffers BF1 to BFm can receive and store data to be stored in memory cells from a controller. Sub-buffers BF1 to BFm can store data read from memory cells for output to the controller. Sub-buffers BF1 to BFm can operate simultaneously in response to buffer control signal BCS, such that memory cells respectively coupled to bit lines BL1 to BLm can be accessed simultaneously. The terms "simultaneously" and "at the same time" as used herein with respect to processes mean that these processes occur over overlapping time intervals. For example, if a first process occurs within a first time interval and a second process occurs simultaneously within a second time interval, then the first and second time intervals at least partially overlap each other, such that there exists a time when both the first and second processes occur.

[0024] Decoder 123 can be coupled to memory cell array 130 via row lines RL. Decoder 123 can apply an operating voltage VO to row lines RL in response to decoder control signal DCS. Row lines RL may include drain select lines, intermediate dummy word lines, word lines, and source select lines, as described later.

[0025] The memory cell array 130 may include memory cells in which data DATA is stored. The memory cells can be selectively accessed via row lines RL and bit lines BL1 to BLm.

[0026] The memory cell array 130 may include multiple strings (not shown) coupled between bit lines and source lines. Each string may include a drain-select transistor coupled to the bit line, a source-select transistor coupled to the source line, multiple memory cell groups disposed between the drain-select transistor and the source-select transistor, and one or more intermediate portions disposed between the multiple memory cell groups. Each memory cell group may include multiple memory cells coupled in series, and one or more dummy memory cells disposed at one or both ends of the multiple memory cells. Each of the one or more intermediate portions may include multiple intermediate select transistors coupled in series between adjacent memory cell groups. Each of the one or more dummy memory cells may couple a memory cell to an adjacent intermediate select transistor, drain-select transistor, or source-select transistor.

[0027] Figure 2 This is a circuit diagram illustrating serial ST1 and ST2 according to an embodiment of the present disclosure. Figure 2 The number of each configuration shown is for example purposes.

[0028] refer to Figure 2 ST1 and ST2 can be coupled between bit line BL and source line SL.

[0029] Serial ST1 may include a drain select transistor DST1 coupled to bit line BL, a source select transistor SST1 coupled to source line SL, memory cell groups GR11, GR12, and GR13 disposed between drain select transistor DST1 and source select transistor SST1, and intermediate portions MT11 and MT12 disposed between memory cell groups GR11, GR12, and GR13. Memory cell groups GR11, GR12, and GR13 and intermediate portions MT11 and MT12 may be connected in series between drain select transistor DST1 and source select transistor SST1.

[0030] The memory cell group GR11 may include series-coupled memory cells C111 to C11a and dummy memory cells D111 and D112 disposed at both ends of memory cells C111 to C11a. Memory cells C111 to C11a may be coupled to word lines WL11 to WL1a, respectively. Dummy memory cells D111 and D112 may be coupled to dummy word lines DWL11 and DWL12, respectively. Dummy memory cell D111 may be coupled to the adjacent source selection transistor SST1 and memory cell C111. Dummy memory cell D112 may couple memory cell C11a to the adjacent intermediate selection transistor M111. In one embodiment, the series-coupled plurality of dummy memory cells may be disposed at each end of memory cells C111 to C11a, instead of a single dummy memory cell as shown. In one embodiment, the memory cell group GR11 may not include dummy memory cells D111 and D112.

[0031] Each memory cell group in memory cell groups GR12 and GR13 can be configured similarly to memory cell group GR11. Memory cell group GR12 may include memory cells C121 to C12b coupled to word lines WL21 to WL2b and dummy memory cells D121 and D122 coupled to dummy word lines DWL21 and DWL22. Memory cell group GR13 may include memory cells C131 to C13c coupled to word lines WL31 to WL3c and dummy memory cells D131 and D132 coupled to dummy word lines DWL31 and DWL32.

[0032] The intermediate portion MT11 may include intermediate select transistors M111 and M112 series-coupled between adjacent memory cell groups GR11 and GR12. Intermediate select transistors M111 and M112 may be coupled to intermediate select lines MSL11 and MSL12, respectively. In one embodiment, the intermediate portion MT11 may include three or more intermediate select transistors series-coupled, instead of the two intermediate select transistors M111 and M112 shown in the figure.

[0033] The intermediate portion MT12 can be configured similarly to the intermediate portion MT11. The intermediate portion MT12 may include intermediate selection transistors M121 and M122 coupled to intermediate selection lines MSL21 and MSL22.

[0034] Drain select transistor DST1 can be coupled to drain select line DSL1. Source select transistor SST1 can be coupled to source select line SSL.

[0035] Serial ST2 can be configured similarly to serial ST1. The drain select transistor DST2 included in serial ST2 can be coupled to the drain select line DSL2. Therefore, serial ST1 and ST2 can be individually selected by controlling the drain select lines DSL1 and DSL2. The memory cells included in serial ST1 and ST2 can be jointly coupled to word lines WL11 to WL1a, WL21 to WL2b, and WL31 to WL3c. Memory cells located at corresponding positions in serial ST1 and ST2 can be coupled to the same word line. The dummy memory cells included in serial ST1 and ST2 can be jointly coupled to dummy word lines DWL11, DWL12, DWL21, DWL22, DWL31, and DWL32. Dummy memory cells located at corresponding positions in serial ST1 and ST2 can be coupled to the same dummy word line. The intermediate selection transistors included in series ST1 and ST2 can be jointly coupled to intermediate selection lines MSL11, MSL12, MSL21, and MSL22. Intermediate selection transistors located at corresponding positions in series ST1 and ST2 can be coupled to the same intermediate selection line. The source selection transistors SST1 and SST2 included in series ST1 and ST2 can be jointly coupled to the source selection line SSL.

[0036] Bit line BL can be Figure 1 Any one of the bit lines BL1 to BLm. Multiple strings can be coupled between the bit lines BL1 to BLm and the source line SL in a manner similar to strings ST1 and ST2. Among the multiple strings coupled to the bit lines BL1 to BLm, the string corresponding to string ST1 can be jointly coupled to the drain select line DSL1. Among the multiple strings coupled to the bit lines BL1 to BLm, the string corresponding to string ST2 can be jointly coupled to the drain select line DSL2. The multiple strings coupled to the bit lines BL1 to BLm can be jointly coupled to word lines WL11 to WL1a, WL21 to WL2b, WL31 to WL3c, dummy word lines DWL11, DWL12, DWL21, DWL22, DWL31, DWL32, intermediate select lines MSL11, MSL12, MSL21, MSL22, and the source select line SSL.

[0037] A stack can refer to a layer formed by memory cell groups GR11, GR12, GR13, GR21, GR22, and GR23 in strings ST1 and ST2 when they are stacked at the same height. Memory cell groups GR11 and GR21 can be included in a first stack STK1, memory cell groups GR12 and GR22 can be included in a second stack STK2, and memory cell groups GR13 and GR23 can be included in a third stack STK3. Memory cell groups included in the same stack can be coupled to the same word line.

[0038] A target memory cell can be the memory cell in which a programming operation is to be performed. A target word line can be a word line coupled to the target memory cell. A selected string can be a string that includes the target memory cell among multiple strings coupled to any bit line. A selected memory cell group can be a group of memory cells that includes the target memory cell among the groups of memory cells included in the selected string. A non-selected memory cell group can be a group of memory cells that does not contain the target memory cell among the groups of memory cells included in the selected string. A non-selected string can be a string that is not the selected string among multiple strings coupled to the same bit line as the selected string. A selected stack can be a stack containing selected memory cell groups. A non-selected stack can be a stack containing non-selected memory cell groups.

[0039] For example, in Figure 2 In the above, when the target memory cell is memory cell C111, the target word line is word line WL11, the selected string is string ST1, the selected memory cell group is memory cell group GR11, the unselected memory cell groups are memory cell groups GR12 and GR13, the unselected string is string ST2, the selected stack is the first stack STK1, and the unselected stacks can be the second stack STK2 and the third stack STK3.

[0040] Refer again Figure 1 The control circuit 110 can, for each bit line BL1 to BLm, determine the selected memory cell group that includes the target memory cell in which the programming operation is to be performed, and one or more unselected memory cell groups that are not selected memory cell groups.

[0041] The peripheral circuit 120 can perform programming operations under the control of the control circuit 110. Specifically, the decoder 123 can apply an intermediate selection voltage to one or more first intermediate selection lines coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups. The intermediate selection voltage can be a voltage that disconnects one or more third intermediate selection transistors coupled to the one or more first intermediate selection lines and included in the one or more unselected strings, and turns on the first intermediate selection transistors. In one embodiment, the decoder 123 can apply intermediate selection voltages at different levels to each of the one or more first intermediate selection lines.

[0042] Decoder 123 may apply a first pass voltage to one or more second intermediate select lines coupled to one or more second intermediate select transistors adjacent to one or both ends of the selected memory cell group.

[0043] Decoder 123 can apply a first pass voltage to one or more first dummy word lines coupled to one or more first dummy memory cells included in one or more unselected memory cell groups.

[0044] Decoder 123 can apply a second pass voltage higher than the first pass voltage to one or more second dummy word lines coupled to one or more second dummy memory cells included in the selected memory cell group.

[0045] Decoder 123 can apply a third pass voltage higher than the first pass voltage to a first word line coupled to a first memory cell included in one or more unselected memory cell groups.

[0046] Decoder 123 can apply a fourth pass voltage higher than the third pass voltage to the second word line of a second memory cell that is not the target memory cell among the memory cells included in the selected memory cell group.

[0047] Decoder 123 can apply a programming voltage to the target word line coupled to the target memory cell.

[0048] According to one embodiment of this disclosure, by controlling the voltage of the corresponding intermediate select line and dummy word line based on the location of the selected memory cell group or the selected stack, interference can be effectively suppressed using fewer dummy word lines.

[0049] Figure 3 This is a diagram illustrating the voltage applied to the row line RL and channel of the unselected string ST2 during programming operations according to an embodiment of the present disclosure. Figure 3 The number of each configuration shown is for illustrative purposes only.

[0050] refer to Figure 3 The target word line can be word line WL22, and the target memory cell can be a memory cell coupled to the target word line WL22 and included in the selected string ST1. Therefore, the second stack STK2 coupled to the target word line WL22 can be the selected stack. The first stack STK1 and the third stack STK3 can be unselected stacks.

[0051] In programming operations, an intermediate selection voltage VMSL can be applied to intermediate selection lines MSL11 and MSL22 (i.e., first intermediate selection lines) coupled to intermediate selection transistors M211 and M222. The intermediate selection voltage VMSL can be the voltage that disconnects intermediate selection transistors M211 and M222. Therefore, intermediate selection transistors M211 and M222 can disconnect the channel between memory cell groups GR21 to GR23 in response to the intermediate selection voltage VMSL. Intermediate selection lines MSL11 and MSL22 can be coupled to adjacent intermediate selection transistors M111 and M122 (i.e., first intermediate selection transistors) located at one or both ends of each unselected memory cell group GR11 and GR13 in the selected string ST1. Intermediate selection lines MSL11 and MSL22 can also be described as intermediate selection lines adjacent to one or both ends of each unselected stack in the unselected stacks STK1 and STK3.

[0052] Furthermore, a first pass voltage VPASS1 can be applied to dummy word lines DWL11, DWL12, DWL31, and DWL32 (i.e., first dummy word lines) coupled to dummy memory cells D211, D212, D231, and D232. Dummy word lines DWL11, DWL12, DWL31, and DWL32 can be coupled to dummy memory cells D111, D112, D131, and D132 (i.e., first dummy memory cells) included in the unselected memory cell groups GR11 and GR13 in the selected string ST1. Dummy word lines DWL11, DWL12, DWL31, and DWL32 can also be described as dummy word lines coupled to unselected stacks STK1 and STK3.

[0053] Furthermore, a third voltage VPASS3 can be applied to word lines WL11 to WL13 and WL31 to WL33 (i.e., the first word lines) coupled to memory cells C211 to C213 and C231 to C233. Word lines WL11 to WL13 and WL31 to WL33 can be coupled to memory cells (i.e., the first memory cells) included in the unselected memory cell groups GR11 and GR13 in the selected string ST1. Word lines WL11 to WL13 and WL31 to WL33 can also be described as word lines coupled to unselected stacks STK1 and STK3.

[0054] Furthermore, the first pass voltage VPASS1 can be applied to intermediate select lines MSL12 and MSL21 (i.e., second intermediate select lines) coupled to intermediate select transistors M212 and M221. Intermediate select lines MSL12 and MSL21 can be coupled to intermediate select transistors M112 and M121 (i.e., second intermediate select transistors) adjacent to both ends of the selected memory cell group GR12 in the selected string ST1. Intermediate select lines MSL12 and MSL21 can also be described as intermediate select lines adjacent to both ends of the selected stack STK2.

[0055] Furthermore, a second voltage VPASS2 can be applied to dummy word lines DWL21 and DWL22 (i.e., second dummy word lines) coupled to dummy memory cells D221 and D222. Dummy word lines DWL21 and DWL22 can be coupled to dummy memory cells D121 and D122 (i.e., second dummy memory cells) included in the selected memory cell group GR12 of the selected string ST1. Dummy word lines DWL21 and DWL22 can also be described as dummy word lines coupled to the selected stack STK2.

[0056] Furthermore, a fourth voltage VPASS4 can be applied to word lines WL21 and WL23 (i.e., second word lines) coupled to memory cells C221 and C223. Word lines WL21 and WL23 can be coupled to memory cells (i.e., second memory cells) that are not target memory cells in the selected memory cell group GR12 of the selected string ST1. Word lines WL21 and WL23 can also be described as word lines coupled to the selected stack STK2.

[0057] The first pass voltage VPASS1 to the fourth pass voltage VPASS4 can be the voltages that connect the memory cell and the dummy memory cell. The first pass voltage VPASS1 can be lower than the second pass voltage VPASS2, the second pass voltage VPASS2 can be lower than the third pass voltage VPASS3, and the third pass voltage VPASS3 can be lower than the fourth pass voltage VPASS4.

[0058] Furthermore, the source non-select voltage VSSL1 can be applied to the source select line SSL coupled to the source select transistor SST2. The source non-select voltage VSSL1 can be the voltage that disconnects the source select transistor SST2. Similarly, the drain non-select voltage VDSL1 can be applied to the drain select line DSL2 coupled to the drain select transistor DST2. The drain non-select voltage VDSL1 can be the voltage that disconnects the drain select transistor DST2.

[0059] In addition, the programming voltage VPGM can be applied to the target word line WL22.

[0060] Therefore, in one embodiment, the channel potential of memory cell group GR22 can be boosted to a high voltage level, and interference caused by programming voltage VPGM can be suppressed. Furthermore, in one embodiment, the channel potentials of memory cell groups GR21 and GR23 can be boosted to a low voltage level, and interference caused by third pass voltage VPASS3 can be suppressed. Here, in one embodiment, the relatively low levels of first pass voltage VPASS1 and second pass voltage VPASS2 can mitigate the electric field caused by nearby third pass voltage VPASS3 and fourth pass voltage VPASS4. In this case, in one embodiment, intermediate select lines MSL12 and MSL21 can similarly act on dummy word lines DWL12 and DWL31 to mitigate the channel potential. As a result, in one embodiment, interference can be effectively suppressed using only a small number of dummy word lines.

[0061] Figure 4 This is a timing diagram of the programming operations, where the second stack STK2 is as follows: Figure 3 The selected stack in the example.

[0062] refer to Figure 4 The programming operation may include a first interval P1 and a second interval P2. The first interval P1 may be a channel pre-charge interval, and the second interval P2 may be a programming interval.

[0063] In the first interval P1, a first precharge voltage VPRE1 or a second precharge voltage VPRE2 higher than the first precharge voltage VPRE1 can be applied to each bit line BL. Specifically, the first precharge voltage VPRE1 can be applied to the bit line BL coupled to the target memory cell to be programmed. The second precharge voltage VPRE2 can be applied to the bit line BL coupled to the target memory cell that has already been programmed. In one embodiment, a third precharge voltage (not shown) higher than the first precharge voltage VPRE1 and lower than the second precharge voltage VPRE2 can be applied to the bit line BL coupled to the target memory cell to be weakly programmed.

[0064] Furthermore, either a drain-select voltage VDSL2 or a drain-non-select voltage VDSL1 can be applied to each drain-select line DSL. Specifically, the drain-select voltage VDSL2 can be applied to the drain-select line DSL1 coupled to the selected string ST1, which includes the target memory cell. The drain-select voltage VDSL2 can be the voltage that enables the drain-select transistor of each string to turn on. The drain-non-select voltage VDSL1 can be applied to the drain-select line DSL2 coupled to the unselected string ST2, which does not contain the target memory cell.

[0065] Furthermore, an intermediate selection voltage VMSL can be applied to intermediate selection lines MSL11 and MSL22 adjacent to one or both ends of each of the unselected stacks STK1 and STK3. The intermediate selection voltage VMSL can be the voltage that disconnects the intermediate selection transistors M211 and M222 included in the unselected string ST2. Intermediate selection transistors M111 and M122 in the selected string ST1, coupled to intermediate selection lines MSL11 and MSL22, can be turned on in response to the intermediate selection voltage VMSL. In one embodiment, a voltage V1 higher than the intermediate selection voltage VMSL can be applied to the intermediate selection lines MSL11 and MSL22 within a first interval P1.

[0066] Furthermore, the first pass voltage VPASS1 can be applied to the intermediate selection lines MSL12 and MSL21 adjacent to both ends of the selected stack STK2. In one embodiment, a voltage V2 higher than the first pass voltage VPASS1 can be applied to the intermediate selection lines MSL12 and MSL21 in the first interval P1.

[0067] Furthermore, a source select voltage VSSL2 can be applied to the source select line SSL. VSSL2 can be the voltage required to turn on the source select transistors in each string. Additionally, a second precharge voltage VPRE2 can be applied to the source line SL.

[0068] In the first interval P1, the first word line voltage VWL can be applied to all word lines WL11 to WL13, WL21 to WL23, WL31 to WL33, and dummy word lines DWL11, DWL12, DWL21, DWL22, DWL31, and DWL32. In one embodiment, the first word line voltage VWL can be a ground voltage.

[0069] In the second interval P2, the source non-selection voltage VSSL1 can be applied to the source select line SSL.

[0070] Furthermore, a first pass voltage VPASS1 can be applied to the dummy word lines DWL11, DWL12, DWL31, and DWL32 coupled to the unselected stacks STK1 and STK3. Additionally, a third pass voltage VPASS3 can be applied to the word lines WL11 to WL13 and WL31 to WL33 coupled to the unselected stacks STK1 and STK3.

[0071] Furthermore, a second pass voltage VPASS2 can be applied to dummy word lines DWL21 and DWL22 coupled to the selected stack STK2. Additionally, a fourth pass voltage VPASS4 can be applied to the remaining word lines WL21 and WL23, which are not the target word line WL22 and are coupled to the selected stack STK2. Furthermore, an intermediate voltage (e.g., the fourth pass voltage VPASS4) can be applied to the target word line WL22, and the programming voltage VPGM can be applied after a predetermined time. The term "predetermined" as used herein with respect to parameters (such as predetermined timing, time, or voltage level) means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0072] Figure 5 This is a diagram illustrating the voltage applied to the row line RL and channel of the unselected string ST2 during programming operations according to an embodiment of the present disclosure. Figure 5 The number of each configuration shown is for example purposes.

[0073] refer to Figure 5 The target word line can be word line WL32, and the target memory cell can be a memory cell coupled to the target word line WL32 and included in the selected string ST1. Therefore, the third stack STK3 coupled to the target word line WL32 can be the selected stack. The first stack STK1 and the second stack STK2 can be unselected stacks.

[0074] During programming, an intermediate selection voltage VMSL can be applied to intermediate selection lines MSL11, MSL12, and MSL21 (i.e., the first intermediate selection lines) coupled to intermediate selection transistors M211, M212, and M221. The intermediate selection voltage VMSL can be the voltage that disconnects intermediate selection transistors M211, M212, and M221. Therefore, intermediate selection transistors M211, M212, and M221 can disconnect the channel between memory cell groups GR21 to GR23 in response to the intermediate selection voltage VMSL. Intermediate selection lines MSL11, MSL12, and MSL21 can be coupled to adjacent intermediate selection transistors M111, M112, and M121 (i.e., the first intermediate selection transistors) located at one or both ends of each unselected memory cell group in unselected memory cell groups GR11 and GR12 within the selected string ST1. The intermediate selection lines MSL11, MSL12, and MSL21 can also be described as intermediate selection lines adjacent to one or both ends of each of the unselected stacks STK1 and STK2.

[0075] Furthermore, a first pass voltage VPASS1 can be applied to dummy word lines DWL11, DWL12, DWL21, and DWL22 (i.e., first dummy word lines) coupled to dummy memory cells D211, D212, D221, and D222. Dummy word lines DWL11, DWL12, DWL21, and DWL22 can be coupled to dummy memory cells D111, D112, D121, and D122 (i.e., first dummy memory cells) included in the unselected memory cell groups GR11 and GR12 in the selected string ST1. Dummy word lines DWL11, DWL12, DWL21, and DWL22 can also be described as dummy word lines coupled to unselected stacks STK1 and STK2.

[0076] Furthermore, a third voltage VPASS3 can be applied to word lines WL11 to WL13, WL21 to WL23 (i.e., the first word lines) coupled to memory cells C211 to C213, C221 to C223. Word lines WL11 to WL13, WL21 to WL23 can be coupled to memory cells (i.e., the first memory cells) included in the unselected memory cell groups GR11 and GR12 in the selected string ST1. Word lines WL11 to WL13, WL21 to WL23 can also be described as word lines coupled to unselected stacks STK1 and STK2.

[0077] Furthermore, a first pass voltage VPASS1 can be applied to an intermediate select line MSL22 (i.e., a second intermediate select line) coupled to an intermediate select transistor M222. The intermediate select line MSL22 can be coupled to an intermediate select transistor M122 (i.e., a second intermediate select transistor) adjacent to one end of the selected memory cell group GR13 in the selected string ST1. The intermediate select line MSL22 can also be described as an intermediate select line adjacent to one end of the selected stack STK3.

[0078] Furthermore, a second voltage VPASS2 can be applied to dummy word lines DWL31 and DWL32 (i.e., second dummy word lines) coupled to dummy memory cells D231 and D232. Dummy word lines DWL31 and DWL32 can be coupled to dummy memory cells D131 and D132 (i.e., second dummy memory cells) included in the selected memory cell group GR13 of the selected string ST1. Dummy word lines DWL31 and DWL32 can also be described as dummy word lines coupled to the selected stack STK3.

[0079] Furthermore, a fourth voltage VPASS4 can be applied to word lines WL31 and WL33 (i.e., second word lines) coupled to memory cells C231 and C233. Word lines WL31 and WL33 can be coupled to memory cells (i.e., second memory cells) that are not target memory cells in the selected memory cell group GR13 of the selected string ST1. Word lines WL31 and WL33 can also be described as word lines coupled to the selected stack STK3.

[0080] Furthermore, the source non-select voltage VSSL1 can be applied to the source select line SSL coupled to the source select transistor SST2. The source non-select voltage VSSL1 can be the voltage that disconnects the source select transistor SST2. Similarly, the drain non-select voltage VDSL1 can be applied to the drain select line DSL2 coupled to the drain select transistor DST2. The drain non-select voltage VDSL1 can be the voltage that disconnects the drain select transistor DST2.

[0081] In addition, the programming voltage VPGM can be applied to the target word line WL32.

[0082] Therefore, in one embodiment, the channel potential of memory cell group GR23 can be boosted to a high voltage level, and interference caused by programming voltage VPGM can be suppressed. Furthermore, in one embodiment, the channel potentials of memory cell groups GR21 and GR22 can be boosted to a low voltage level, and interference caused by third pass voltage VPASS3 can be suppressed. Here, in one embodiment, the relatively low levels of first pass voltage VPASS1 and second pass voltage VPASS2 can mitigate the electric field caused by nearby third pass voltage VPASS3 and fourth pass voltage VPASS4. In this case, in one embodiment, intermediate select line MSL22 can similarly act on dummy word line DWL22 to mitigate channel potential. As a result, in one embodiment, interference can be effectively suppressed using only a small number of dummy word lines.

[0083] Figure 6 This is a timing diagram of the programming operations, where the third stack STK3 is as follows: Figure 5 The selected stack in the example.

[0084] refer to Figure 6 It can be used as a reference. Figure 4 The described method performs programming operations. (Focus on...) Figure 4For different parts of the operation, the intermediate selection voltage VMSL can be applied to intermediate selection lines MSL11, MSL12, MSL21 adjacent to one or both ends of each of the unselected stacks STK1 and STK2. The intermediate selection voltage VMSL can be the voltage that disconnects the intermediate selection transistors M211, M212, M221 included in the unselected string ST2. The intermediate selection transistors M111, M112, M121 coupled to the intermediate selection lines MSL11, MSL12, MSL21 in the selected string ST1 can be turned on in response to the intermediate selection voltage VMSL. In one embodiment, in the first interval P1, a voltage V1 higher than the intermediate selection voltage VMSL can be applied to the intermediate selection lines MSL11, MSL12, MSL21.

[0085] Furthermore, a first pass voltage VPASS1 can be applied to an intermediate select line MSL22 adjacent to one end of the selected stack STK3. In one embodiment, during the first interval P1, a voltage V2 higher than the first pass voltage VPASS1 can be applied to the intermediate select line MSL22.

[0086] In the second interval P2, a first pass voltage VPASS1 can be applied to the dummy word lines DWL11, DWL12, DWL21, and DWL22 coupled to the unselected stacks STK1 and STK2. Furthermore, a third pass voltage VPASS3 can be applied to the word lines WL11 to WL13 and WL21 to WL23 coupled to the unselected stacks STK1 and STK2.

[0087] Furthermore, a second pass voltage VPASS2 can be applied to the dummy word lines DWL31 and DWL32 coupled to the selected stack STK3. Additionally, a fourth pass voltage VPASS4 can be applied to the remaining word lines WL31 and WL33, which are not the target word line WL32 and are coupled to the selected stack STK3. Furthermore, an intermediate voltage (e.g., the fourth pass voltage VPASS4) can be applied to the target word line WL32, and the programming voltage VPGM can be applied after a predetermined time.

[0088] In one embodiment, when the selected stack is the first stack STK1, it can be similar to the reference. Figures 3 to 6 The programming operations described herein are used to perform programming operations.

[0089] Figure 7 This is a flowchart illustrating the operation of a memory device 100 according to an embodiment of the present disclosure.

[0090] refer to Figure 7 In operation S110, the control circuit 110 can receive programming commands from the controller.

[0091] In operation S120, control circuit 110 can determine the selected memory cell group and one or more unselected memory cell groups in the selected string, the selected memory cell group including the target memory cell in which the programming operation is to be performed, and the one or more unselected memory cell groups are not selected memory cell groups.

[0092] In operation S130, decoder 123 may apply an intermediate selection voltage to one or more first intermediate selection lines coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups. The intermediate selection voltage may be a voltage that disconnects one or more third intermediate selection transistors included in the one or more unselected strings and coupled to the one or more first intermediate selection lines, and turns on the first intermediate selection transistors.

[0093] In operation S140, decoder 123 may apply a first pass voltage to one or more second intermediate select lines coupled to one or more second intermediate select transistors adjacent to one or both ends of the selected memory cell group. In one embodiment, memory device 100 may include NAND flash memory, three-dimensional NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM).

[0094] According to embodiments of this disclosure, the memory device can effectively suppress interference.

[0095] The concept has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and technical concept of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of this disclosure is not limited to the description provided. All variations within the meaning and equivalents of the claims are included within its scope.

Claims

1. A memory device, comprising: A string coupled between a bit line and a source line, each string including a drain select transistor coupled to the bit line, a source select transistor coupled to the source line, a plurality of memory cell groups disposed between the drain select transistor and the source select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups, each of the one or more intermediate portions including a plurality of intermediate select transistors series coupled between adjacent memory cell groups; A control circuit is configured to determine a selected memory cell group and one or more unselected memory cell groups from among the memory cell groups included in a selected string, the selected memory cell group including a target memory cell in which programming operations will be performed, the one or more unselected memory cell groups not being the selected memory cell group, and the selected string being a string that includes the target memory cell. as well as The peripheral circuitry is configured to operate under the control of the control circuitry and is configured to apply an intermediate selection voltage to one or more first intermediate selection lines coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups. The peripheral circuitry is also configured to apply a first through voltage to one or more second intermediate selection lines coupled to one or more second intermediate selection transistors adjacent to one or both ends of the selected memory cell group.

2. The memory device according to claim 1, wherein: The string also includes one or more unselected strings in addition to the selected string; The one or more unselected strings include one or more third intermediate selection transistors coupled to the one or more first intermediate selection lines; and The one or more third intermediate selection transistors are configured to turn off in response to the intermediate selection voltage.

3. The memory device of claim 2, wherein the one or more first intermediate selection transistors are configured to turn on in response to the intermediate selection voltage.

4. The memory device of claim 1, wherein the peripheral circuitry is configured to apply intermediate selection voltages at different levels to each of the one or more first intermediate selection lines.

5. The memory device of claim 1, wherein each of the plurality of memory cell groups comprises a plurality of memory cells coupled in series, and one or more dummy memory cells disposed at one or both ends of the plurality of memory cells, and The peripheral circuitry is configured to apply the first pass voltage to one or more first dummy word lines, the one or more first dummy word lines being coupled to one or more first dummy memory cells included in the one or more unselected memory cell groups.

6. The memory device of claim 5, wherein the peripheral circuitry is configured to apply a second pass voltage to one or more second dummy word lines coupled to one or more second dummy memory cells included in the selected memory cell group, the second pass voltage being higher than the first pass voltage.

7. The memory device of claim 1, wherein the peripheral circuitry is configured to apply a third pass voltage to a first word line coupled to a first memory cell included in the one or more unselected memory cell groups, the third pass voltage being higher than the first pass voltage.

8. The memory device of claim 7, wherein the peripheral circuitry is configured to apply a fourth pass voltage to a second word line, the second word line being coupled to a second memory cell in the selected memory cell group that is not the target memory cell, the fourth pass voltage being higher than the third pass voltage.

9. The memory device of claim 1, wherein the peripheral circuitry is configured to apply the intermediate selection voltage during a channel precharge interval and a programming interval following the channel precharge interval, and is configured to apply the first pass voltage during the programming interval.

10. The memory device of claim 9, wherein the peripheral circuitry is configured to apply a programming voltage to a target word line coupled to the target memory cell during the programming interval.

11. The memory device of claim 9, wherein the peripheral circuitry is configured as follows: During the channel precharge interval and the programming interval, a first precharge voltage is applied to one or more selected bit lines among the plurality of bit lines, a second precharge voltage is applied to one or more unselected bit lines among the plurality of bit lines, and the second precharge voltage is applied to the source line. During the channel precharge interval and the programming interval, a drain select voltage is applied to the drain select line coupled to the drain select transistor included in a plurality of selected strings, and a drain non-select voltage is applied to the drain select line coupled to the drain select transistor included in an unselected string, wherein the plurality of selected strings are all strings coupled to the plurality of bit lines that include the target memory cell, and the unselected strings are all strings other than the plurality of selected strings; and During the channel precharge interval, a source select voltage is applied to the source select line coupled to the source select transistors included in all the strings, and during the programming interval, a source non-select voltage is applied to the source select line.

12. A memory device, comprising: A series of memory cells are coupled between a bit line and a source line. Each of the series includes a drain select transistor coupled to the bit line, a source select transistor coupled to the source line, a plurality of memory cell groups disposed between the drain select transistor and the source select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups. Each of the plurality of memory cell groups includes a plurality of memory cells coupled in series and one or more dummy memory cells disposed at one or both ends of the plurality of memory cells. Each of the one or more intermediate portions includes a plurality of intermediate select transistors coupled in series between adjacent memory cell groups. A control circuit is configured to determine a selected memory cell group and one or more unselected memory cell groups from among the memory cell groups included in a selected string, the selected memory cell group including a target memory cell in which programming operations will be performed, the one or more unselected memory cell groups not being the selected memory cell group, and the selected string being a string that includes the target memory cell. as well as The peripheral circuitry, configured to operate under the control of the control circuitry, is configured to apply an intermediate selection voltage to one or more first intermediate selection lines coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups, and the peripheral circuitry is configured to apply a first pass voltage to one or more first dummy word lines coupled to one or more first dummy memory cells included in the one or more unselected memory cell groups.

13. The memory device according to claim 12, wherein: The string also includes one or more unselected strings in addition to the selected string; The one or more unselected strings include one or more third intermediate selection transistors coupled to the one or more first intermediate selection lines; and The one or more third intermediate selection transistors are configured to turn off in response to the intermediate selection voltage.

14. The memory device of claim 13, wherein the one or more first intermediate selection transistors are configured to turn on in response to the intermediate selection voltage.

15. The memory device of claim 12, wherein the peripheral circuitry is configured to apply intermediate selection voltages at different levels to each of the one or more first intermediate selection lines.

16. The memory device of claim 12, wherein the peripheral circuitry is configured to apply a second pass voltage to one or more second dummy word lines coupled to one or more second dummy memory cells included in the selected memory cell group, the second pass voltage being higher than the first pass voltage.

17. The memory device of claim 12, wherein the peripheral circuitry is configured to apply a third pass voltage to a first word line coupled to a first memory cell included in the one or more unselected memory cell groups, the third pass voltage being higher than the first pass voltage.

18. The memory device of claim 17, wherein the peripheral circuitry is configured to apply a fourth pass voltage to a second word line, the second word line being coupled to a second memory cell in the selected memory cell group that is not the target memory cell, the fourth pass voltage being higher than the third pass voltage.

19. The memory device of claim 12, wherein the peripheral circuitry is configured to apply the intermediate selection voltage during a channel precharge interval and a programming interval following the channel precharge interval, and is configured to apply the first pass voltage during the programming interval.

20. The memory device of claim 19, wherein the peripheral circuitry is configured to apply a programming voltage to a target word line coupled to the target memory cell during the programming interval.

21. The memory device of claim 19, wherein the peripheral circuitry is configured to: During the channel precharge interval and the programming interval, a first precharge voltage is applied to one or more selected bit lines among the plurality of bit lines, a second precharge voltage is applied to one or more unselected bit lines among the plurality of bit lines, and the second precharge voltage is applied to the source line. During the channel precharge interval and the programming interval, a drain select voltage is applied to the drain select line coupled to the drain select transistor included in a plurality of selected strings, and a drain non-select voltage is applied to the drain select line coupled to the drain select transistor included in an unselected string, wherein the plurality of selected strings are all strings coupled to the plurality of bit lines that include the target memory cell, and the unselected strings are all strings other than the plurality of selected strings; and During the channel precharge interval, a source select voltage is applied to the source select line coupled to the source select transistors included in all the strings, and during the programming interval, a source non-select voltage is applied to the source select line.

22. A memory device, comprising: A series of memory cells are coupled between a bit line and a source line. Each of the series includes a drain select transistor coupled to the bit line, a source select transistor coupled to the source line, a plurality of memory cell groups disposed between the drain select transistor and the source select transistor, and one or more intermediate portions disposed between the plurality of memory cell groups. Each of the plurality of memory cell groups includes a plurality of memory cells coupled in series and one or more dummy memory cells disposed at one or both ends of the plurality of memory cells. Each of the one or more intermediate portions includes a plurality of intermediate select transistors coupled in series between adjacent memory cell groups. A control circuit is configured to determine a selected memory cell group and one or more unselected memory cell groups from among the memory cell groups included in a selected string, the selected memory cell group including a target memory cell in which programming operations will be performed, the one or more unselected memory cell groups not being the selected memory cell group, and the selected string being a string that includes the target memory cell. as well as The peripheral circuitry, configured to operate under the control of the control circuitry, is configured to apply a first pass voltage to one or more intermediate select lines coupled to one or more intermediate select transistors adjacent to one or both ends of the selected memory cell group, and the peripheral circuitry is configured to apply a second pass voltage to one or more dummy word lines coupled to one or more dummy memory cells included in the selected memory cell group, the second pass voltage being higher than the first pass voltage.

23. The memory device of claim 22, wherein the peripheral circuitry is configured to apply the first pass voltage to one or more dummy word lines coupled to one or more dummy memory cells included in the one or more unselected memory cell groups.

24. The memory device of claim 22, wherein the peripheral circuitry is configured to apply a third pass voltage to a word line coupled to a memory cell included in the one or more unselected memory cell groups, the third pass voltage being higher than the first pass voltage.

25. The memory device of claim 24, wherein the peripheral circuitry is configured to apply a fourth pass voltage to a word line coupled to a memory cell that is not the target memory cell among the memory cells included in the selected memory cell group, the fourth pass voltage being higher than the third pass voltage.

26. The memory device of claim 22, wherein the peripheral circuitry is configured to apply an intermediate selection voltage to one or more first intermediate selection lines, the one or more first intermediate selection lines being coupled to one or more first intermediate selection transistors adjacent to one or both ends of each of the one or more unselected memory cell groups.

27. The memory device of claim 26, wherein: The string also includes one or more unselected strings in addition to the selected string; The one or more unselected strings include one or more intermediate selection transistors coupled to the one or more first intermediate selection lines; and One or more intermediate selection transistors included in the one or more unselected strings are configured to turn off in response to the intermediate selection voltage.

28. The memory device of claim 27, wherein the first intermediate selection transistor is configured to turn on in response to the intermediate selection voltage.

29. The memory device of claim 27, wherein the peripheral circuitry is configured to apply intermediate selection voltages at different levels to each of the one or more first intermediate selection lines.

30. The memory device of claim 22, wherein the peripheral circuitry is configured to apply the intermediate selection voltage during a channel precharge interval and a programming interval following the channel precharge interval, and is configured to apply the first pass voltage during the programming interval.

31. The memory device of claim 30, wherein the peripheral circuitry is configured to apply a programming voltage to a target word line coupled to the target memory cell during the programming interval.

32. The memory device of claim 30, wherein the peripheral circuitry is configured as follows: During the channel precharge interval and the programming interval, a first precharge voltage is applied to one or more selected bit lines among the plurality of bit lines, a second precharge voltage is applied to one or more unselected bit lines among the plurality of bit lines, and the second precharge voltage is applied to the source line. During the channel precharge interval and the programming interval, a drain select voltage is applied to the drain select line coupled to the drain select transistor included in a plurality of selected strings, and a drain non-select voltage is applied to the drain select line coupled to the drain select transistor included in an unselected string, wherein the plurality of selected strings are all strings coupled to the plurality of bit lines that include the target memory cell, and the unselected strings are all strings other than the plurality of selected strings; and During the channel precharge interval, a source select voltage is applied to the source select line coupled to the source select transistors included in all the strings, and during the programming interval, a source non-select voltage is applied to the source select line.

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