Memory devices and methods of memory devices performing programming operations

Abstract

A memory device and a method of a memory device performing a program operation are disclosed. The memory device includes an array of memory cells including memory cells coupled to a selected word line, a peripheral circuit to perform a program operation on the memory cells by applying a program voltage to the selected word line, and a control logic to group program pulses to be applied to the memory cells into a plurality of groups according to an order of target threshold voltages of the memory cells, and to control the peripheral circuit so as to apply the program pulses included in the groups to the memory cells in a descending order of representative threshold voltages of the groups, wherein the representative threshold voltage of each group is a lowest target threshold voltage among the target threshold voltages of the plurality of memory cells corresponding to the program pulses included in each group.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0182863, filed on December 10, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure generally relate to a memory device, and more specifically, to a memory device and method for grouping programming pulses applied to memory cells to sequentially execute programming operations. Background Technology

[0004] Memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices store data only when powered on and the stored data is lost when power is off. Non-volatile memory devices retain data even when power is off.

[0005] A memory device can apply programming pulses to memory cells to perform programming operations. As the number of threshold voltage distributions in memory cells increases, it is necessary to improve the threshold voltage distributions of the memory cells so that the number of programming pulses can be increased. Due to the increase in the number of threshold voltage distributions and programming pulses, programming interference may occur, in which the threshold voltage distribution of memory cells with low target threshold voltages widens. Summary of the Invention

[0006] Embodiments of this disclosure may provide a memory device and method for performing programming operations, wherein during the programming operation, a programming pulse corresponding to a memory cell having a high target threshold voltage is applied before applying a programming pulse corresponding to a memory cell having a low target threshold voltage, thereby improving the performance of the programming operation.

[0007] According to embodiments of the present disclosure, a memory device may include: a memory cell array including a plurality of memory cells coupled to a select word line; peripheral circuitry for performing a programming operation on the plurality of memory cells by applying a programming voltage to the select word line; and control logic for grouping a plurality of programming pulses to be applied to the plurality of memory cells into a plurality of groups according to the order of target threshold voltages of the plurality of memory cells, and controlling the peripheral circuitry to apply the programming pulses included in the plurality of groups to the plurality of memory cells in descending order of representative threshold voltages of the plurality of groups, wherein the representative threshold voltage of each of the plurality of groups is the lowest target threshold voltage among the target threshold voltages of the plurality of memory cells corresponding to the programming pulses included in each of the plurality of groups.

[0008] According to embodiments of the present disclosure, a method of operating a memory device may include: grouping a plurality of programming pulses to be applied to a plurality of memory cells into a plurality of groups according to the order of target threshold voltages of a plurality of memory cells coupled to select word lines; determining a representative threshold voltage of each of the plurality of groups as the lowest target threshold voltage among the target threshold voltages of the plurality of memory cells corresponding to the programming pulses included in each of the plurality of groups; and sequentially applying programming pulses corresponding to the representative threshold voltages included in each of the plurality of groups according to the descending order of the representative threshold voltages of the plurality of groups. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a diagram illustrating the programming pulses applied to memory cells during programming operations;

[0011] Figure 3 This is a diagram illustrating the application of programming pulses according to an embodiment of the present disclosure;

[0012] Figure 4 It shows the basis Figure 3 A diagram showing the threshold voltage distribution of the memory cell programmed by the application of programming pulses;

[0013] Figure 5 This is a diagram illustrating the programming pulse application operation and threshold voltage distribution of a memory cell according to another embodiment of the present disclosure;

[0014] Figure 6 This is a diagram illustrating the programming pulse application operation and threshold voltage distribution of a memory cell according to another embodiment of the present disclosure;

[0015] Figure 7 This is a flowchart illustrating programming operations according to embodiments of the present disclosure; and

[0016] Figure 8 This is an exemplary diagram illustrating a data storage system including a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0017] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0018] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The memory device 100 can store data. The memory device 100 may include a memory cell array 110, an address decoder 120, input and output (input / output) circuitry 130, control logic 140, and a voltage generator 150. The memory cell array 110 contains memory cells for storing data, the address decoder 120 is used to decode column addresses, the input / output circuitry 130 is used to transmit data to and receive data from the memory device 100, and the voltage generator 150 is used to generate multiple voltages with various voltage levels.

[0020] Each memory cell included in the memory cell array 110 can be a single-level cell (SLC) that stores 1 bit of data or a memory cell that stores multiple bits of data. Depending on the number of bits in the multiple bits of data, the memory cell that stores multiple bits of data can be a multi-level cell (MLC) that stores 2 bits of data, a three-level cell (TLC) that stores 3 bits of data, a four-level cell (QLC) that stores 4 bits of data, or a five-level cell (PLC) that stores 5 bits of data.

[0021] Address decoder 120 can be connected to memory cell array 110 via word lines. Address decoder 120 can decode an address received from input / output circuitry 130 to select a word line. Address decoder 120 can apply a voltage received from voltage generator 150 to the selected word line. Address decoder 120 can operate in response to control signals received from control logic 140.

[0022] The input / output circuit 130 may include a page buffer that reads data stored in the memory cell and temporarily stores that data. The input / output circuit 130 may output the data stored in the page buffer to an external part of the memory device 100, or it may store data received from an external source in the page buffer and then store the data in the memory cell.

[0023] Control logic 140 can control various operations of memory device 100. Control logic 140 can generate control signals that control address decoder 120, input / output circuit 130 and voltage generator 150 to perform read operations, programming operations and erase operations on memory cell array 110.

[0024] Voltage generator 150 can generate the voltages required for the operation of memory device 100. Voltage generator 150 may include a voltage regulator that generates voltages with various potentials. Voltage generator 150 can generate the programming voltage, verification voltage, and read voltage required by memory device 100. The voltages generated by voltage generator 150 can be supplied to the memory cells included in memory cell array 110 via address decoder 120.

[0025] In embodiments of this disclosure, the address decoder 120, input / output circuitry 130, and voltage generator 150 may be referred to as peripheral circuitry 160. Control logic 140 may control peripheral circuitry 160 to perform operations on memory cells included in memory cell array 110.

[0026] In embodiments of this disclosure, control logic 140 can control peripheral circuitry 160 to perform programming operations on memory cells. Peripheral circuitry 160 can perform a programming pulse application operation to apply a programming pulse to the memory cell, and a verification operation to detect whether the threshold voltage of the memory cell has reached a target threshold voltage distribution.

[0027] Control logic 140 can group programming pulses corresponding to a predetermined target threshold voltage into multiple groups based on the target threshold voltage of the memory cell. Control logic 140 can control peripheral circuitry 160 such that programming pulses included in the group with a high target threshold voltage are applied to the memory cell earlier than programming pulses included in the group with a low target threshold voltage.

[0028] The order in which programming pulses are applied to memory cells can be ordered according to the target threshold voltage. When a programming pulse is applied, a programming disable voltage can be applied to the remaining memory cells to which no programming pulse has been applied. In embodiments of this disclosure, memory cells with high target threshold voltages can complete programming operations before memory cells with low target threshold voltages. Programming pulses included in the group with lower target threshold voltages can be applied to memory cells later. According to embodiments of this disclosure, when a programming pulse application operation is performed on memory cells with high target threshold voltages, programming interference caused by applying programming disable voltages to memory cells with low target threshold voltages that have already completed programming operations can be minimized.

[0029] Figure 2 This is a diagram illustrating the programming pulses applied to a memory cell during a programming operation.

[0030] Reference Figure 2 , Figure 1The peripheral circuitry 160 can perform programming operations on the memory cells. The programming operations can include applying programming pulses and verifying them. The magnitude of the programming pulses applied to the memory cells can gradually increase over time. Figure 2 In the diagram, the horizontal axis represents time, and the vertical axis represents the pulse size.

[0031] For convenience, Figure 2 In this process, the number of programming pulses can be 16. After applying a programming pulse to a memory cell, a verification voltage Vvfy can be applied to the memory cell. The size of the programming pulse can be gradually increased, while the size of the verification voltage Vvfy can be constant.

[0032] When applying according to memory cells Figure 2 When the programming pulse is applied, the programming operation can begin with the memory cell having a low target threshold voltage. A programming disable voltage can be applied to the memory cell that has completed programming until the programming operations of other memory cells are also completed.

[0033] Because the boosting level of memory cells to which a programming disable voltage is applied is low, programming interference that broadens the threshold voltage distribution may occur. Programming interference may occur in memory cells with low target threshold voltages when a high programming pulse is applied to a memory cell with a high target threshold voltage and a programming disable voltage is applied to a memory cell with a low target threshold voltage. More programming interference may occur as the size and number of programming pulses applied to the memory cell increase.

[0034] As the number of bits stored in each memory cell increases, the number and size of programming pulses applied to the memory cell during programming operations need to be increased to improve the threshold voltage distribution of the memory cell. The more memory cells operated using TLC, QLC, and PLC instead of SLC, the more programming interference may occur.

[0035] This disclosure provides a method for minimizing programming interference that occurs during programming operations.

[0036] Figure 3 This is a diagram illustrating the application of programming pulses according to an embodiment of the present disclosure.

[0037] Reference Figure 3 It can group multiple programming pulses and apply the programming pulses included in each group to the memory cell according to the order of the multiple groups. Figure 3 For convenience, the memory cell can be a TLC, and 16 programming pulses can be applied to the memory cell during programming operations.

[0038] Figure 1 The control logic 140 can group multiple programming pulses to be applied to the memory cells into multiple groups according to the order of the target threshold voltages of the memory cells. The control logic 140 can group the programming pulses corresponding to a predetermined number of target threshold voltages in descending order, starting from the highest target threshold voltage, so that they are included in each of the multiple groups. In another embodiment of this disclosure, the control logic 140 can group the programming pulses corresponding to a predetermined number of target threshold voltages in ascending order, starting from the lowest target threshold voltage, so that they are included in each of the multiple groups.

[0039] exist Figure 3 In this configuration, control logic 140 can divide 16 programming pulses into four groups. Control logic 140 can group the programming pulses corresponding to the highest and second-highest threshold voltages of the TLC (i.e., the seventh and sixth threshold voltages) into a first group 310, the programming pulses corresponding to the fifth and fourth threshold voltages into a second group 320, the programming pulses corresponding to the third and second threshold voltages into a third group 330, and the programming pulses corresponding to the lowest threshold voltage for the TLC (i.e., the first threshold voltage) into a fourth group 340. Each group can include four programming pulses. The threshold voltages of the TLC can include seven threshold voltages, gradually increasing from the first threshold voltage to the seventh threshold voltage. The seventh threshold voltage can be the highest threshold voltage of the TLC.

[0040] In embodiments of this disclosure, control logic 140 may determine a representative threshold voltage for each of a plurality of groups. Control logic 140 may determine the lowest target threshold voltage among the target threshold voltages corresponding to each group as the representative threshold voltage. In another embodiment of this disclosure, control logic 140 may determine one of the target threshold voltages corresponding to each group as the representative threshold voltage. For example, the representative threshold voltage may be the highest threshold voltage or an intermediate value among the target threshold voltages corresponding to that group. The target threshold voltages corresponding to each of the plurality of groups do not overlap with each other, therefore one of the target threshold voltages corresponding to that group may be the representative threshold voltage.

[0041] Control logic 140 can control peripheral circuitry 160 to apply programming pulses corresponding to the representative threshold voltages to memory cells in descending order, i.e., from the highest representative threshold voltage to the lowest representative threshold voltage. Figure 3In one embodiment, control logic 140 may determine the lowest threshold voltage among the target threshold voltages corresponding to each group as the representative threshold voltage. That is, the representative threshold voltage of the first group 310 is the sixth threshold voltage among the sixth and seventh threshold voltages, the representative threshold voltage of the second group 320 is the fourth threshold voltage among the fourth and fifth threshold voltages, the representative threshold voltage of the third group 330 is the second threshold voltage among the second and third threshold voltages, and the representative threshold voltage of the fourth group 340 is the first threshold voltage. Control logic 140 may apply programming pulses in descending order of the representative threshold voltages. That is, programming pulses included in the first group 310 may be applied to the memory cells first, followed by programming pulses included in the second group 320.

[0042] Control logic 140 can control peripheral circuitry 160 to apply programming pulses included in the first group 310 to memory cells. When programming pulses included in the first group 310 are applied, programming disable voltages are applied to memory cells corresponding to programming pulses included in the remaining groups, namely the second group 320, the third group 330, and the fourth group 340.

[0043] Control logic 140 controls peripheral circuitry 160 to first apply programming pulses included in the first group 310 to memory cells, and then apply programming pulses included in the second group 320 to memory cells. When programming pulses included in the second group 320 are applied to memory cells, a programming disable voltage is applied to memory cells corresponding to the programming pulses included in the remaining groups, namely the first group 310, the third group 330, and the fourth group 340.

[0044] Similarly, control logic 140 can control peripheral circuitry 160 such that, after applying programming pulses from the second group 320 to memory cells, programming pulses from the third group 330 and the fourth group 340 are sequentially applied to the memory cells. When programming pulses from the third group 330 and the fourth group 340 are applied, programming disable voltages are applied to the memory cells corresponding to the programming pulses from the remaining groups.

[0045] Figure 3This is merely an embodiment of the present disclosure, therefore the number of groups including programming pulses and the number of programming pulses included in each group can be different. For example, the first group 310 may include 8 programming pulses, the second group 320 may include 4 programming pulses, and the third group 330 may include 4 programming pulses. Optionally, the target threshold voltage corresponding to the programming pulses included in the first group 310 may be a seventh threshold voltage, a sixth threshold voltage, a fifth threshold voltage, and a fourth threshold voltage, and the target threshold voltage corresponding to the programming pulses included in the second group 320 may be a third threshold voltage, a second threshold voltage, and a first threshold voltage.

[0046] Figure 4 It is a description based on Figure 3 A diagram illustrating the threshold voltage distribution of a memory cell programmed by applying a programming pulse.

[0047] Reference Figure 4 The diagram shows the threshold voltage distribution of a memory cell, and how this threshold voltage distribution changes as a programming pulse is applied to the memory cell. Figure 4 This can refer to when applying force to a memory cell. Figure 3 The change in the threshold voltage distribution of the memory cell during the programming pulse. Similar to... Figure 3 The memory cell can be a TLC.

[0048] As a programming pulse is applied, the threshold voltage of a memory cell in the erase state can be changed from the first threshold voltage distribution PV1 to the seventh threshold voltage distribution PV7. When a programming pulse included in the first group 310 is applied to a memory cell, the threshold voltage distribution of the memory cell can be changed to the sixth threshold voltage distribution PV6 and the seventh threshold voltage distribution PV7 410. When a programming pulse included in the first group 310 is applied, a programming inhibit voltage is applied to the memory cells corresponding to the programming pulses included in the second group 320, the third group 330, and the fourth group 340, so that the threshold voltage distribution of the remaining memory cells can remain unchanged.

[0049] When programming pulses included in the second group 320 are applied to a memory cell, the threshold voltage distribution of the memory cell can be changed to a fourth threshold voltage distribution PV4 and a fifth threshold voltage distribution PV5 420. When programming pulses included in the second group 320 are applied, a programming inhibit voltage is applied to the memory cell corresponding to the programming pulses included in the first group 310, so that the threshold voltages of the memory cells having a sixth threshold voltage distribution PV6 and a seventh threshold voltage distribution PV7 can remain unchanged. Similarly, programming pulses included in the third group 330 are applied to change the threshold voltage distribution of the memory cell to a second threshold voltage distribution PV2 and a third threshold voltage distribution PV3 430, and programming pulses included in the fourth group 340 can be applied to change the threshold voltage distribution of the memory cell to a first threshold voltage distribution PV1 440.

[0050] Because the programming pulses included in the first group 310 to the fourth group 340 are applied sequentially to the memory cells, the threshold voltage distribution of the memory cells changes in the order of 410, 420, 430, and 440. The memory cells corresponding to the first threshold voltage distribution PV1, the second threshold voltage distribution PV2, and the third threshold voltage distribution PV3 are programmed later than the memory cells corresponding to the fourth threshold voltage distribution PV4 to the seventh threshold voltage distribution PV7. Since programming interference occurs in memory cells with lower target threshold voltages compared to memory cells with higher target threshold voltages, programming interference can be minimized when memory cells with relatively lower target threshold voltages are programmed later than memory cells with higher target threshold voltages.

[0051] Figure 5 This is a diagram illustrating the programming pulse application operation and threshold voltage distribution of a memory cell according to another embodiment of the present disclosure.

[0052] Reference Figure 5 This can illustrate the programming pulse applied to a memory cell and the change in the threshold voltage distribution of the memory cell under the application of the programming pulse. For convenience, in Figure 5 In this configuration, the memory cell can be a QLC, the number of programming pulse groups is 2, and the number of programming pulses can be 16.

[0053] Figure 1The control logic 140 can group the programming pulses corresponding to the eight target threshold voltages into a first group 510, starting in descending order, i.e., from the highest target threshold voltage among the target threshold voltages of the memory cells, and can group the remaining target threshold voltages into a second group 520. The first group 510 and the second group 520 can each contain the same number of programming pulses: eight. The number of target threshold voltages corresponding to the programming pulses in the first group 510 is eight, and the number of target threshold voltages corresponding to the programming pulses in the second group 520 is seven.

[0054] Compared to the programming pulses included in the second group 520, the programming pulses included in the first group 510 can be applied to the memory cells earlier. In response to the application of the programming pulses included in the first group 510, the threshold voltage of the memory cell in the erase state changes from the eighth threshold voltage distribution PV8 to the fifteenth threshold voltage distribution PV15 511. When the programming pulses included in the first group 510 are applied, a programming disable voltage can be applied to the memory cell corresponding to the programming pulses included in the second group 520.

[0055] After the programming pulses included in the first group 510 are applied, programming pulses included in the second group 520 can be applied to the memory cells. When the programming pulses included in the second group 520 are applied, a programming disable voltage can be applied to the memory cells corresponding to the programming pulses included in the first group 510. The threshold voltage of the memory cells corresponding to the programming pulses included in the first group 510 may remain unchanged, and the threshold voltage of the memory cells corresponding to the programming pulses included in the second group 520 may be changed from the first threshold voltage distribution PV1 to the seventh threshold voltage distribution PV7 521.

[0056] Figure 6 This is a diagram illustrating the programming pulse application operation and threshold voltage distribution of a memory cell according to another embodiment of the present disclosure.

[0057] Reference Figure 6 This can illustrate the programming pulse applied to a memory cell and the change in the threshold voltage distribution of the memory cell under the application of the programming pulse. For convenience, in Figure 6 In this configuration, the memory cell can be a QLC, the number of programming pulse groups is 4, and the number of programming pulses can be 16. Figure 6 In the middle, "and" can be omitted. Figure 5 The description in the text is a repetitive description.

[0058] Figure 1The control logic 140 can group the programming pulses corresponding to the eight target threshold voltages arranged in descending order among the target threshold voltages of the memory cell into the first group 610, group the programming pulses not included in the first group 610 and corresponding to the four target threshold voltages arranged in descending order among the target threshold voltages into the second group 620, group the programming pulses not included in the first group 610 and the second group 620 and corresponding to the two target threshold voltages arranged in descending order among the high target threshold voltages into the third group 630, and group the remaining programming pulses into the fourth group 640.

[0059] The programming pulses included in the first group 610 may correspond to the eighth threshold voltage distribution PV8 to the fifteenth threshold voltage distribution PV15, and the first group 610 may include 8 programming pulses. The programming pulses included in the second group 620 may correspond to the fourth threshold voltage distribution PV4 to the seventh threshold voltage distribution PV7, and the second group 620 may include 4 programming pulses. The programming pulses included in the third group 630 may correspond to the second threshold voltage distribution PV2 and the third threshold voltage distribution PV3, and the third group 630 may include 2 programming pulses. The programming pulses included in the fourth group 640 may correspond to the first threshold voltage distribution PV1, and the fourth group 640 may include 2 programming pulses.

[0060] Compared to the programming pulses included in the second group 620, the programming pulses included in the first group 610 can be applied to the memory cells earlier. In response to the application of the programming pulses included in the first group 610, the threshold voltage of the memory cells in the erase state changes from the eighth threshold voltage distribution PV8 to the fifteenth threshold voltage distribution PV15 611. When the programming pulses included in the first group 610 are applied, programming disable voltages can be applied to the memory cells corresponding to the programming pulses included in the second group 620, the third group 630, and the fourth group 640.

[0061] Because the programming pulses included in the first group 610 to the fourth group 640 are applied sequentially, the threshold voltage distribution of the memory cells changes in the order of 611, 621, 631, and 641. The memory cells corresponding to the first threshold voltage distribution PV1, the second threshold voltage distribution PV2, and the third threshold voltage distribution PV3 are programmed later than the memory cells corresponding to the fourth threshold voltage distribution PV4 to the fifteenth threshold voltage distribution PV15.

[0062] In embodiments of this disclosure, the number of target threshold voltages corresponding to programming pulses included in the first group 610 may be greater than or equal to the number of target threshold voltages corresponding to programming pulses included in the second group 620. That is, the number of target threshold voltages corresponding to programming pulses included in a group applied later to the memory cell may be less than or equal to the number of target threshold voltages corresponding to programming pulses applied first to the memory cell. Control logic 140 may group the number of target threshold voltages corresponding to programming pulses included in each of the second group 620, the third group 630, and the fourth group 640 into groups less than or equal to the number of target threshold voltages corresponding to programming pulses included in the first group 610.

[0063] because Figure 5 and Figure 6 This is merely an example, so the number of groups including programming pulses and the number of programming pulses included in each group can vary. For example, the number of programming pulses included in each group can be the same, or the number of target threshold voltages corresponding to the programming pulses included in each group can be the same.

[0064] Figures 3 to 6 The illustration shows the case where the memory cell is a TLC or QLC. However, when the memory cell is a PLC or higher, control logic 140 can control peripheral circuitry 160 to group programming pulses and apply the programming pulses included in the group with a high target threshold voltage to the memory cell first. The programming pulses included in the group with a low target threshold voltage can be applied later to minimize programming interference occurring in the memory cell with the low target threshold voltage.

[0065] Figure 7 This is a flowchart illustrating programming operations according to embodiments of the present disclosure. Figure 7 The programming operations can be performed by Figure 1 The memory device 100 executes.

[0066] Reference Figure 7 The memory device 100 can apply programming pulses to memory cells to perform programming operations. The memory device 100 can group the programming pulses according to the order of target threshold voltages, and first apply the programming pulses included in the group with the highest target threshold voltage to the memory cells. The order in which programming pulses are applied to the memory cells can be ordered to minimize programming interference occurring in memory cells with relatively low target threshold voltages.

[0067] In S710, control logic (e.g., Figure 1The control logic 140 can group the programming pulses to be applied to the memory cells connected to the select word line into multiple groups according to the order of the target threshold voltages of the memory cells. For each of the multiple groups, the control logic can group the programming pulses corresponding to a predetermined number of target threshold voltages of the memory cells arranged in descending order (i.e., from the highest target threshold voltage to the lowest target threshold voltage).

[0068] In embodiments of this disclosure, the control logic can group programming pulses corresponding to m target threshold voltages arranged in descending order into a first group, and group programming pulses corresponding to n target threshold voltages arranged in descending order among the remaining target threshold voltages into a second group, where m and n are natural numbers, and m can be greater than or equal to n.

[0069] The control logic can determine the representative threshold voltage for each of the multiple groups. The control logic can determine the lowest target threshold voltage among the target threshold voltages of the memory cells corresponding to the programming pulses included in each of the multiple groups as the representative threshold voltage for each of the multiple groups.

[0070] In S720, the control logic can apply a programming pulse from the highest representative threshold voltage among multiple groups to a memory cell. The programming pulse applied to the memory cell can be determined based on the representative threshold voltage. When the programming pulse from the highest group is applied, the control logic can apply a programming disable voltage to the remaining memory cells other than the memory cell corresponding to the programming pulse from the highest group.

[0071] In S721, the control logic can perform a verification operation on the memory cell to which the programming pulse included in the highest group has been applied. If the verification operation results in successful verification, S730 is executed. If the verification operation results in failed verification, S722 is executed.

[0072] In S722, the control logic compares the magnitude of the programming pulse applied to the memory cell with the magnitude of a reference voltage determined based on a representative threshold voltage. When the magnitude of the programming pulse applied to the memory cell is less than or equal to the magnitude of the reference voltage, the control logic increases the magnitude of the programming voltage by one step (S723). After S723, in S720, the increased programming pulse can be reapplied to the memory cell. The operation of increasing the magnitude of the programming pulse based on the verification result corresponds to the Incremental Step Pulse Programming (ISPP) operation. When the magnitude of the programming pulse applied to the memory cell is greater than the magnitude of the reference voltage, the control logic can terminate the programming pulse application operation for the memory cell corresponding to the highest group. Subsequently, S730 can be executed.

[0073] In S730, the control logic can apply programming pulses from the second-highest group of multiple groups to the memory cell based on a representative threshold voltage. The operation of applying programming pulses to the memory cell can correspond to the descriptions of S720 to S723.

[0074] The control logic can control the peripheral circuitry to sequentially apply programming pulses, included in each of multiple groups, to memory cells in descending order of representative threshold voltages.

[0075] In S740, the control logic applies a programming pulse to the memory cell, specifically the lowest group containing the lowest representative threshold voltage from among multiple groups. In S741, the control logic performs a verification operation on the memory cell corresponding to the applied programming pulse. The programming operation can be terminated if the verification operation results in a successful verification. S742 can be executed if the verification operation results in a failed verification. In S742, the control logic compares the magnitude of the programming pulse applied to the memory cell with the magnitude of a reference voltage. The programming operation can be terminated if the magnitude of the programming pulse is greater than the magnitude of the reference voltage. S743 can be executed if the magnitude of the programming pulse is less than or equal to the magnitude of the reference voltage. In S743, the control logic increases the magnitude of the programming pulse by a predetermined amount. After S743, S740 can be executed again to apply the increased programming pulse to the memory cell. The operation of applying a programming pulse to the memory cell corresponds to the descriptions of S720 to S723.

[0076] Figure 7 The description of each operation in the middle can be compared with Figures 1 to 6 The description corresponds to that.

[0077] Figure 8 This is a diagram illustrating a data storage system 2000 including a memory system according to an embodiment of the present disclosure.

[0078] Reference Figure 8 The data storage system 2000 may include a host device 2100 and an SSD 2200.

[0079] The SSD 2200 may include a controller 2210, a buffer memory device 2220, non-volatile memory 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260. The SSD 2200 may include... Figures 1 to 7 The memory device 100 described.

[0080] The buffer memory device 2220 can temporarily store data to be stored in the non-volatile memories 2231 to 223n. Additionally, the buffer memory device 2220 can temporarily store data read from the non-volatile memories 2231-223n. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the non-volatile memories 2231 to 223n under the control of the controller 2210.

[0081] Non-volatile memories 2231 to 223n can be used as storage media for the SSD 2200. Each of the non-volatile memories 2231 to 223n can be connected to the controller 2210 through multiple channels CH1 to CHn. One or more non-volatile memories can be connected to one channel. Non-volatile memories connected to one channel can be connected to the same signal bus and data bus.

[0082] The controller 2210 can control various operations of the SSD 2200. In embodiments of this disclosure, the controller 2210 can control the SSD 2200 to perform programming operations. The controller 2210 can group programming pulses applied to the memory cells to be programmed into multiple groups, and control the SSD 2200 to apply the programming pulses included in the multiple groups to the memory cells in descending order of the target threshold voltage. Therefore, the threshold voltage distribution of the non-volatile memories 2231 to 223n can be improved.

[0083] Power supply 2240 can provide power PWR, input via power connector 2260, to the internal components of SSD 2200. Power supply 2240 may include auxiliary power supply 2241. Auxiliary power supply 2241 can supply power so that SSD 2200 can terminate normally in the event of a sudden power outage. Auxiliary power supply 2241 may include a large-capacity capacitor capable of charging the power PWR.

[0084] The controller 2210 can exchange signals SGL with the host device 2100 via signal connector 2250. Signal SGL may include commands, addresses, data, etc. Depending on the interface between the host device 2100 and the SSD 2200, signal connector 2250 may include various types of connectors.

[0085] This invention is defined by the appended claims rather than the foregoing detailed descriptions, and all modifications and variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in this invention.

[0086] According to embodiments of this disclosure, a memory device and a programming operation method for improving the performance of programming operations are provided. By grouping programming pulses applied to memory cells according to the order of target threshold voltages, and applying programming pulses corresponding to groups with high target threshold voltages earlier than programming pulses corresponding to groups with low target threshold voltages, the memory device can reduce programming interference in which the threshold voltage distribution of memory cells with low target threshold voltages becomes wider. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A memory device, comprising: A memory cell array, comprising multiple memory cells connected to a select word line; The peripheral circuitry performs programming operations on the plurality of memory cells by applying a programming voltage to the select word line; as well as The control logic groups multiple programming pulses to be applied to the multiple memory cells into multiple groups according to the order of the target threshold voltages of the multiple memory cells, and controls the peripheral circuitry to apply the programming pulses included in the multiple groups to the multiple memory cells in descending order of the representative threshold voltages of the multiple groups. The representative threshold voltage of each of the plurality of groups is the lowest target threshold voltage among the target threshold voltages of a plurality of memory cells corresponding to the programming pulses included in each of the plurality of groups.

2. The memory device according to claim 1, wherein, The control logic groups the programming pulses corresponding to the m target threshold voltages arranged in descending order from the target threshold voltages of the plurality of memory cells into a first group, and groups the programming pulses corresponding to the n target threshold voltages arranged in descending order from the remaining target threshold voltages into a second group. Where m is greater than or equal to n.

3. The memory device according to claim 2, wherein, The control logic controls the peripheral circuitry such that the programming pulses included in the first group are applied to the plurality of memory cells before the second group.

4. The memory device according to claim 3, wherein, When the programming pulse included in the first group is applied, the control logic controls the peripheral circuit to apply a programming disable voltage to the remaining memory cells among the plurality of memory cells, excluding the memory cells corresponding to the programming pulses included in the first group.

5. The memory device according to claim 3, wherein, After completing the operation of applying the programming pulses included in the first group, the control logic controls the peripheral circuitry to apply the programming pulses included in the second group to the plurality of memory cells.

6. The memory device according to claim 5, wherein, When the programming pulse included in the second group is applied, the control logic controls the peripheral circuit to apply a programming disable voltage to the remaining memory cells among the plurality of memory cells, excluding the memory cells corresponding to the programming pulses included in the second group.

7. The memory device according to claim 1, wherein, The control logic groups programming pulses corresponding to a predetermined number of target threshold voltages arranged in ascending order among the target threshold voltages of the plurality of memory cells into each of the plurality of groups.

8. The memory device according to claim 7, wherein, The control logic controls the application of programming pulses included in the plurality of groups to the plurality of memory cells in descending order of the representative threshold voltage.

9. The memory device according to claim 8, wherein, The control logic controls the peripheral circuit to apply a programming disable voltage to the remaining memory cells among the plurality of memory cells, excluding the memory cells corresponding to the applied programming pulse.

10. The memory device according to claim 9, wherein, The programming pulse is determined based on a representative threshold voltage of the group associated with the programming pulse, and The control logic increases the size of the programming pulse in response to a verification failure of the memory cell to which the programming pulse is applied.

11. The memory device according to claim 10, wherein, The control logic responds to the fact that the magnitude of the programming pulse exceeds the magnitude of the reference voltage determined based on the representative threshold voltage, and completes the programming pulse application operation on the memory cell to which the programming pulse is applied.

12. A method of operating a memory device, the method comprising: Based on the order of the target threshold voltages of the multiple memory cells connected to the select word line, the multiple programming pulses to be applied to the multiple memory cells are grouped into multiple groups; The representative threshold voltage of each of the plurality of groups is determined as the lowest target threshold voltage among the target threshold voltages of a plurality of memory cells corresponding to the programming pulses included in each of the plurality of groups; as well as Programming pulses corresponding to the representative threshold voltages included in each of the plurality of groups are applied sequentially according to the descending order of the representative threshold voltages of the plurality of groups.

13. The method according to claim 12, wherein, Grouping the plurality of programming pulses includes: grouping the programming pulses corresponding to a predetermined number of target threshold voltages arranged in descending order among the target threshold voltages of the plurality of memory cells into the plurality of groups respectively.

14. The method according to claim 13, wherein, Grouping the plurality of programming pulses includes: The programming pulses corresponding to the m target threshold voltages arranged in descending order among the target threshold voltages of the plurality of memory cells are grouped into a first group; and The programming pulses corresponding to the n target threshold voltages arranged in descending order from the remaining target threshold voltages are grouped into a second group, and Where m is greater than or equal to n.

15. The method according to claim 12, wherein, Grouping the plurality of programming pulses includes grouping programming pulses corresponding to a predetermined number of target threshold voltages arranged in ascending order among the target threshold voltages of the plurality of memory cells into each of the plurality of groups.

16. The method according to claim 15, wherein, The number of target threshold voltages corresponding to the group in which the included programming pulses are applied is less than or equal to the number of target threshold voltages corresponding to the group in which the application of the included programming pulses has ended.

17. The method according to claim 12, wherein, Applying the programming pulse includes applying a programming disable voltage to the remaining memory cells in the plurality of memory cells, excluding the memory cells corresponding to the programming pulses included in the group to which the programming pulse was applied.

18. The method according to claim 12, wherein, Applying the programming pulse includes: Apply a programming pulse determined based on the representative threshold voltage from among the programming pulses included in each of the plurality of groups; In response to a failure in the verification of the memory cell to which the programming pulse was applied, the size of the programming pulse is increased; and In response to the programming pulse magnitude exceeding the magnitude of a reference voltage determined based on the representative threshold voltage, the programming pulse application operation on the memory cell to which the programming pulse was applied is terminated.

19. The method of claim 14, wherein, Applying the programming pulse includes: A programming pulse corresponding to the representative threshold voltage from the programming pulses included in the first group is applied to the plurality of memory cells; When the programming pulse in the first group is applied, a programming disable voltage is applied to the remaining memory cells in the plurality of memory cells other than the memory cells corresponding to the programming pulses included in the first group; After completing the application of programming pulses to the first group, programming pulses included in the second group are applied to the plurality of memory cells; and When the programming pulse in the second group is applied, the programming disable voltage is applied to the remaining memory cells in the plurality of memory cells, excluding the memory cells corresponding to the programming pulses included in the second group.

Images