Test method, device, equipment and medium for DRAM data retention time
By writing to and reading from DRAM memory cells one by one and adjusting the latency to determine the data retention time, the problem of insufficient test accuracy in existing technologies is solved, achieving higher test coverage and precision.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KINGTIGER TESTING TECH (SZ) LTD
- Filing Date
- 2026-05-14
- Publication Date
- 2026-06-12
Smart Images
Figure CN122201395A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage testing technologies, and in particular, to a method, apparatus, device, and medium for testing the data retention time of DRAM. Background Art
[0002] The principle of DRAM is to store the written data through capacitors. Since the capacitors will leak electricity over time, resulting in data loss, the data in DRAM needs to be refreshed periodically to ensure that the data remains unchanged for a long time. The data retention time is one of the key reliability indicators of DRAM, which represents the longest time that the storage unit can correctly retain data without performing a refresh operation. Therefore, it is crucial to quickly and accurately evaluate the limit data retention time of DRAM to ensure memory reliability and improve system stability.
[0003] The existing methods for testing the data retention time of DRAM usually set background data such as all 0s, all 1s, or all check boards (checkerboard pattern) for each storage unit in DRAM, and then read the stored data after a specified time interval. The data retention time is obtained based on whether the data fails. For example, in the patent application with the publication number CN112037843A, aiming at the problem that the data retention ability of the memory changes with the increase of the test time, so the data retention time obtained by only standing still for a specified time once is not accurate. By performing operations of writing and then standing still and reading the memory multiple times, modifying the standing still time each time, and according to the multiple test results, requiring the memory to pass multiple tests, and determining the failure of the entire memory as long as there is a failure of any storage unit once, the failed storage unit can be accurately detected, increasing the coverage rate of the memory test. For the storage units that pass a single test, they need to pass multiple tests to be considered qualified, and the maximum standing still time in multiple tests considered qualified is taken as the data retention time of the memory.
[0004] However, such a test method cannot cover the harsh environments encountered by DRAM during actual high-speed and high-density operations, and the data retention time will also change under the influence of harsh environments. Therefore, the accuracy of the data retention time of DRAM determined by the test is not high. Summary of the Invention
[0005] In view of this, the purpose of this application is to overcome the deficiencies in the prior art and provide a method for testing the data retention time of DRAM, the method comprising: Writing all storage units of the DRAM into a first state; Each of the memory cells of the DRAM is sequentially used as a target memory cell. For each target memory cell, the target memory cell is written to a second state and data is read from the target memory cell. The data retention time of the target memory cell is determined based on the data reading result. The data retention time of the DRAM is determined based on the data retention time of all the target storage cells.
[0006] In one embodiment, the steps of writing the target storage unit to a second state, reading data from the target storage unit, and determining the data retention time of the target storage unit based on the data reading result include: The target storage unit is written to the second state, and after waiting for the target waiting time, the target storage unit is read from the data, and the target waiting time is adjusted based on the data reading result. Based on the adjusted target waiting time, the steps of writing to the target storage unit and reading data from the target storage unit are repeated to continuously adjust the target waiting time; The data retention time of the target storage unit is obtained until the target waiting time meets the preset conditions.
[0007] In one embodiment, the step of adjusting the target waiting time based on the data reading result includes: If the data reading result is successful, then increase the target waiting time; If the data reading result is a reading failure, then the target waiting time is reduced.
[0008] In one embodiment, the method further includes: Based on the current target waiting time and the theoretical data retention time of the DRAM, determine the time adjustment step size; The target waiting time can be increased or decreased based on the time adjustment step size.
[0009] In one embodiment, the step of obtaining the data retention time of the target storage unit until the target waiting time meets a preset condition includes: If the difference between the latest preset number of adjusted target waiting times is less than a preset threshold, then the target waiting time is determined to meet the preset conditions. The data retention time of the target storage unit is determined based on a preset number of adjusted target waiting times.
[0010] In one embodiment, the step of determining the data retention time of the DRAM based on the data retention time of all the target storage cells includes: Compare the data retention times of all the target storage units to determine the minimum data retention time; The minimum data retention time is determined as the data retention time of the DRAM.
[0011] This application also provides a testing apparatus for DRAM data retention time, the testing apparatus for DRAM data retention time comprising: The write module is used to write all memory cells of the DRAM to the first state; The first determining module is used to sequentially take each of the memory cells of the DRAM as a target memory cell, write the target memory cell to a second state for each target memory cell, and read data from the target memory cell, and determine the data retention time of the target memory cell based on the data reading result; The second determining module is used to determine the data retention time of the DRAM based on the data retention time of all the target storage cells.
[0012] This application also provides a computer device, the computer device including a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the above-described DRAM data retention time test method.
[0013] This application also provides a computer-readable storage medium storing a computer program that, when run on a processor, executes the above-described method for testing DRAM data retention time.
[0014] The embodiments of this application have the following beneficial effects: In this embodiment, all memory cells of the DRAM are written to a first state; each memory cell of the DRAM is sequentially used as a target memory cell, and for each target memory cell, it is written to a second state and data is read from the target memory cell. The data retention time of the target memory cell is determined based on the data read results; the data retention time of the DRAM is determined based on the data retention times of all target memory cells. By clearing the capacitor charge in all memory cells of the DRAM to zero and writing to the target memory cell, a memory cell containing the data "1" is created in the DRAM. This constructs a harsh environment encountered by the DRAM in actual high-speed, high-density operation, and then tests to determine the data retention time of the DRAM, improving the accuracy of the data retention time of the DRAM determined by the test. Attached Figure Description
[0015] To more clearly illustrate the technical methods of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 A flowchart illustrating the first embodiment of the DRAM data retention time testing method provided in this application; Figure 2 A schematic diagram of the structure of the DRAM memory cell matrix provided in this application; Figure 3 A schematic diagram illustrating the implementation process of the DRAM data retention time test method provided in this application; Figure 4 A flowchart illustrating a second embodiment of the DRAM data retention time testing method provided in this application; Figure 5 A schematic diagram of the circuit structure of a DRAM memory cell and its associated circuitry provided in this application; Figure 6 A schematic diagram of voltage changes when a memory cell of the DRAM provided in this application is read; Figure 7 A schematic diagram of voltage changes when a memory cell of the DRAM provided in this application fails to be read; Figure 8 A schematic diagram of the structure of the DRAM data retention time test apparatus provided in this application. Detailed Implementation
[0017] The technical methods in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0018] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0019] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.
[0020] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.
[0022] It is understood that the method of this application is applied to a memory testing device, which can be electrically or communicatively connected to DRAM to test the data retention time of DRAM. The memory testing device can be a smart terminal, PC terminal, mobile terminal, etc., and is not limited thereto. For ease of description, the following embodiments are described using the memory testing device as the execution subject.
[0023] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0024] Please refer to Figure 1 , Figure 1 A flowchart illustrating a first embodiment of the DRAM data retention time testing method provided in this application, the method comprising: Step S101: Write all memory cells of the DRAM to the first state.
[0025] Step S102: Each of the memory cells of the DRAM is sequentially used as a target memory cell. For each target memory cell, the target memory cell is written to a second state and data is read from the target memory cell. The data retention time of the target memory cell is determined based on the data reading result.
[0026] In this embodiment, the memory testing device writes all memory cells of the DRAM to a first state, where the first state is when 0 is written into the memory cell. The memory testing device sequentially uses each memory cell of the DRAM as a target memory cell, writes the target memory cell to a second state for each target memory cell, and reads data from the target memory cell. Based on the data reading results, the data retention time of the target memory cell is determined; where the second state is when 1 is written into the memory cell.
[0027] It should be noted that, as Figure 2 As shown, the DRAM consists of a matrix of N rows (WL0-WLN) and N columns (BL0-BLN) of memory cells. The target memory cell is located in the first row (WL0) and first column (BL0). The memory testing device selects only one target memory cell at a time, writes a 1 to the target memory cell, and then performs a test on the data retention time of the target memory cell, that is, a test on the data retention time of the target memory cell. The remaining memory cells are written with 0.
[0028] It should be noted that after waiting for the target waiting time, the memory testing device reads data from the target storage unit and adjusts the target waiting time based on the data reading result. Based on the adjusted target waiting time, the steps of writing to and reading from the target storage unit are repeated to continuously adjust the target waiting time until the target waiting time meets the preset conditions, thus obtaining the data retention time of the target storage unit.
[0029] Step S103: Determine the data retention time of the DRAM based on the data retention time of all the target storage cells.
[0030] In this embodiment, the memory testing device takes each storage cell in the DRAM as a target storage cell, tests the data retention time of each target storage cell, and then determines the data retention time of the DRAM based on the data retention time of all target storage cells.
[0031] In one embodiment, the step of determining the data retention time of the DRAM based on the data retention time of all the target storage cells includes: Step S1031: Compare the data retention times of all the target storage units to determine the minimum data retention time.
[0032] Step S1032: The minimum data retention time is determined as the data retention time of the DRAM.
[0033] In this embodiment, the memory testing device compares the data retention times of all target memory cells to determine the minimum data retention time, which is then set as the DRAM data retention time. It should be noted that the data retention time is different for each target memory cell; the minimum data retention time is the earliest time data failure occurs, therefore, the minimum data retention time is set as the DRAM data retention time.
[0034] In one embodiment, such as Figure 3 As shown, the memory testing device first initializes the row and column addresses of the memory cell matrix in the DRAM and writes 0 to each memory cell in the matrix. The device then reverses the data of a memory cell at a specific row (Xi) and column (Yi) address by writing 1, creating a harsh environment for the stored data 1. After a pause time T, the device reads back the 1. If the readback shows the data is invalid, the data retention time of that memory cell is less than T; otherwise, the data retention time is greater than T. The process of adjusting T and repeatedly writing 1 to and reading from the target memory cell continues until T meets a preset condition, thus obtaining the data retention time of the target memory cell. After determining the data retention times of the memory cells at addresses Xi and Yi, the device repeats the above method to determine the data retention times of the memory cells at addresses Xi+N and Yi, and finally, compares the data retention times of each memory cell and determines the minimum data retention time as the DRAM's data retention time.
[0035] The memory testing device in this embodiment writes all memory cells of the DRAM to a first state; each memory cell of the DRAM is sequentially used as a target memory cell, and for each target memory cell, it is written to a second state and data is read from the target memory cell. The data retention time of the target memory cell is determined based on the data read results; the data retention time of the DRAM is determined based on the data retention time of all target memory cells. By clearing the capacitor charge in all memory cells of the DRAM to zero and writing to the target memory cell, a memory cell containing the data "1" is created in the DRAM. This constructs a harsh environment encountered by the DRAM in actual high-speed, high-density operation, and then tests to determine the data retention time of the DRAM, improving the accuracy of the data retention time of the DRAM determined by the test.
[0036] Please refer to Figure 4 , Figure 4This is a flowchart illustrating a second embodiment of the DRAM data retention time testing method provided in this application. The difference between the second embodiment and the first embodiment is that the steps of writing the target memory cell to a second state, reading data from the target memory cell, and determining the data retention time of the target memory cell based on the data reading result include: Step S201: Write the target storage unit to the second state and after waiting for the target waiting time, read the data from the target storage unit and adjust the target waiting time based on the data reading result.
[0037] In this embodiment, the memory testing device writes the target storage cell to the second state and waits for the target waiting time before reading data from the target storage cell and adjusting the target waiting time based on the data reading results. It should be noted that the target waiting time is preset and can be set based on the nominal data retention time of the DRAM or determined based on empirical values; no limitation is made here.
[0038] In one embodiment, the step of adjusting the target waiting time based on the data reading result includes: Step S2011: If the data reading result is successful, then increase the target waiting time.
[0039] Step S2012: If the data reading result is a reading failure, then reduce the target waiting time.
[0040] In this embodiment, the memory testing device reads data from the target storage unit. If the data read is successful, it indicates that the target waiting time is less than the data retention time of the target storage unit. In this case, the target waiting time needs to be increased before proceeding to the next round of testing. If the data read fails, it indicates that the target waiting time is greater than the data retention time of the target storage unit. In this case, the target waiting time needs to be reduced before proceeding to the next round of testing.
[0041] In one embodiment, the method further includes: determining a time adjustment step size based on the current target waiting time and the theoretical data retention time of the DRAM; and increasing or decreasing the target waiting time based on the time adjustment step size.
[0042] It is understandable that the theoretical data retention time is the data retention time specified by the DRAM manufacturer. The memory testing equipment continuously adjusts the target latency. Before each adjustment, it calculates the difference between the current target latency and the theoretical data retention time of the DRAM, and determines the time adjustment step size based on this difference. The time adjustment step size is less than or equal to this difference, and then the target latency is increased or decreased based on the time adjustment step size.
[0043] Exemplarily, the memory test device can determine the data retention time of the target memory cell by repeating the test process by adjusting the target waiting time. For example: set the target waiting time to T1, and if it is found that reading the target memory cell fails, then the data retention time of the target memory cell is less than T1; calculate the difference between T1 and the theoretical data retention time of the DRAM, determine the time adjustment step according to the difference, and set the target waiting time to T2 (T2 < T1) according to the time adjustment step. If it is found that reading the target memory cell is successful, then the data retention time of the target memory cell is greater than T2; calculate the difference between T2 and the theoretical data retention time of the DRAM, determine the time adjustment step according to the difference, and set the target waiting time to T3 (T2 < T3 < T1) according to the time adjustment step. If it is found that reading the target memory cell fails, then the data retention time of the memory cell is less than T3; calculate the difference between T3 and the theoretical data retention time of the DRAM, determine the time adjustment step according to the difference, and set the target waiting time to T4 (T2 < T4 < T3) according to the time adjustment step. If it is found that reading the target memory cell is successful, then the data retention time of the target memory cell is greater than T4; calculate the difference between T4 and the theoretical data retention time of the DRAM, determine the time adjustment step according to the difference, and set the target waiting time to T5 (T4 < T5 < T3) according to the time adjustment step. If it is found that reading the target memory cell fails, then the data retention time of the target memory cell is less than T5.
[0044] In one embodiment, the target memory cell includes a word line, a bit line, a reverse bit line, and a sense amplifier circuit. During the data reading process, the method further includes: Step S2013, control the word line of the target memory cell to be opened so that the target memory cell shares charge with the bit line.
[0045] In this embodiment, when the memory test device needs to read data from the target memory cell in the DRAM, it controls the word line of the target memory cell to be opened so that the capacitor of the target memory cell shares charge with the bit line. Specifically, please refer to Figure 5 , Figure 5 which is a schematic circuit diagram of a memory cell in the DRAM; where the memory cell includes a word line WL, a bit line BL, a reverse bit line / BL, and a sense amplifier circuit. The sense amplifier circuit includes four transistor devices Tn1, Tn2, Tp1, Tp2, and two potentials SAN(0) and SAP(1); when the word line WL is opened, the capacitor Ta of the memory cell starts to share charge (charge sharing) with the bit line BL.
[0046] Step S2014: After charge sharing is completed, if the inductive amplifier circuit amplifies the voltage of the bit line to the first voltage threshold and the voltage of the reverse bit line to the second voltage threshold, then the data reading result is determined to be successful.
[0047] In this embodiment, after charge sharing is completed, the memory testing device detects the voltage of the bit line and the voltage of the reverse bit line of the target memory cell. If the inductive amplifier circuit amplifies the voltage of the bit line to the first voltage threshold and the voltage of the reverse bit line to the second voltage threshold, the data reading result is determined to be successful.
[0048] It should be noted that the reference Figure 5 and Figure 6 After charge sharing is completed, the voltage on the bit line BL of the target memory cell is higher than the initial reference voltage V. REF Increased ΔV BL At this time, the potentials SAN and SAP of the inductive amplifier circuit are turned on, Tn2 in the inductive amplifier circuit is turned on, and the voltage on the inverting bit line / BL starts to rise from the reference voltage V. REF The voltage of the bit line BL is pulled down until Tp1 in the inductive amplifier circuit is turned on, the voltage of the bit line BL is pulled up, the gate voltage of Tn2 in the inductive amplifier circuit increases, and the voltage of the reverse bit line / BL is continuously pulled down. The gate voltage of Tp1 in the inductive amplifier circuit is also strengthened, and the voltage of the bit line BL is continuously pulled up. Finally, the inductive amplifier circuit amplifies the voltage of the reverse bit line / BL to the first voltage threshold SAN (0) and the bit line BL to the second voltage threshold SAP (1).
[0049] Step S2015: After charge sharing is completed, if the inductive amplifier circuit amplifies the voltage of the bit line to the second voltage threshold and the voltage of the reverse bit line to the first voltage threshold, then the data reading result is determined to be a reading failure.
[0050] In this embodiment, after charge sharing is completed, the memory testing device detects the voltage of the bit line and the voltage of the reverse bit line of the target memory cell. If the inductive amplifier circuit amplifies the voltage of the bit line to the second voltage threshold and the voltage of the reverse bit line to the first voltage threshold, the data read result is determined to be a read failure. It can be understood that if the inductive amplifier circuit amplifies the voltage of the reverse bit line / BL to the first voltage threshold SAN (0) and the bit line BL to the second voltage threshold SAP (1), the data read result is determined to be a read failure.
[0051] In one embodiment, there is a coupling capacitor between the bit line and the reverse bit line; if the voltage pull-down effect of the coupling capacitor and the target memory cell continues to occur, causing the voltage of the bit line to be less than or equal to the voltage of the reverse bit line, then the inductive amplifier circuit amplifies the voltage of the bit line to the second voltage threshold and amplifies the voltage of the reverse bit line to the first voltage threshold.
[0052] It should be noted that the reference Figure 5 , Figure 6 and Figure 7 There is a coupling capacitance Cbl between the bit line and the reverse bit line; after charge sharing is completed, the inductive amplifier circuit potentials SAN and SAP are turned on, Tn2 is turned on, and the voltage of the reverse bit line / BL of the target memory cell starts from the reference voltage V. REF The voltage is pulled down slightly due to the coupling capacitance Cbl between bit line BL and the reverse bit line / BL. Figure 6 The green box indicates time X. At this moment, in the DRAM, among the memory cells in the same row as the target memory cell, except for the target memory cell whose capacitance is stored as "1", the capacitances of the other memory cells are stored as "0". When the word line WL is opened, the capacitances of all memory cells in that row begin to share charge with their respective corresponding BL and are amplified by their respective inductive amplifier circuits. When the capacitance of other memory cells storing "0" is amplified, the potential of their upper plate (the other plate in the capacitor besides the lower plate) is pulled down to a lower potential. This causes the potential of the lower plate (the plate in the capacitor connected to the power supply Vplate) of the capacitors of all other memory cells storing "0" in that row to be momentarily pulled down. Consequently, the potential of the upper plate of the capacitor of the target memory cell storing "1" is also pulled down at that moment, thus pulling down the voltage of the bit line BL of the target memory cell storing "1". If the pull-down effect of Cbl and the capacitor is too large, that is, if the voltage pull-down effect of the coupling capacitor and the target memory cell continues to occur, the voltage of the bit line BL of the target memory cell will be less than or equal to the voltage of the reverse bit line / BL (e.g., ...). Figure 7 As shown), this will cause Tp1 and Tp2 of the inductive amplifier circuit to turn on simultaneously, and the degree of opening of Tp2 is greater than that of Tp1. At this time, the voltage of the target memory cell bit line BL and the reverse bit line / BL are pulled up, but the voltage of the reverse bit line / BL is pulled up faster, causing Tn1 of the inductive amplifier circuit to turn on, pulling down the voltage of bit line BL, causing Tp1 of the inductive amplifier circuit to gradually turn off, until finally Tn1 of the inductive amplifier circuit amplifies the voltage of bit line BL to SAN (0), and Tp2 of the inductive amplifier circuit amplifies the voltage of / BL to SAP (1), causing the read data to fail.
[0053] It is understandable that, in the DRAM, among the memory cells in the same row as the target memory cell, except for one target memory cell whose capacitor stores "1" and the other memory cells whose capacitors store "0", this creates a harsh environment for the stored data 1, simulating power supply noise. When the memory testing device reads data from the target memory cell after a long target waiting time, the voltage pull-down effect of the coupling capacitor and the target memory cell continues to occur, causing the coupling capacitor and the internal pull-down effect of the capacitor to be too large. The inductive amplifier circuit Tn1 amplifies the bit line BL to close to SAN (0), and the inductive amplifier circuit Tp2 amplifies / BL to close to SAP (1). At this time, the voltage of the bit line and the reverse bit line of the target memory cell of the memory testing device are opposite to the voltage of the bit line and the reverse bit line of the target memory cell when the data is successfully read. As a result, the data read is opposite to the stored data, causing the read data to be invalid.
[0054] Step S202: Based on the adjusted target waiting time, repeatedly execute the steps of writing to the target storage unit and reading from the target storage unit to continuously adjust the target waiting time.
[0055] In this embodiment, the memory testing device repeatedly executes the steps of writing to and reading from the target storage unit based on the adjusted target latency, in order to continuously adjust the target latency. It is understood that each time the target latency is adjusted, the target storage unit needs to be written to again, and after waiting for the adjusted target latency, data is read from the target storage unit to obtain the data read result. This cycle continues until the target latency meets the preset conditions.
[0056] Step S203: Until the target waiting time meets the preset conditions, the data retention time of the target storage unit is obtained.
[0057] In one embodiment, the step of obtaining the data retention time of the target storage unit until the target waiting time meets a preset condition includes: Step S2031: If the difference between the latest preset number of adjusted target waiting times is less than a preset threshold, then the target waiting time is determined to meet the preset conditions.
[0058] Step S2032: Determine the data retention time of the target storage unit based on a preset number of adjusted target waiting times.
[0059] In this embodiment, during the process of the memory test device continuously updating the target waiting time, the difference between the latest obtained preset number of adjusted target waiting times is calculated. If the difference is less than the preset threshold, it is determined that the target waiting time meets the preset conditions, and then based on the preset number of adjusted target waiting times, the data retention time of the target storage unit is determined.
[0060] Exemplarily, the memory test device can determine the data retention time of the target storage unit by adjusting the target waiting time and repeating the test process. For example: set the target waiting time to T1, and it is found that reading the target storage unit fails, then the data retention time of the target storage unit is less than T1; set the target waiting time to T2 (T2 < T1), and it is found that reading the target storage unit is not failed, then the data retention time of this target storage unit is greater than T2; set the target waiting time to T3 (T2 < T3 < T1), and it is found that reading the target storage unit fails, then the data retention time of this storage unit is less than T3; set the target waiting time to T4 (T2 < T4 < T3), and it is found that reading the target storage unit is not failed, then the data retention time of this target storage unit is greater than T4; set the target waiting time to T5 (T4 < T5 < T3), and it is found that reading the target storage unit fails, then the data retention time of this target storage unit is less than T5. The difference between the latest obtained 3 adjusted target waiting times T3, T4, and T5 is small enough to be less than the preset threshold (such as 0.5 ms, 0.1 s, etc., which can be set manually. The smaller the preset threshold, the more accurate the determined data retention time of the target storage unit). Any one of the times T3, T4, and T5 can be used as the data retention time of the target storage unit, or the intermediate time T4 can be used as the data retention time of the target storage unit.
[0061] The memory test device of this embodiment clears the capacitor charges in all storage units of the DRAM, writes data to the target storage unit, so that there is a storage unit storing the data "1" in the DRAM, constructs the harsh environment encountered by the DRAM during actual high-speed and high-density operation, then reads the data of the target storage unit, and adjusts the target waiting time based on the data reading result; based on the adjusted target waiting time, repeat the steps of writing data to the target storage unit and reading the data of the target storage unit to continuously adjust the target waiting time; until the target waiting time meets the preset conditions, and obtain the data retention time of the target storage unit. By simulating the harsh environment encountered by the DRAM during actual high-speed and high-density operation and adopting the gradually approaching ideal method to test the data retention time of the target storage unit, the accuracy of the determined data retention time of the target storage unit is improved, which in turn helps to improve the accuracy of the determined data retention time of the DRAM.
[0062] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the DRAM data retention time testing apparatus provided in this application. The DRAM data retention time testing apparatus includes: The write module 10 is used to write all the memory cells of the DRAM to the first state.
[0063] The first determining module 20 is used to sequentially take each of the memory cells of the DRAM as a target memory cell, write the target memory cell to a second state for each target memory cell, and read data from the target memory cell, and determine the data retention time of the target memory cell based on the data reading result.
[0064] The second determining module 30 is used to determine the data retention time of the DRAM based on the data retention time of all the target storage cells.
[0065] It is understood that the DRAM data retention time test apparatus of this embodiment corresponds to the DRAM data retention time test method of the above embodiment. The options in the above embodiment are also applicable to this embodiment, so they will not be described again here.
[0066] This application also provides a computer device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer device to perform the above-described method for testing DRAM data retention time by running the computer program.
[0067] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.
[0068] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving execution instructions.
[0069] This application also provides a computer storage medium for storing the computer program used in the aforementioned computer device. The computer storage medium can be a readable storage medium, a non-volatile storage medium, or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0070] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0071] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0072] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical methods of this application, in essence, or the part that contributes to the prior art, or a part of the technical methods, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.
[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A method for testing DRAM data retention time, characterized in that, The method includes: Write all memory cells of the DRAM to the first state; Each of the memory cells of the DRAM is sequentially used as a target memory cell. For each target memory cell, the target memory cell is written to a second state and data is read from the target memory cell. The data retention time of the target memory cell is determined based on the data reading result. The data retention time of the DRAM is determined based on the data retention time of all the target storage cells.
2. The method for testing DRAM data retention time according to claim 1, characterized in that, The steps of writing the target storage unit to the second state, reading data from the target storage unit, and determining the data retention time of the target storage unit based on the data reading result include: The target storage unit is written to the second state, and after waiting for the target waiting time, the target storage unit is read from the data, and the target waiting time is adjusted based on the data reading result. Based on the adjusted target waiting time, the steps of writing to the target storage unit and reading data from the target storage unit are repeated to continuously adjust the target waiting time; The data retention time of the target storage unit is obtained until the target waiting time meets the preset conditions.
3. The method for testing DRAM data retention time according to claim 2, characterized in that, The step of adjusting the target waiting time based on the data reading results includes: If the data reading result is successful, then increase the target waiting time; If the data reading result is a reading failure, then the target waiting time is reduced.
4. The method for testing DRAM data retention time according to claim 3, characterized in that, The method further includes: Based on the current target waiting time and the theoretical data retention time of the DRAM, determine the time adjustment step size; The target waiting time can be increased or decreased based on the time adjustment step size.
5. The method for testing DRAM data retention time according to claim 2, characterized in that, The step of obtaining the data retention time of the target storage unit until the target waiting time meets the preset conditions includes: If the difference between the latest preset number of adjusted target waiting times is less than a preset threshold, then the target waiting time is determined to meet the preset conditions. The data retention time of the target storage unit is determined based on a preset number of adjusted target waiting times.
6. The method for testing DRAM data retention time according to claim 1, characterized in that, The step of determining the data retention time of the DRAM based on the data retention time of all the target storage cells includes: Compare the data retention times of all the target storage units to determine the minimum data retention time; The minimum data retention time is determined as the data retention time of the DRAM.
7. A testing apparatus for DRAM data retention time, characterized in that, The DRAM data retention time testing device includes: The write module is used to write all memory cells of the DRAM to the first state; The first determining module is used to sequentially take each of the memory cells of the DRAM as a target memory cell, write the target memory cell to a second state for each target memory cell, and read data from the target memory cell, and determine the data retention time of the target memory cell based on the data reading result; The second determining module is used to determine the data retention time of the DRAM based on the data retention time of all the target storage cells.
8. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the DRAM data retention time test method according to any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on a processor, executes the method for testing the DRAM data retention time according to any one of claims 1-6.