An integrated phase gain and gain flatness adjustment circuit

Abstract

The application relates to the technical field of radio frequency integrated circuits, and particularly discloses an integrated phase gain and gain flatness adjusting circuit. The integrated phase gain and gain flatness adjusting circuit is configured as follows: when a process library of a target chip does not provide a logic device, the integrated phase gain and gain flatness adjusting circuit comprises a switch switching module and a function module; when the process library of the target chip provides the logic device, the integrated phase gain and gain flatness adjusting circuit comprises a level conversion module and a function switching module. The integrated phase gain and gain flatness adjusting circuit seamlessly integrates phase, gain and gain flatness adjusting functions into a single integrated circuit, realizes accurate, stable and detailed adjustment without external control signals, and can complete gain, phase and gain flatness compensation and adjustment in the chip without external control signals.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to an integrated phase gain and gain flatness adjustment circuit. Background Technology

[0002] In microwave radio frequency systems, precise control of signal amplitude (gain) and phase is a crucial function and a prerequisite for achieving cutting-edge applications such as high-performance communications, radar, navigation, and electronic warfare. It is widely used in phased array radar, satellite communications, 5G / 6G base stations, instrumentation, and other fields.

[0003] Traditional solutions primarily rely on external ceramic amplitude and phase modulation blocks, digital attenuator / phase shifter technology, or external phase shifter / attenuator / equalizer target chips. These traditional solutions have the following inherent drawbacks and limitations:

[0004] 1) Inability to integrate, large system size: Ceramic amplitude and phase modulators and external phase shift attenuators are usually independently packaged discrete devices. They need to be connected to amplifiers, mixers and other target chips that require amplitude and phase modulation through PCB traces, which occupies a lot of system board and space, making it difficult to achieve system miniaturization and weight reduction.

[0005] 2) Requires complex external control: These devices typically require external dedicated digital control circuits or TTL signals to provide precise control voltages or digital signals to set their attenuation and phase shift, which increases the complexity, power consumption and cost of system design.

[0006] 3) Performance accuracy is affected by external factors: Its adjustment accuracy is easily affected by the quality of external control signals, noise introduced by PCB wiring, power supply ripple, changes in ambient temperature, and the length, height, and even curvature of the bonding wire on the ceramic amplitude and phase modulation block, which leads to unstable system performance.

[0007] 4) Introduction of insertion loss and mismatch: In traditional technical solutions, due to the use of independent components, the soldering and connection of their input and output ports will introduce additional insertion loss and may cause impedance mismatch, affecting the performance of the entire link.

[0008] Therefore, there is an urgent need for a technical solution that can overcome the above-mentioned shortcomings and seamlessly integrate the phase, gain and gain flatness adjustment functions into a single integrated circuit to achieve precise, stable and fine-tuned adjustment without the need for external control signals. Summary of the Invention

[0009] Based on this, the purpose of this invention is to provide an integrated phase gain and gain flatness adjustment circuit. This invention can complete gain, phase and gain flatness compensation and adjustment within the target chip without the need for external control signals.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] This invention provides an integrated phase gain and gain flatness adjustment circuit, which is integrated inside a target chip; the integrated phase gain and gain flatness adjustment circuit is constructed as follows:

[0012] When the process library of the target chip does not provide logic devices, the integrated phase gain and gain flatness adjustment circuit includes a switch switching module and a functional module; the control terminal of the switch switching module is provided with a first pad, and when the first pad is connected to the ground pad of the target chip, the radio frequency signal passes directly; when the first pad is floating, the functional module is used to adjust the phase, gain or gain flatness of the radio frequency signal of the target chip.

[0013] When the target chip's process library provides logic devices, the integrated phase gain and gain flatness adjustment circuit includes a level conversion module and a function switching module. The control terminal of the level conversion module is provided with a second pad. When the second pad is connected to the ground pad of the target chip, VC is high and VCN is low in the two opposite output levels. When the second pad is floating, VC is low and VCN is high in the two opposite output levels. The function switching module is controlled by the level signal output by the level conversion module to provide a reference state path or a functional state path for the RF signal of the target chip. When providing a reference state path, no phase or amplitude adjustment is performed on the RF signal. When providing a functional state path, phase, gain, or gain flatness adjustment is performed on the RF signal.

[0014] As a further improvement to the above-described solution of the present invention, the switch switching module includes a signal input terminal, a signal output terminal, and a bias network; the radio frequency signal of the target chip is input from the signal input terminal, and output to the signal output terminal after passing through the bias network; the first pad serves as an external control interface for bonding with the ground pad of the target chip; the bias network is connected to the first pad and the functional module.

[0015] As a further improvement to the above-described solution of the present invention, the bias network includes a capacitor C1, a resistor R1, a pull-up resistor R2, a resistor R3, a switch S1, and a capacitor C2. One end of the capacitor C1 is connected to the signal input terminal and the signal output terminal, and the other end of the capacitor C1 is connected to the drain of the switch S1. One end of the resistor R1 is connected to the gate of the switch S1, and the other end of the resistor R1 is connected to the first pad. One end of the pull-up resistor R2 is connected to the power supply voltage of the target chip. One end of the capacitor C2 is connected to the source of the switch S1, and the other end of the capacitor C2 is connected to the functional module. The source of the switch S1 is also connected to the power supply voltage of the target chip through the resistor R3.

[0016] As a further improvement to the above-mentioned solution of the present invention, the functional module includes a phase adjustment function module, which includes a capacitor C3, one end of which is connected to a capacitor C2 and the other end of which is grounded.

[0017] As a further improvement to the above-mentioned solution of the present invention, the functional module includes an amplitude modulation function module, the amplitude modulation function module includes a resistor R4, one end of the resistor R4 is connected to the capacitor C2 and the other end is grounded.

[0018] As a further improvement to the above-mentioned solution of the present invention, the functional module gain equalization module includes a resistor R5, a capacitor C4 and an inductor L1. One end of the resistor R5 is connected to the capacitor C2 and the other end of the resistor R5 is connected to one end of the capacitor C4. The other end of the capacitor C4 is connected to one end of the inductor L1 and the other end of the inductor L1 is grounded.

[0019] As a further improvement to the above-described solution of the present invention, the level conversion module includes enhancement-mode field-effect transistors T1, T2, T3, T5, and T6, depletion-mode field-effect transistors T4 and T7, Schottky diodes D1, D2, D3, and D4, and resistors R6, R7, R9, R10, R11, R12, and R13.

[0020] Schottky diodes D1, D2, D3, and D4 are connected in series and then connected to the power supply voltage of the target chip. Each of the Schottky diodes D1, D2, D3, and D4 sequentially drops the power supply voltage, generating an intermediate voltage node Vhigh. The power supply voltage of the target chip is then connected to ground via resistors R7 and R6.

[0021] The second pad serves as an external control interface for bonding with the ground pad of the target chip. The second pad is connected to the gate of the enhancement-mode field-effect transistor T1. The gate of the enhancement-mode field-effect transistor T1 is also connected to the connection point of resistors R7 and R6. The source of the enhancement-mode field-effect transistor T1 is grounded, and the drain of the enhancement-mode field-effect transistor T1 is connected to resistor R9 and the gate of the enhancement-mode field-effect transistor T2. The other end of resistor R9 is connected to the intermediate voltage node Vhigh.

[0022] The source of enhancement-mode field-effect transistor T2 is grounded, the drain of enhancement-mode field-effect transistor T2 is connected to resistor R10 and the gate of enhancement-mode field-effect transistor T3, and the other end of resistor R10 is connected to the intermediate voltage node Vhigh;

[0023] The source of enhancement-mode MOSFET T3 is grounded, and the drain of enhancement-mode MOSFET T3 is connected to resistor R11. The other end of resistor R11 is connected to the source of depletion-mode MOSFET T4. The drain of depletion-mode MOSFET T4 is connected to the +5V power supply voltage of the target chip. The gate of depletion-mode MOSFET T4 is connected to the junction of resistor R11 and the drain of enhancement-mode MOSFET T3. The drain of enhancement-mode MOSFET T3 outputs a voltage level VC.

[0024] The gate of enhancement-mode field-effect transistor T5 is connected to the gate of enhancement-mode field-effect transistor T3, the source of enhancement-mode field-effect transistor T5 is grounded, the drain of enhancement-mode field-effect transistor T5 is connected to resistor R12 and the gate of enhancement-mode field-effect transistor T6, and the other end of resistor R12 is connected to the intermediate voltage node Vhigh.

[0025] The source of enhancement-mode MOSFET T6 is grounded, the drain of enhancement-mode MOSFET T6 is connected to resistor R13, the other end of resistor R13 is connected to the source of depletion-mode MOSFET T7, the drain of depletion-mode MOSFET T7 is connected to the +5V power supply voltage of the target chip, and the gate of depletion-mode MOSFET T7 is connected to the junction of resistor R13 and the drain of enhancement-mode MOSFET T6; the drain of enhancement-mode MOSFET T6 outputs the voltage level VCN.

[0026] As a further improvement to the above-described solution of the present invention, the function switching module includes a first single-pole double-throw switch, a second single-pole double-throw switch, a reference state circuit, and a functional state circuit; the first single-pole double-throw switch and the second single-pole double-throw switch are controlled by the level output of the level conversion module to switch between the reference state circuit and the functional state circuit.

[0027] As a further improvement to the above-described solution of the present invention, the functional circuit is a phase-shifting circuit, an attenuation circuit, or a gain equalization circuit.

[0028] As a further improvement to the above-described solution of the present invention, the target chip includes, but is not limited to, an amplifier chip, a multi-functional chip, or a transceiver module chip.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The integrated phase gain and gain flatness adjustment circuit based on MMIC provided by this invention seamlessly integrates phase, gain and gain flatness adjustment functions into a single integrated circuit, achieving precise, stable and fine-tuned adjustment without external control signals. It can complete gain, phase and gain flatness compensation and adjustment within the chip without the need for external control signals.

[0031] This invention requires no external active control level; the circuit's operating state is selected solely through a one-time bonding process. This approach not only eliminates complex external control circuitry and dedicated chip pins, significantly saving chip area, but also greatly improves system integration and design convenience. The circuit structure of this invention is simple and compact, and can be widely integrated as a standard functional unit into various MMIC circuits such as amplifiers and multi-functional chips. It not only supports single-function adjustment but also enables multi-step adjustable functions through cascading multiple circuits. The pads on the control end are only used for bonding and selecting the level, without affecting the RF path performance, thus enabling high-precision amplitude and phase adjustment. Furthermore, the control state is fixed after chip packaging, unaffected by external noise and temperature drift, exhibiting excellent long-term stability. Attached Figure Description

[0032] Figure 1 A circuit diagram of a switch switching module provided for an example of the present invention;

[0033] Figure 2 Circuit diagrams of functional modules provided for embodiments of the present invention;

[0034] Figure 3 A circuit diagram of a level conversion module provided for an example of the present invention;

[0035] Figure 4 A circuit diagram of a function switching module provided for an example of the present invention;

[0036] Figure 5 The phase adjustment curve is obtained by simulating the phase adjustment of a power amplifier using the integrated phase gain and gain flatness adjustment circuit provided in this invention.

[0037] Figure 6 The gain adjustment curve is obtained by simulating the gain adjustment of a power amplifier using the integrated phase gain and gain flatness adjustment circuit provided in this invention.

[0038] Figure 7The gain flatness adjustment curve is obtained by simulating the gain flatness adjustment of a power amplifier using the integrated phase gain and gain flatness adjustment circuit provided in this invention example. Detailed Implementation

[0039] To facilitate understanding of the present invention, a more comprehensive description will be provided below with reference to specific examples. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough and complete understanding of the disclosure of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0041] This example proposes an integrated phase gain and gain flatness adjustment circuit based on MMIC. The circuit structure of this example operates in the DC to millimeter wave band and can be integrated into the front end of amplifier chips, multifunction chips, or transceiver module chips. Depending on whether the target chip's process library provides logic devices, there are two implementation states. Neither requires an external control level; the functional adjustment can be completed using only the +5V / +3.3V power supply voltage provided by the active chip such as the amplifier chip or multifunction chip.

[0042] In the first implementation, for process libraries without logic dies (i.e., where the target chip's process library does not provide logic devices), the integrated phase gain and gain flatness adjustment circuit includes a switch module and a functional module. The control terminal of the switch module is led out through a first pad. The on / off state of the switch module is determined by whether the first pad is bonded to the ground pad on the target chip. When the first pad is bonded to the ground pad on the target chip, the RF signal bypasses (passes through) the functional module; when the first pad is floating or not bonded, the switch module connects the target chip's RF path to the functional module. This bonding method enables small-range phase shift, minute gain adjustment, and gain flatness compensation.

[0043] In the second implementation, for the process library providing logic devices such as enhancement-mode (E-mode) or depletion-mode (D-mode) field-effect transistors (FETs), i.e., the process library of the target chip, the integrated phase gain and gain flatness adjustment circuit includes a level shifting module and a function switching module. The control terminal of the level shifting module is brought out through a second pad. The logic high or low level output by the level shifting module is switched between high and low levels by whether the second pad is bonded to the ground pad on the chip. The function switching module is controlled by the logic level signal output by the level shifting module, providing a reference state path or a functional state path for the chip's RF signal. When providing a reference state path, no phase or amplitude adjustment is performed on the RF signal; when providing a functional state path, phase, gain, and / or gain flatness adjustment is performed on the RF signal.

[0044] like Figure 1 As shown, the switch switching module in this example includes a first pad, a signal input terminal, a signal output terminal, and a bias network. The RF signal from the target chip is input from the signal input terminal RFin, and output to the signal output terminal RFout after passing through the bias network. The first pad serves as an external control interface for bonding with the ground pad of the target chip. The bias network is connected to the first pad and the functional module. The bias network includes a capacitor C1, a resistor R1, a pull-up resistor R2, a resistor R3, a switch S1, and a capacitor C2. One end of capacitor C1 is connected to the signal input terminal and the signal output terminal, and the other end of capacitor C1 is connected to the drain of switch S1. One end of resistor R1 is connected to the gate of switch S1, and the other end is connected to the first pad and one end of pull-up resistor R2. The other end of pull-up resistor R2 is connected to the supply voltage of the target chip (the supply voltage of the target chip can be +5V or +3.3V; this article uses +5V as an example). One end of capacitor C2 is connected to the source of switch S1, and the other end is connected to the functional module. The source of switch S1 is also connected to the +5V supply voltage of the target chip through resistor R3. Resistor R1 limits current; capacitors C1 and C2 block DC current to prevent leakage into the RF signal path. The source of switch S1 is connected to +5V through the large resistor R3. When the first pad is floating, pull-up resistor R2 pulls the gate voltage of switch S1 up to +5V. At this time, the gate-source voltage is greater than the turn-on voltage, switch S1 is turned on, and the RF signal is loaded to the functional module, thereby achieving the desired phase modulation, amplitude modulation, or gain equalization functions. When the first pad is bonded to the ground pad of the target chip, the gate-source voltage is -5V, the switch S1 is turned off, and the functional module is in a disconnected or bypassed state. The radio frequency signal is not affected by the functional module, and the circuit behaves as a reference (pass-through) state.

[0045] Combination Figure 2This example provides three basic functional circuits for selection: the first is a phase modulation module with a parallel capacitor C3 connected to ground, where one end of capacitor C3 is connected to capacitor C2 and the other end is grounded; the second is an amplitude modulation module with a parallel resistor R4 connected to ground, where one end of resistor R4 is connected to capacitor C2 and the other end is grounded; the third is a gain equalization module using a network-to-ground structure composed of a parallel resistor R5, capacitor C4, and inductor L1, where one end of resistor R5 is connected to capacitor C2 and the other end is connected to one end of capacitor C4, the other end of capacitor C4 is connected to one end of inductor L1, and the other end of inductor L1 is grounded. The appropriate function of the module can be selected according to actual application requirements, and different adjustment values ​​can be set by adjusting the component parameters.

[0046] Combination Figure 3The level conversion module in this example includes a second pad, enhancement-mode MOSFETs T1, T2, T3, T5, and T6, depletion-mode MOSFETs T4 and T7, Schottky diodes D1, D2, D3, and D4, and resistors R6, R7, R9, R10, R11, R12, and R13. Schottky diodes D1, D2, D3, and D4 are connected in series to the +5V supply voltage of the target chip. These diodes sequentially reduce the +5V voltage, generating an intermediate voltage node Vhigh. The +5V supply voltage of the target chip is then connected to ground via resistors R7 and R6. The second pad serves as an external control interface for bonding with the ground pad of the target chip. The second pad is connected to the gate of enhancement-mode MOSFET T1. The gate of enhancement-mode MOSFET T1 is also connected to the junction of resistors R7 and R6. The source of enhancement-mode MOSFET T1 is grounded, and its drain is connected to resistor R9 and the gate of enhancement-mode MOSFET T2. The other end of resistor R9 is connected to the intermediate voltage node Vhigh. The source of enhancement-mode MOSFET T2 is grounded, and its drain is connected to resistor R10 and the gate of enhancement-mode MOSFET T3. The other end of resistor R10 is connected to the intermediate voltage node Vhigh. The source of enhancement-mode MOSFET T3 is grounded. The drain of T3 is connected to resistor R11, the other end of which is connected to the source of depletion-mode MOSFET T4. The drain of T4 is connected to the +5V supply voltage of the target chip. The gate of T4 is connected to the junction of resistor R11 and the drain of T3. The drain of T3 outputs a voltage level VC. The gate of enhancement-mode MOSFET T5 is connected to the gate of T3. The source of T5 is grounded. The drain of T5 is connected to resistor R12 and the gate of enhancement-mode MOSFET T6. The other end of resistor R12 is connected to the intermediate voltage node Vhigh. The source of enhancement-mode MOSFET T6 is grounded, and the drain of enhancement-mode MOSFET T6 is connected to resistor R13. The other end of resistor R13 is connected to the source of depletion-mode MOSFET T7. The gate of depletion-mode MOSFET T7 is connected to the +5V power supply voltage of the target chip. The drain of depletion-mode MOSFET T7 is connected to the junction of resistor R13 and the drain of enhancement-mode MOSFET T6. The drain output level of enhancement-mode MOSFET T6 is VCN.

[0047] During circuit operation, the +5V voltage is first reduced by four Schottky diodes (D1, D2, D3, and D4) to generate an intermediate voltage node Vhigh suitable for driving subsequent circuits. External function selection is achieved by whether the second pad is bonded to the ground pad: when the second pad is floating, +5V is grounded through voltage divider resistors R6 and R7, outputting a high level that turns on transistor T1. This high level is then inverted by T1 and outputs a low level to transistor T2. When the second pad is bonded to the target chip's ground pad, T1 is turned off, and the low level is inverted by T1 and outputs a high level to T2. Subsequent signals are output as two inverted levels VC and VCN via two simple inverters (transistor T2 and resistor R10, transistor T5 and resistor R12 respectively) and two DCFL (directly coupled field-effect transistor logic) inverter circuits (transistors T3, T4 and resistor R11, transistors T6, T7 and resistor R13 respectively). This differential output signal is sent to the function switching module to complete the path selection function.

[0048] Combination Figure 4 The function switching module in this example includes a first single-pole double-throw (SPD) switch, a second SPD switch, a reference state circuit, and a functional state circuit. The first and second SPD switches are controlled by two levels, VC and VCN, output from the level conversion module. When the first and second SPD switches are controlled to switch to the reference state path, this path does not adjust the phase or amplitude of the signal, providing a low-insertion-loss reference path. When the first and second SPD switches are controlled to switch to the functional state path, the RF signal passes through a specific functional circuit. This path integrates circuits capable of specific signal adjustment, such as a phase-shifting circuit using a bridge-T, high-low-pass, or load-line structure; an attenuation circuit using a π-type, T-type, or parallel resistor-to-ground structure; or an equalization circuit using a parallel RCL resonant network structure to compensate for gain variations with frequency.

[0049] The phase gain and gain flatness adjustment circuit described in this example was used to simulate the phase, gain, and gain flatness adjustment of a power amplifier with an operating frequency band of 2GHz-20GHz. The results are as follows: Figure 5-7 As shown. Figure 5 As shown, the functional module adjusts the phase of the signal, resulting in a 20° phase lead; as Figure 6 As shown, the functional module adjusts the signal gain, resulting in a 1dB gain attenuation; as Figure 7 As shown, the functional module adjusts the gain flatness of the signal, making the curve of gain with negative frequency slope become horizontal.

[0050] The technical features described in the above examples can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above examples are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The examples described above are merely illustrative of several embodiments of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An integrated phase gain and gain flatness adjustment circuit, characterized in that, It is integrated inside the target chip; the integrated phase gain and gain flatness adjustment circuit is constructed as follows: When the process library of the target chip does not provide logic devices, the integrated phase gain and gain flatness adjustment circuit includes a switch switching module and a functional module; the control terminal of the switch switching module is provided with a first pad and when the first pad is floating, the functional module is used to adjust the phase, gain or gain flatness of the RF signal of the target chip. When the target chip's process library provides logic devices, the integrated phase gain and gain flatness adjustment circuit includes a level conversion module and a function switching module. The control terminal of the level conversion module is provided with a second pad. When the second pad is connected to the ground pad of the target chip, VC is high and VCN is low in the two opposite output levels. When the second pad is floating, VC is low and VCN is high in the two opposite output levels. The function switching module is controlled by the level signal output by the level conversion module to provide a reference state path or a functional state path for the RF signal of the target chip. When a reference state path is provided, the phase and amplitude of the radio frequency signal are not adjusted; when a functional state path is provided, the phase, gain, or gain flatness of the radio frequency signal is adjusted.

2. The integrated phase gain and gain flatness adjustment circuit according to claim 1, characterized in that, The switching module includes a signal input terminal, a signal output terminal, and a bias network; the radio frequency signal of the target chip is input from the signal input terminal, passes through the bias network, and is output to the signal output terminal; the first pad serves as an external control interface for bonding with the ground pad of the target chip; the bias network is connected to the first pad and the functional module.

3. The integrated phase gain and gain flatness adjustment circuit according to claim 2, characterized in that, The bias network includes capacitor C1, resistor R1, pull-up resistor R2, resistor R3, switch S1, and capacitor C2. One end of capacitor C1 is connected to the signal input terminal and the signal output terminal, and the other end of capacitor C1 is connected to the drain of switch S1. One end of resistor R1 is connected to the gate of switch S1, and the other end is connected to the first pad. One end of pull-up resistor R2 is connected to the power supply voltage of the target chip. One end of capacitor C2 is connected to the source of switch S1, and the other end is connected to the functional module. The source of switch S1 is also connected to the power supply voltage of the target chip through resistor R3.

4. The integrated phase gain and gain flatness adjustment circuit according to claim 3, characterized in that, The functional module includes a phase adjustment function module, which includes a capacitor C3, one end of which is connected to a capacitor C2 and the other end is grounded.

5. The integrated phase gain and gain flatness adjustment circuit according to claim 3, characterized in that, The functional module includes an amplitude modulation module, which includes a resistor R4, one end of which is connected to a capacitor C2 and the other end is grounded.

6. The integrated phase gain and gain flatness adjustment circuit according to claim 3, characterized in that, The gain equalization function module includes a resistor R5, a capacitor C4, and an inductor L1. One end of the resistor R5 is connected to the capacitor C2 and the other end is connected to one end of the capacitor C4. The other end of the capacitor C4 is connected to one end of the inductor L1, and the other end of the inductor L1 is grounded.

7. The integrated phase gain and gain flatness adjustment circuit according to claim 1, characterized in that, The level conversion module includes enhancement-mode field-effect transistors T1, T2, T3, T5, and T6; depletion-mode field-effect transistors T4 and T7; Schottky diodes D1, D2, D3, and D4; and resistors R6, R7, R9, R10, R11, R12, and R13. Schottky diodes D1, D2, D3, and D4 are connected in series and then connected to the power supply voltage of the target chip. Each of the Schottky diodes D1, D2, D3, and D4 sequentially drops the power supply voltage, generating an intermediate voltage node Vhigh. The power supply voltage of the target chip is then connected to ground via resistors R7 and R6. The second pad serves as an external control interface for bonding with the ground pad of the target chip, and the second pad is connected to the gate of the enhancement-mode field-effect transistor T1. The gate of enhancement-mode field-effect transistor T1 is connected to the connection point of resistors R7 and R6; the source of enhancement-mode field-effect transistor T1 is grounded; the drain of enhancement-mode field-effect transistor T1 is connected to resistor R9 and the gate of enhancement-mode field-effect transistor T2; the other end of resistor R9 is connected to the intermediate voltage node Vhigh. The source of enhancement-mode field-effect transistor T2 is grounded, the drain of enhancement-mode field-effect transistor T2 is connected to resistor R10 and the gate of enhancement-mode field-effect transistor T3, and the other end of resistor R10 is connected to the intermediate voltage node Vhigh; The source of enhancement-mode MOSFET T3 is grounded, and its drain is connected to resistor R11. The other end of resistor R11 is connected to the source of depletion-mode MOSFET T4. The drain of depletion-mode MOSFET T4 is connected to the power supply voltage of the target chip, and its gate is connected to the junction of resistor R11 and the drain of enhancement-mode MOSFET T3. The drain output level VC of the field-effect transistor T3; The gate of enhancement-mode field-effect transistor T5 is connected to the gate of enhancement-mode field-effect transistor T3, the source of enhancement-mode field-effect transistor T5 is grounded, the drain of enhancement-mode field-effect transistor T5 is connected to resistor R12 and the gate of enhancement-mode field-effect transistor T6, and the other end of resistor R12 is connected to the intermediate voltage node Vhigh. The source of enhancement-mode MOSFET T6 is grounded, the drain of enhancement-mode MOSFET T6 is connected to resistor R13, the other end of resistor R13 is connected to the source of depletion-mode MOSFET T7, the drain of depletion-mode MOSFET T7 is connected to the power supply voltage of the target chip, and the gate of depletion-mode MOSFET T7 is connected to the junction of resistor R13 and the drain of enhancement-mode MOSFET T6; the drain of enhancement-mode MOSFET T6 outputs a voltage level VCN.

8. The integrated phase gain and gain flatness adjustment circuit according to claim 1, characterized in that, The function switching module includes a first single-pole double-throw switch, a second single-pole double-throw switch, a reference state circuit, and a functional state circuit; the first single-pole double-throw switch and the second single-pole double-throw switch are controlled by the level output of the level conversion module to switch between the reference state circuit and the functional state circuit.

9. The integrated phase gain and gain flatness adjustment circuit according to claim 8, characterized in that, The functional circuit is a phase-shifting circuit, an attenuation circuit, or a gain equalization circuit.

10. The integrated phase gain and gain flatness adjustment circuit according to claim 1, characterized in that, The target chip is an amplifier chip, a multi-functional chip, or a transceiver module chip.

Images