Three-node flip-tolerant self-restoring latch based on three-input two-output c-cell

Abstract

The application relates to a three-node flip-tolerant self-recovery latch based on a three-input two-output C unit, the latch adopts a plurality of three-input two-output C units to construct a latch circuit, when the input and output of a certain TDC are flipped at the same time, the downstream cascaded TDC maintains the original output state due to the inconsistent input signals, so that the propagation of the error signal to the adjacent node is blocked. Through the synergistic effect of the redundant feedback path, the TDC, the CG-TDC and the three-input C unit, the disturbed node can be gradually recovered to the original logic state through multi-stage feedback, complete self-recovery of the three-node flip is realized, and the static and dynamic power consumption is kept low.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a three-node flip-tolerant self-recovery latch based on a three-input dual-output C-cell. Background Technology

[0002] As the feature size of semiconductor devices continues to shrink, the power supply voltage, node capacitance, and critical charge decrease accordingly, leading to a significant increase in the sensitivity of circuit nodes to radiation-induced soft errors. When high-energy particles pass through the sensitive regions of integrated circuits, they generate a large number of electron-hole pairs in the semiconductor material. These electron-hole pairs are collected in the depletion region and form transient current pulses; this phenomenon is called a single-event transient (SET). If this SET propagates to a digital storage circuit and is latched, it will cause unexpected changes to the stored data; this effect is called a single-event upset (SEU).

[0003] As transistor feature sizes shrink further and integrated circuit density increases, a single particle bombardment can simultaneously affect multiple spatially adjacent circuit nodes, triggering a multiple node upset (MNU). The scenario where two adjacent nodes simultaneously undergo state reversal is called a dual node upset (DNU). The mechanism behind this phenomenon is that the charge generated by the particle bombardment diffuses spatially. Besides being collected at the bombardment center, some charge diffuses to neighboring nodes and is also collected, resulting in charge distribution across multiple nodes. Correspondingly, the amount of charge collected by a single node may be below its reversal threshold, but under specific geometric layouts and process conditions, adjacent nodes can still accumulate sufficient charge simultaneously, leading to a reversal. At current advanced process nodes, dual node upset is one of the most common scenarios in multi-node upsets. To address this issue, researchers have begun studying anti-dual node upset latches. These latches can self-recover when any two nodes are disturbed through a feedback loop. Their structure is as follows: Figure 1 As shown in the diagram, while this design can resist two-node flips, it cannot solve the problem of data changes when three nodes flip simultaneously. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional methods, this invention proposes a three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell is provided, comprising: The data input and sampling control module is used to write the input data D into nodes N3, N5, N7, N9, N11 and Q during the sampling phase, and to isolate the input data D during the latching phase.

[0006] The clock input terminal is used to receive clock signals and transmit them to the data input and sampling control module and the interlock feedback loop.

[0007] The multi-level interlocked feedback loop includes three three-input dual-output C units TDC1, TDC3, and TDC5, and three three-input dual-output clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6, connected sequentially in the order TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6 to form the feedback loop. The logic states of nodes N3, N5, N7, N9, N11, and Q drive the inputs of the three TDC units. Each three-input dual-output C unit TDC includes three PMOS transistors PM1 to PM3 and three N... MOS transistors NM1 to NM3; the gates of NM2 and PM1 are both connected to the first input terminal of TDC; the gates of NM1 and PM2 are both connected to the second input terminal of TDC; the gates of NM3 and PM3 are both connected to the third input terminal of TDC; the source of PM1 is connected to VDD, the drain of PM1 is connected to the source of PM2 and PM3, the drains of PM2 and NM1 are both connected to the first output terminal of TDC, the source of NM1 and the drain of NM2 are both connected to the source of NM3, the source of NM2 is grounded; the drains of NM3 and PM3 are both connected to the second output terminal of TDC.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell utilizes multiple three-input dual-output C-cells to construct the latch circuit. When the input and output of a certain TDC flip simultaneously, the downstream cascaded TDCs maintain their original output state due to the inconsistent input signals, thereby blocking the propagation of erroneous signals to neighboring nodes. Through redundant feedback paths and the synergistic effect of the TDC, CG-TDC, and three-input C-cells, the disturbed node can gradually recover to its original logic state through multi-level feedback, achieving complete self-recovery of the three-node flip-by-node while maintaining low static and dynamic power consumption. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is the most advanced DNU-resistant flip-flop latch available in the technology. Figure 2 This is a schematic diagram of a three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell in one embodiment. Figure 3 This is a schematic diagram of a three-input dual-output C-unit in one embodiment, wherein... Figure 3 (a) is the schematic diagram of a three-input dual-output C-unit TDC. Figure 3 (b) is the three-input dual-output clock-gated C unit CG-TDC. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0013] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0014] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0015] In one embodiment, such as Figure 2 As shown, a three-node flip-flop tolerant self-recovering latch based on a three-input dual-output C-cell is provided, comprising: The data input and sampling control module is used to write the input data D into nodes N3, N5, N7, N9, N11 and Q during the sampling phase, and to isolate the input data D during the latching phase.

[0016] The clock input terminal is used to receive clock signals and transmit them to the data input and sampling control module and the interlock feedback loop.

[0017] The multi-level interlocked feedback loop includes three three-input dual-output C units TDC1, TDC3, and TDC5, and three three-input dual-output clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6, connected sequentially in the order TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6 to form the feedback loop. The logic states of nodes N3, N5, N7, N9, N11, and Q drive the inputs of the three TDC units. Each three-input dual-output C unit TDC includes three PMOS transistors PM1 to PM3 and three N... MOS transistors NM1 to NM3; the gates of NM2 and PM1 are both connected to the first input terminal of TDC; the gates of NM1 and PM2 are both connected to the second input terminal of TDC; the gates of NM3 and PM3 are both connected to the third input terminal of TDC; the source of PM1 is connected to VDD, the drain of PM1 is connected to the source of PM2 and PM3, the drains of PM2 and NM1 are both connected to the first output terminal of TDC, the source of NM1 and the drain of NM2 are both connected to the source of NM3, the source of NM2 is grounded; the drains of NM3 and PM3 are both connected to the second output terminal of TDC.

[0018] Specifically, to achieve the tolerance and self-recovery function of Triple Node Upset (TNU), this application uses multiple Triple-Input Dual-Output C-elements (TDC) to construct the latch circuit.

[0019] Figure 2The structural principle of a three-node toggle-tolerant self-recovery latch based on a three-input dual-output C-element is presented. This three-node toggle-tolerant self-recovery latch includes six transmission gates (TG), three three-input dual-output C-elements (TCD), and three clock-gated three-input dual-output C-elements (CG-TDC). The circuit contains twelve nodes N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, and Q. The clock input receives the clock signal CLK and its inverted signal NCLK. In transparent mode, the transmission gates are turned on, transmitting the input signal D to nodes Q, N3, N5, N7, N9, and N11, thereby driving the input of the TDC in the feedback loop to maintain the correct logic state. Compared to... Figure 1 In the existing structure shown, this application replaces some C units with TDC and CG-TDC. When the input and output of a certain TDC flip simultaneously, the downstream cascaded TDC maintains its original output state due to the input inconsistency, thereby blocking the propagation of erroneous signals to neighboring nodes. Because the feedback loop employs a multi-layered redundancy design, when any three nodes flip simultaneously, at least one complete feedback path is available for state recovery, enabling the latch to tolerate three-node flips. Under normal operating conditions without radiated interference, the signal is directly transmitted to the output node Q via the transmission gate, exhibiting low propagation delay and dynamic power consumption. The multi-level interlocking structure of the feedback loop enhances the blocking capability against node flips, enabling the circuit to have self-recovery functionality in radiated environments while maintaining low static and dynamic power consumption.

[0020] Compared to Figure 1 The anti-dual-node flip-flop latch shown in this invention uses TDC and CG-TDC to replace some of the C units in the original structure. When the input and output of a certain TDC flip-flop simultaneously, the downstream cascaded TDC maintains its original output state due to the inconsistent input signals, thereby blocking the propagation of the error signal to neighboring nodes. Taking a DNU occurring between node pair (N1, A) or (N2, B) as an example: Figure 1 In the original structure, the output node N2 of CE1 or the output node N3 of CE2 will generate transient disturbances; however, in the structure of this invention, no DNU event will cause any additional node state changes.

[0021] Compared to Figure 1 The illustrated anti-two-node flip-flop latch of this invention has three-node flip-flop tolerance capability. Taking a TNU (Turning Null-Down) event occurring in node pairs (N1, N3, N5) or (N1, A, B) as an example: Figure 1In the structure, the above-mentioned flip will cause all nodes to change their states and become unrecoverable; however, in this invention, through the redundant feedback path and the synergistic effect of TDC and CG-TDC, the disturbed nodes can be gradually restored to their original logical states through multi-level feedback, achieving complete self-recovery of the three-node flip.

[0022] The aforementioned three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell utilizes multiple three-input dual-output C-cells to construct the latch circuit. When the input and output of a certain TDC flip simultaneously, the downstream cascaded TDCs maintain their original output state due to the inconsistent input signals, thereby blocking the propagation of erroneous signals to neighboring nodes. Through redundant feedback paths and the synergistic effect of the TDC, CG-TDC, and three-input C-cells, the disturbed node can gradually recover to its original logic state through multi-level feedback, achieving complete self-recovery of the three-node flip-by-node while maintaining low static and dynamic power consumption.

[0023] In one embodiment, the interlocked feedback loop is configured in the order of TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6. The two outputs of TDC1 are connected to nodes N6 and N12, respectively; the two outputs of CG-TDC2 are connected to nodes Q and N3, respectively; the two outputs of TDC3 are connected to nodes N2 and N4, respectively; the two outputs of CG-TDC4 are connected to nodes N7 and N9, respectively; the two outputs of TDC5 are connected to nodes N10 and N8, respectively; and the two outputs of CG-TDC6 are connected to nodes N11 and N5, respectively. The third input of TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6 is connected to nodes N9, N10, N5, N6, Q, and N2, respectively.

[0024] In a multi-level interlocked feedback loop, the first and second output terminals of the preceding unit are connected to the two first and second input terminals of the following unit, respectively.

[0025] The enable pins of the clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6 are connected to the clock input pins.

[0026] Specifically, such as Figure 2 As shown, the connections in the multi-level interlocked feedback loop are as follows: the first output terminal of TDC1 and the first input terminal of CG-TDC2 are both connected to node N6, the second output terminal of TDC1 and the second input terminal of CG-TDC2 are both connected to node N12, and the third input terminal of TDC1 is connected to node N9.

[0027] The first output terminal of CG-TDC2 and the first input terminal of TDC3 are both connected to node N3. The second output terminal of CG-TDC2 and the second input terminal of TDC3 are both connected to output node Q. The third input terminal of CG-TDC2 is connected to node N10.

[0028] The first output terminal of TDC3 and the first input terminal of CG-TDC4 are both connected to node N2. The second output terminal of TDC3 and the second input terminal of CG-TDC4 are both connected to node N4. The third input terminal of TDC3 is connected to node N5.

[0029] The first output terminal of CG-TDC4 and the first input terminal of TDC5 are both connected to node N9, the second output terminal of CG-TDC4 and the second input terminal of TDC5 are both connected to node N7, and the third input terminal of CG-TDC4 is connected to node N6.

[0030] The first output of TDC5 and the first input of CG-TDC6 are both connected to node N10. The second output of TDC5 and the second input of CG-TDC6 are both connected to node N8. The third input of TDC5 is connected to node Q.

[0031] The first output terminal of CG-TDC6 and the first input terminal of TDC1 are both connected to node N5. The second output terminal of CG-TDC6 and the second input terminal of TDC1 are both connected to node N11. The third input terminal of CG-TDC6 is connected to node N2.

[0032] In one embodiment, the data input and sampling control module includes six transmission gates TG1 to TG6; each transmission gate includes an NMOS transistor and a PMOS transistor, with the drain of the NMOS transistor and the source of the PMOS transistor connected together as the input terminal of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor connected together as the output terminal of the transmission gate.

[0033] The clock input is connected to the gate of the NMOS transistors of transmission gates TG1 to TG6, and the clock input is connected to the gate of the PMOS transistors of transmission gates TG1 to TG6 through an inverter; the inputs of TG1, TG2, and TG3 are all connected to the data input; the outputs of transmission gates TG1 to TG6 are connected to nodes Q, N3, N5, N7, N9, and N11, respectively.

[0034] In one embodiment, when the clock signal CLK=1, the latch is in transparent operating mode; transmission gates TG1 to TG6 are turned on, and the input data D is transmitted through the transmission gates to nodes Q, N3, N5, N7, N9 and N11.

[0035] When D=0, the logical states of nodes Q, N3, N5, N7, N9 and N11 are 0, and the logical states of nodes N2, N4, N6, N8, N10 and N12 are 1; when D=1, the states of each node are inverted.

[0036] Clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6 are enabled, and multi-level interlocking feedback loops are activated to maintain the data state and perform error detection and recovery functions.

[0037] Specifically, the latch has two operating modes: transparent operating mode and hold operating mode. When CLK=1, the latch operates in transparent operating mode, and when CLK=0, the latch operates in hold operating mode.

[0038] In transparent mode, all six transmission gates are turned on, and the input signal D drives nodes Q, N3, N5, N7, N9, and N11 respectively through the transmission gates. When D=0, the logic state of nodes Q, N3, N5, N7, N9, N11, and nodes N2, N4, N6, N8, N10, and N12 is 1; when D=1, the state of each node is inverted. In this mode, the logic state of all nodes is consistent with the input signal D. In hold mode (CLK=0), the transmission gates are turned off, and the path between nodes N2, N4, and Q and the input D is cut off. At this time, each TDC and CG-TDC is in the working state, forming a ring feedback structure. The two outputs of each TDC and CG-TDC are connected to the two inputs of the next level unit, forming a multi-level interlocked feedback loop, which enables the circuit to recover to the original logic state through feedback after the node state is disturbed.

[0039] In one embodiment, when the clock signal CLK=0, the latch operates in hold mode, the transmission gates TG1 to TG6 are turned off, and the paths between nodes Q, N3, N5, N7, N9 and N11 and the input signal D are cut off; at this time, the three three-input dual-output C units and the three three-input dual-output clock-gated C units are all in working state, forming a ring feedback structure.

[0040] Specifically, in hold mode (CLK=0), the circuit contains twelve sensitive nodes: Q and N2-N12. When a dual-node flip (DNU) occurs, Figure 2 The structure shown is a three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell. Figure 1 The structure shown has the following differences compared to the previous one: it adopts... Figure 3 TDC and shown in (a) Figure 3 The CG-TDC replacement shown in (b) Figure 1In some C units, when the input and output of a certain TDC simultaneously flip, its downstream cascaded TDCs maintain their original output state due to the inconsistent input signals, thereby blocking the propagation of error signals to neighboring nodes. In contrast, Figure 1 When node pair (N1, A) is flipped in the structure, C unit CE1 may output an error signal and affect downstream nodes.

[0041] In one embodiment, the three-input dual-output clock-gated C unit includes four PMOS transistors PM7 to PM10 and four NMOS transistors NM7 to NM10.

[0042] The source of PM7 is connected to VDD, the gate of PM7 receives the clock signal CLK, the drain of PM7 is connected to the source of PM8, the gates of PM8 and NM9 are both connected to the second input of the three-input dual-output clock gate C unit, the drain of PM8 and the source of PM9 are both connected to the source of PM10, the gates of PM9 and NM7 are both connected to the first input of the three-input dual-output clock gate C unit, and the drains of PM9 and NM7 are both connected to the third input of the third-input dual-output clock gate C unit. The first output terminal of the output clock gate C unit is connected, the gates of PM10 and NM8 are both connected to the third input terminal of the three-input dual-output clock gate C unit, the drains of PM10 and NM8 are both connected to the second output terminal of the three-input dual-output clock gate C unit, the sources of NM7 and NM8 are both connected to the drain of NM9, the source of NM9 is connected to the drain of NM10, the source of NM10 is grounded, and the gate of NM10 receives the inverted signal of the clock signal CLK.

[0043] Specifically, the latch circuit is constructed using multiple Triple-Input Dual-Output C-elements (TDCs). The circuit structure of this TDC is as follows: Figure 3 As shown in Figure (a), the latch includes three PMOS transistors and three NMOS transistors, with three input terminals A, B, and C and two output terminals X and Y. Its logic function is as follows: input A controls output X, input B controls both outputs X and Y, and input C controls output Y; when A=B=C=0, X=Y=1; when A=B=C=1, X=Y=0; under other input combinations, the output temporarily maintains its current state. This holding characteristic allows the latch to block the propagation of error signals to subsequent circuits when some nodes flip, and achieves state self-recovery through a feedback mechanism. Figure 3As shown in (b), to reduce dynamic power consumption, this TDC further incorporates clock gating technology, forming a clock-gated three-input dual-output C-cell (CG-TDC). During clock invalidation periods, transistor switching activity is suppressed, thereby reducing unnecessary charging and discharging energy consumption and lowering the overall power consumption of the latch.

[0044] The self-recovery capability of the proposed latch under dual node upset (DNU) conditions is analyzed as follows. The latch has 66 possible DNU combinations, which can be divided into three categories: DN1, where any two inputs of the same TDC toggle simultaneously; DN2, where both outputs of the same TDC toggle simultaneously; and DN3, where one input and one output of the same TDC toggle simultaneously.

[0045] DN1 type: One input and one output of the same TDC flip simultaneously. There are a total of 36 types of this type of latch. Taking node pair (Q, N4) as an example, these are the input and output of TDC-3, respectively. When Q and N4 flip simultaneously, since the inputs N6, N10, and N12 of CG-TDC-2 do not flip, all inputs of TDC-3 remain in their original state. Through the feedback loop, the disturbed node can be restored to the correct logic state.

[0046] DN2 type: Any two inputs of the same TDC or C unit flip simultaneously. There are a total of 18 types of this type of DNU in the proposed latches. Taking the two input nodes (Q, N3) of TDC-3 as an example, their flipping will affect the output node N2; since the states of inputs N6, N10, and N12 of CG-TDC-2 remain unchanged, the output of CG-TDC-2 remains unchanged; subsequently, nodes Q and N3 are restored to their correct states through the output of CG-TDC-2.

[0047] DN3 type: Input nodes of different TDCs or C units flip simultaneously. In this case, the flips acting on two different TDCs can be regarded as single node upsets (SNUs) of each TDC; since TDCs are fault-tolerant to single node upsets, the disturbed nodes can recover through the feedback mechanism.

[0048] Based on the location of the toggle, the proposed triple node upset (TNU) in the latch can be divided into three categories: TN1, where the toggle occurs at all three inputs of the same TDC or C unit; TN2, where the toggle occurs at any two inputs and one output of the same TDC or C unit; and TN3, where the toggle occurs at any one input and two outputs of the same TDC. Other possible TNU combinations in the latch can be classified as SNU or DNU cases.

[0049] TN1 type: All three inputs of the same TDC or C unit toggle simultaneously. Since the latch contains six TDCs (including clock-gated types), there are a total of 6 types of this type of TNU. Taking the simultaneous toggle of input nodes Q, N3, and N5 of TDC-3 as an example, its output nodes N2 and N4 change accordingly, causing N9 to change; since input N6 of CG-TDC-4 does not toggle, node N7 will not toggle, causing errors of N2 and N4 to be intercepted at TDC-5. Node N5 is recovered through the output of CG-TDC-6; subsequently, nodes Q and N3 are recovered through the output of CG-TDC-2.

[0050] TN2 type: Any two inputs and one output of the same TDC or C unit flip simultaneously. There are 36 types of TNUs in this category. Taking the simultaneous flipping of input nodes Q, N3, and N4 in TDC-1 as an example, due to the change in the state of input nodes Q and N3, node N2 changes through the output of TDC-3; the subsequent recovery is consistent with the example in TN2. Another example is the simultaneous flipping of Q, N5, and N4. The error is intercepted at TDC-3 and CG-TDC-4, and then Q is recovered through CG-TDC-2. TN3 type: Any one input and two outputs of the same TDC flip simultaneously. There are 18 types of TNUs in this category. Taking the simultaneous flipping of input node Q and output nodes N2 and N4 in TDC-3 as an example, the error is intercepted at TDC-5, Q is recovered through CG-TDC-2, while N3 and N5 remain unchanged, so N2 and N4 are recovered through TDC-3.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A three-node flip-flop tolerant self-recovering latch based on a three-input dual-output C-cell, characterized in that, include: The data input and sampling control module is used to write the input data D to nodes N3, N5, N7, N9, N11 and Q during the sampling phase, and to isolate the input data D during the latching phase. The clock input terminal is used to receive clock signals and transmit them to the data input and sampling control module and the interlock feedback loop. The multi-level interlocked feedback loop includes three three-input dual-output C units TDC1, TDC3, and TDC5, and three three-input dual-output clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6, which are connected sequentially in the order of TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6 to form the feedback loop; the logic states of nodes N3, N5, N7, N9, N11, and Q drive the inputs of the three TDC units. The three-input dual-output (C) unit TDC includes three PMOS transistors PM1 to PM3 and three NMOS transistors NM1 to NM3. The gates of NM2 and PM1 are connected to the first input terminal of TDC. The gates of NM1 and PM2 are connected to the second input terminal of TDC. The gates of NM3 and PM3 are connected to the third input terminal of TDC. The source of PM1 is connected to VDD, the drain of PM1 is connected to the source of PM2 and PM3, the drains of PM2 and NM1 are connected to the first output terminal of TDC, the source of NM1 and the drain of NM2 are connected to the source of NM3, the source of NM2 is grounded, and the drains of NM3 and PM3 are connected to the second output terminal of TDC.

2. The three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell as described in claim 1, characterized in that, In the multi-level interlocked feedback loop, the two outputs of TDC1 are connected to nodes N6 and N12 respectively, the two outputs of CG-TDC2 are connected to nodes Q and N3 respectively, the two outputs of TDC3 are connected to nodes N2 and N4 respectively, the two outputs of CG-TDC4 are connected to nodes N7 and N9 respectively, the two outputs of TDC5 are connected to nodes N10 and N8 respectively, the two outputs of CG-TDC6 are connected to nodes N11 and N5 respectively, and the third input of TDC1, CG-TDC2, TDC3, CG-TDC4, TDC5, and CG-TDC6 are connected to nodes N9, N10, N5, N6, Q, and N2 respectively. The first and second output terminals of the previous stage unit are respectively connected to the two first and second input terminals of the next stage unit. The enable terminals of the clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6 are connected to the clock input terminal.

3. The three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell as described in claim 1, characterized in that, The data input and sampling control module includes six transmission gates TG1 to TG6; each transmission gate includes an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor and the source of the PMOS transistor are connected together to serve as the input terminal of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor are connected together to serve as the output terminal of the transmission gate. The clock input terminal is connected to the gate of the NMOS transistors of transmission gates TG1 to TG6, and the clock input terminal is connected to the gate of the PMOS transistors of transmission gates TG1 to TG6 through an inverter; the input terminals of TG1, TG2, and TG3 are all connected to the data input terminal, and the output terminals of transmission gates TG1 to TG6 are connected to nodes Q, N3, N5, N7, N9, and N11, respectively.

4. The three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell as described in claim 3, characterized in that, When the clock signal CLK=1, the latch is in transparent working mode; transmission gates TG1 to TG6 are turned on, and the input data D is transmitted to nodes Q, N3, N5, N7, N9 and N11 through the transmission gates; When D=0, the logical states of nodes Q, N3, N5, N7, N9, and N11 are 0, and the logical states of nodes N2, N4, N6, N8, N10, and N12 are 1; when D=1, the states of each node are inverted. Clock-gated C units CG-TDC2, CG-TDC4, and CG-TDC6 are enabled, and multi-level interlocking feedback loops are activated to maintain the data state and perform error detection and recovery functions.

5. The three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell according to claim 3, characterized in that, When the clock signal CLK=0, the latch operates in hold mode, the transmission gates TG1 to TG6 are turned off, and the paths between nodes Q, N3, N5, N7, N9 and N11 and the input signal D are cut off. At this time, the three three-input dual-output C units and the three three-input dual-output clock-gated C units are all in working state, forming a ring feedback structure.

6. The three-node flip-tolerant self-recovering latch based on a three-input dual-output C-cell as described in claim 1, characterized in that, The three-input dual-output clock-gated C-cell includes four PMOS transistors PM7 to PM10 and four NMOS transistors NM7 to NM10; The source of PM7 is connected to VDD, the gate of PM7 receives the clock signal CLK, the drain of PM7 is connected to the source of PM8, the gates of PM8 and NM9 are both connected to the second input of the three-input dual-output clock gate C unit, the drain of PM8 and the source of PM9 are both connected to the source of PM10, the gates of PM9 and NM7 are both connected to the first input of the three-input dual-output clock gate C unit, and the drains of PM9 and NM7 are both connected to the third input of the third-input dual-output clock gate C unit. The first output terminal of the output clock gate C unit is connected, the gates of PM10 and NM8 are both connected to the third input terminal of the three-input dual-output clock gate C unit, the drains of PM10 and NM8 are both connected to the second output terminal of the three-input dual-output clock gate C unit, the sources of NM7 and NM8 are both connected to the drain of NM9, the source of NM9 is connected to the drain of NM10, the source of NM10 is grounded, and the gate of NM10 receives the inverted signal of the clock signal CLK.

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