Circuit substrate and semiconductor package including the same

Abstract

Embodiments of the present invention disclose a circuit substrate, comprising: a first insulating layer; a first circuit pattern layer disposed on at least one of an upper surface and a lower surface of the first insulating layer; a second insulating layer covering the first circuit pattern layer; and a first intermediate layer disposed between the first circuit pattern layer and the second insulating layer, wherein the first intermediate layer on the first circuit pattern layer emits secondary ions containing at least one of hydrogen (H), nitrogen (N), oxygen (O) and sulfur (S) when subjected to primary ion irradiation, and among the secondary ions, the intensity of C3N3Cu2 ‑ is greater than the intensity of C2N2Cu ‑ .

Description

Technical Field

[0001] Embodiments of the present invention relate to a circuit board and a semiconductor package, and more specifically, to a circuit board and a semiconductor package having improved bonding strength between an insulating layer (substrate) and an electrode layer. Background Technology

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to substrates of limited size. However, conventional packaging is limited in achieving the desired performance because it is based on mounting a single semiconductor chip.

[0003] Conventional circuit boards or packaging substrates are formed by integrating a processor package with a processor chip and a memory package with a memory chip attached into a single package. These packaging substrates offer the advantage of manufacturing the processor chip and memory chip into a single integrated package, thereby reducing chip mounting area and enabling high-speed signal transmission via shorter paths. Due to these advantages, these packaging substrates are widely used in mobile devices and the like.

[0004] On the other hand, recently, due to the higher specifications of electronic devices such as mobile devices and the adoption of high-bandwidth memory (HBM), package size is increasing. Furthermore, as the required functions of application processors increase, each function needs to be configured as a separate processor chip, with a circuit board on which these processor chips can be mounted. In this case, even when the application processor is divided into two processor chips according to function, the number of terminals (input / output) provided in each processor chip is increasing.

[0005] Furthermore, recently, due to factors such as fifth-generation mobile communication technology (5G), the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals in processor chips has been gradually increasing. Consequently, the number of interconnects between processor chips has also been increasing recently.

[0006] Therefore, in order to mount processor chips on a single circuit board, minimize the spacing between processor chips, and connect processor chips to each other within a limited space, it is necessary to miniaturize the circuit patterns or through electrodes included in the circuit board.

[0007] Furthermore, to reduce signal loss due to the skin effect in circuit patterns, it is necessary to reduce the pattern width and lower the roughness. However, in this case, there is a limitation due to reduced adhesion caused by physical anchoring. Summary of the Invention

[0008] Technical issues

[0009] Embodiments of the present invention provide a circuit board with improved reliability by including an intermediate layer and a semiconductor package including the circuit board.

[0010] Furthermore, the embodiments provide a circuit board having improved bonding strength between an insulating layer and an electrode layer, and a semiconductor package including the circuit board.

[0011] Furthermore, the embodiments provide a circuit board including an intermediate layer disposed on a circuit pattern layer and containing a silane coupling agent, and a semiconductor package including the circuit board.

[0012] The problems to be solved by the embodiments are not limited to the above-described objectives, but also include objectives or effects that can be understood from the technical solutions or embodiments described below.

[0013] Technical solution

[0014] The circuit board according to an embodiment of the present invention includes: a first insulating layer; a second insulating layer disposed on at least one of an upper surface and a lower surface of the first insulating layer; a second insulating layer covering a first circuit pattern layer; and a first intermediate layer disposed between the first circuit pattern layer and the second insulating layer, wherein, when the first intermediate layer on the first circuit pattern layer is irradiated by primary ions, it emits secondary ions containing at least one of hydrogen (H), nitrogen (N), oxygen (O), and sulfur (S), and among the secondary ions, C3N3Cu2 - Its strength is greater than that of C2N2Cu - The intensity.

[0015] In secondary ions, CN - Its strength can be greater than that of C4H2O - The intensity.

[0016] In secondary ions, C4H2O - Its strength can be greater than that of C3N3Cu2 - The intensity.

[0017] In secondary ions, C2N2Cu - The strength can be greater than C 12 H 11 O4 - The intensity.

[0018] The circuit board may include a first electrode layer having a first circuit pattern layer and a first through electrode that passes through a first insulating layer and contacts the first circuit pattern layer.

[0019] The first circuit pattern layer may include a first surface that contacts the first insulating layer and a second surface that contacts the second insulating layer and faces the first surface.

[0020] The second surface can have an uneven structure.

[0021] The first intermediate layer may be disposed on at least a portion of the second surface.

[0022] The first through electrode can contact the first surface.

[0023] The circuit board may include: a second circuit pattern layer disposed on at least one of the upper and lower surfaces of the second insulating layer; a third insulating layer covering the second circuit pattern layer; and a second intermediate layer disposed between the second circuit pattern layer and the third insulating layer.

[0024] The second intermediate layer on the second circuit pattern layer can emit secondary ions containing at least one of nitrogen (N), oxygen (O), and sulfur (S) when irradiated by primary ions, and in the secondary ions, C3N3Cu2 - Its strength can be greater than that of C2N2Cu - The intensity.

[0025] The circuit board may also include a second electrode layer, including a second through electrode that passes through the second insulating layer and contacts the first circuit pattern layer, and the second circuit pattern layer.

[0026] The second circuit pattern layer may include a third surface that contacts the second insulating layer and a fourth surface that contacts the third insulating layer and faces the third surface.

[0027] The fourth surface may have an uneven structure, and the second intermediate layer may be disposed on at least a portion of the fourth surface.

[0028] The circuit board according to the embodiment may include: a first insulating layer; a first circuit pattern layer disposed on at least one of an upper surface and a lower surface of the first insulating layer; a second insulating layer covering the first circuit pattern layer; and a first intermediate layer disposed between the first circuit pattern layer and the second insulating layer, wherein the first intermediate layer comprises nitrogen (N), oxygen (O) and sulfur (S) and has a molecular weight of 100 to 1000.

[0029] According to one embodiment, a semiconductor package may include: a circuit substrate; a connection portion disposed on the circuit substrate; and a chip connected to the connection portion, wherein the circuit substrate includes: a first insulating layer; a first circuit pattern layer disposed on at least one upper surface and a lower surface of the first insulating layer; a second insulating layer covering the first circuit pattern layer; and a first intermediate layer disposed between the first circuit pattern layer and the second insulating layer, wherein when the first intermediate layer on the first circuit pattern layer is irradiated with primary ions, it emits secondary ions containing at least one of hydrogen (H), nitrogen (N), oxygen (O), and sulfur (S), and among the secondary ions, C3N3Cu2 - Its strength can be greater than that of C2N2Cu - The intensity.

[0030] Beneficial effects

[0031] Embodiments of the present invention achieve a circuit board with improved reliability and a semiconductor package including the circuit board by including an intermediate layer.

[0032] Furthermore, the embodiments can realize a circuit board with improved bonding strength between the insulating layer and the electrode layer, and a semiconductor package including the circuit board.

[0033] Furthermore, embodiments can realize a circuit board including an intermediate layer disposed on a circuit pattern layer and containing a silane coupling agent, and a semiconductor package including the circuit board.

[0034] The various advantages and effects of the present invention are not limited to those described above, and are more readily understood in the process of describing specific embodiments of the present invention. Attached Figure Description

[0035] Figure 1 This is a diagram showing the configuration of a circuit board according to an embodiment of the present invention.

[0036] Figure 2 yes Figure 1 A magnified view of a portion of the image.

[0037] Figure 3 yes Figure 2 The diagram of K in the middle.

[0038] Figure 4 This is a graph showing the analytical results obtained by performing time-of-flight secondary ion mass spectrometry (TOF-SIMS) on a first intermediate layer on a first circuit pattern layer of a circuit substrate according to an embodiment.

[0039] Figure 5 The results of advanced polymer chromatography (APC) performed on the intermediate layer of the circuit board according to the embodiment before and after baking are shown.

[0040] Figure 6 The results of a reliability test on a circuit board according to an embodiment are shown.

[0041] Figure 7 This is a diagram illustrating the manufacturing sequence of a circuit board according to an embodiment.

[0042] Figure 8 This is a diagram of the circuit board according to the first embodiment.

[0043] Figure 9This is a plan view of the circuit board according to the first embodiment.

[0044] Figure 10 yes Figure 8 A magnified view of K1.

[0045] Figure 11 yes Figure 8 A magnified view of K2.

[0046] Figure 12 This is a diagram of the circuit board according to the second embodiment.

[0047] Figure 13 This is a diagram of a circuit board according to the third embodiment.

[0048] Figure 14 This is a diagram of the circuit board according to the fourth embodiment.

[0049] Figure 15 This is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0050] Figure 16 This is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0051] Figure 17 This is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0052] Figure 18 This is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0053] Figure 19 This is a cross-sectional view showing a semiconductor package according to the fifth embodiment. Detailed Implementation

[0054] This invention can be modified in various ways and can have various embodiments; therefore, specific embodiments will be shown and described in the accompanying drawings. However, this is not intended to limit the invention to the specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions falling within the spirit and scope of the invention.

[0055] Although terms including ordinal numbers (such as second and first) may be used to describe various components, these components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the invention, a second component may be referred to as a first component, and similarly, a first component may be referred to as a second component. The term "and / or" includes any combination of multiple related descriptive terms, or any one of multiple related descriptive terms.

[0056] When referring to one component as "connected" or "combined" with another component, it should be understood that it can be directly connected or combined with other components, but there may be another component between them. On the other hand, when referring to one component as "directly connected" or "directly combined" with another component, it should be understood that there are no other components between them.

[0057] The terminology used in this application is for describing particular embodiments only and is not intended to limit the invention. Unless the context clearly specifies otherwise, singular expressions include plural expressions. In this application, the terms "comprising" or "having" are intended to indicate the presence of the features, quantities, steps, operations, components, portions, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, portions, or combinations thereof.

[0058] Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms as defined in common dictionaries should be interpreted as having the same meaning as in the context of the relevant technical field, and should not be interpreted in an idealized or overly formal manner unless expressly defined otherwise in this application.

[0059] In the following description, various embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals used, the same or corresponding parts will be designated by the same reference numerals, and repeated descriptions will be omitted.

[0060] Before describing the embodiments, an electronic device comprising a circuit board and a semiconductor package according to an application embodiment will be briefly described. The electronic device includes a motherboard (not shown). The motherboard can be physically and / or electrically connected to various components. For example, the motherboard can be connected to a semiconductor package according to an embodiment. Various semiconductor elements can be mounted on the semiconductor package.

[0061] Semiconductor components can include active and / or passive components. Active components can be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of components are integrated into a single chip. Semiconductor components can be logic chips, memory chips, etc. Logic chips can be central processing units (CPUs), graphics processing units (GPUs), etc. For example, a logic chip can be an application processor (AP) chip (which includes at least one of a CPU, GPU, digital signal processor, encryption processor, microprocessor, and microcontroller); or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc.; or it can be a chipset that includes a specific combination of the above components.

[0062] The memory chip can be a stacked memory, such as high-bandwidth memory (HBM). In addition, the memory chip can also include memory chips such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)) or flash memory.

[0063] On the other hand, the product group using the semiconductor packaging of this embodiment can be any one of chip-scale packaging (CSP), flip chip-scale packaging (FC-CSP), flip chip ball grid array (FC-BGA), package-on-package (POP), and system-in-package (SIP), but is not limited thereto.

[0064] Furthermore, electronic devices can include smartphones, personal digital assistants, digital camcorders, digital cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video game consoles, smartwatches, automobiles, and so on. However, electronic devices are not limited to these; they can certainly be any other electronic device that processes data.

[0065] Figure 1 This is a diagram showing the configuration of a circuit board according to an embodiment of the present invention. Figure 2 yes Figure 1 A magnified view of a portion of the image. Figure 3 yes Figure 2 The chart of K in the middle, Figure 4 This is a graph showing the analytical results obtained by performing time-of-flight secondary ion mass spectrometry (TOF-SIMS) on a first intermediate layer on a first circuit pattern layer of a circuit substrate according to an embodiment.

[0066] Reference Figure 1 According to an embodiment, the circuit board 100 may include an insulating layer DL, a circuit pattern layer CP, and an intermediate layer IL. The insulating layer DL may include a first insulating layer DL1 and a second insulating layer DL2, wherein the second insulating layer DL2 covers at least a portion of the circuit pattern layer CP and the intermediate layer IL on the first insulating layer DL1.

[0067] The circuit board 100 according to this embodiment can correspond to at least a portion of the inner stacked layer region and the outer stacked layer region of the substrate. For example, the circuit board 100 can correspond to the inner stacked layer region or the outer stacked layer region of the substrate (e.g., a package substrate). Therefore, the first insulating layer DL1, the circuit pattern layer CP, the intermediate layer IL, and the second insulating layer DL2 shown can be the inner stacked layer region or the outer stacked layer region of the substrate. For example, in the case of the inner stacked layer region, the first insulating layer DL1 can correspond to the core layer. Furthermore, the first insulating layer DL1 or the second insulating layer DL2 can have vias, such that the circuit pattern layer CP can be electrically connected to each other on different surfaces through the vias of the first insulating layer DL1 and the second insulating layer DL2. In addition, the outer stacked layer region refers to the insulating layer / circuit pattern layer / insulating layer used for electrical connection with other components and the substrate. The inner stacked layer region can be a region different from the outer stacked layer region, or a region between outer stacked layer regions that are spaced apart from each other.

[0068] The insulating layer DL can be made of an insulating material. The insulating layer DL may include at least one layer. When the insulating layer DL has a multilayer structure, the multiple insulating layers DL may contain the same insulating material, but are not limited thereto. For example, at least one of the multiple insulating layers DL may contain an insulating material that is different from the insulating material of at least one other insulating layer DL.

[0069] The insulating layer DL of the circuit board can be rigid or flexible. For example, the insulating layer DL of the circuit board can comprise glass or plastic. For example, the insulating layer DL of the circuit board can comprise chemically reinforced / semi-reinforced glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer DL of the substrate can comprise reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer DL of the circuit board can comprise sapphire. For example, the insulating layer DL of the substrate can comprise an optically isotropic film. For example, the insulating layer DL of the substrate can comprise cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer DL of the substrate can be formed from a material comprising fillers and insulating resins. For example, the insulating layer DL of the substrate can have a structure in which silica or alumina fillers are disposed in a thermosetting resin or a thermoplastic resin.

[0070] The insulating layer DL can have a structure in which multiple different insulating materials are stacked. An example of such an arrangement will be described in more detail below.

[0071] In one embodiment, the insulating layer DL may include a core layer containing reinforcing members or a coreless layer. Here, the core layer may be an insulating layer containing reinforcing members and having a thickness exceeding 30 μm in its stacking direction (X-axis direction). Alternatively, the insulating layer may include multiple layers disposed above and below the core layer that do not contain reinforcing members. In this case, the circuit board may be a core board. The reinforcing members may also be referred to as reinforcing fibers or glass fibers.

[0072] The reinforcing member can be a glass fiber material extending horizontally along the insulation layer, and its meaning is different from that of the fillers spaced apart from each other.

[0073] In another embodiment, the insulating layer DL of the substrate can be a coreless substrate without a core layer. For example, the insulating layer DL of the substrate can include organic materials without reinforcing members, which enables excellent processability, ultrathin substrates, and miniaturization of the electrode layers of the substrate. For example, as the insulating layer DL of the substrate, Ajinomoto Additive Fabrication Film (ABF) products from Ajinomoto Co., Ltd. can be used, as well as flame retardant-4 (FR-4), bismaleimide triazine (BT), photoimaging dielectric (PID) resin, BT, etc. For example, the insulating layer DL can include multiple layers made of ABF.

[0074] Furthermore, as described above, when the insulating layer DL corresponds to the outer stacked layer region, the second insulating layer DL2 can be a photoresist layer. For example, the second insulating layer DL2 of the substrate can be a photoresist layer disposed on the uppermost side of the substrate.

[0075] The second insulating layer DL2 can be a solder resist layer containing organic polymer materials. For example, the second insulating layer DL2 of the circuit board can contain resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. In this embodiment, the second insulating layer DL2 can be any one of a photoresist layer, a cover layer, or a polymer material.

[0076] Furthermore, the upper second insulating layer DL2 may have an opening OP. The second insulating layer DL2 can be electrically connected to other semiconductor components, circuit boards, etc., through the opening OP. However, when the second insulating layer is located in the stacked region of the inner layers of the circuit board, the second insulating layer may not have an opening.

[0077] Furthermore, in the modified example, both the first insulating layer DL1 and the second insulating layer DL2 can be solder resist layers disposed on the outer side of the substrate. Such solder resist layers can have the function of preventing solder flow during soldering by having low solder wettability, or the function of preventing external moisture or contaminants from penetrating into the circuit board.

[0078] The description of insulating layer DL or first insulating layer DL1 and second insulating layer DL2 also applies to the insulating layers described below, as well as the first insulating layer and the second insulating layer.

[0079] The circuit pattern layer CP can be disposed on at least one of the upper and lower surfaces of the first insulating layer DL1. Hereinafter, the circuit pattern layer will be described as being stacked based on an upper or stacking direction. However, it should be understood that the circuit pattern layer can also be disposed on the lower part of the insulating layer as described above.

[0080] Further reference Figure 2 The circuit pattern layer CP can be disposed on the upper surface US of the first insulating layer DL1. The lower surface CBS of the circuit pattern layer CP can contact the upper surface of the first insulating layer DL1. In addition, the second insulating layer DL2 can cover the circuit pattern layer CP and the intermediate layer IL.

[0081] The circuit pattern layer CP can be made of a conductive material. For example, the circuit pattern layer CP can be a conductor for transmitting electrical signals. The circuit pattern layer CP can be made of a highly conductive metallic material. The circuit pattern layer CP can be formed from at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the circuit pattern layer CP can be formed from a paste or solder paste containing at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) and having excellent bonding strength. Preferably, the circuit pattern layer CP can be formed from copper (Cu), which has high conductivity and is inexpensive.

[0082] The first insulating layer DL1 may include vias or through-holes. The circuit pattern layer CP can be electrically connected to circuit pattern layers disposed on different surfaces or layers through the vias of the first insulating layer DL1. The description of the circuit pattern layer also applies to the circuit pattern layers described below.

[0083] The intermediate layer IL can be disposed on the upper surface CUS of the circuit pattern layer CP. The intermediate layer IL can be disposed on the upper part of the circuit pattern layer CP and is covered by the second insulating layer DL2.

[0084] An intermediate layer IL can be disposed between the second insulating layer DL2 and the circuit pattern layer CP, thereby improving the bonding strength between the second insulating layer DL2 and the circuit pattern layer CP. In other words, the intermediate layer IL can serve as a bonding facilitating layer. This structure improves the reliability of the circuit board according to this embodiment.

[0085] Furthermore, the intermediate layer IL may overlap with the circuit pattern layer CP along the stacking direction. Furthermore, the intermediate layer IL may overlap with the first insulating layer DL1 and the second insulating layer DL2 along the stacking direction. Furthermore, the intermediate layer IL is not disposed within the opening OP of the second insulating layer DL2. Therefore, the intermediate layer IL may at least partially not overlap with the opening OP of the second insulating layer DL2. The sides of the intermediate layer IL may be partially exposed through the opening OP.

[0086] The intermediate layer IL may comprise a silane. In one embodiment, the intermediate layer IL may comprise a silane coupling agent containing a silane. For example, the intermediate layer IL may be an organosilicon compound having two functional groups with different reactivity. One of the two functional groups may react with an organic compound, and the other functional group may react with an inorganic compound. In one embodiment, the intermediate layer IL may comprise nitrogen (N), oxygen (O), and sulfur (S), and have a molecular weight of 100 to 1000.

[0087] The intermediate layer IL can be represented by the following chemical formula 1.

[0088] [Chemical Formula 1]

[0089] Here, Y refers to a functional group that is bonded to an organic compound (e.g., vinyl, epoxy, or amino); X refers to a functional group that is hydrolyzed by water or moisture to form a silanol. Such silanols can correspond to inorganic materials. Representative examples of X include chlorine, alkoxy, and acetoxy groups.

[0090] As described above, silane coupling agents can provide enhanced adhesion at the interface between organic and inorganic materials. Therefore, when the bonding strength between the circuit pattern layer and the insulating layer is improved, the intermediate layer IL can provide the effect of improving the strength and performance of the circuit board.

[0091] Further reference Figure 3 and Figure 4 The intermediate layer IL can be located on top of the circuit pattern layer CP. The upper part of the circuit pattern layer CP can have an uneven structure. For example, multiple protrusions PT can be formed on the upper part of the circuit pattern layer CP. Alternatively, the upper part of the circuit pattern layer CP can have a roughness (Ra) of less than 0.4 μm. Using this structure, the intermediate layer IL can also have a shape corresponding to the protrusions PT. In one embodiment, the intermediate layer IL can have a predetermined pattern corresponding to the structure of the protrusions PT of the circuit pattern layer CP. Due to the protruding structure of the circuit pattern layer CP, the surface area of ​​the upper surface of the circuit pattern layer CP can be increased. Therefore, the bonding area between the circuit pattern layer CP, the intermediate layer IL, and the insulating layer (second insulating layer) is increased, thereby improving the bonding strength between them. As a result, the reliability of the circuit board is improved.

[0092] Furthermore, the intermediate layer IL on the circuit pattern layer CP of the circuit board may emit secondary ions when irradiated by primary ions. According to this embodiment, the secondary ions may contain at least one of hydrogen (H), nitrogen (N), oxygen (O), and sulfur (S). In this case, Figure 4 SIMS data can be analytical data obtained through TOF-SIMS. SIMS data is the analysis result of positive or negative ions emitted when the surface of a target (an intermediate layer on a circuit pattern layer) is irradiated by a primary ion and then bombarded by that primary ion. Based on this SIMS data, chemical composition and surface structure can be analyzed. Primary ions can be selected from Aun+, C... 60 +, SF5+, O2+, Cs+Bi+, etc.

[0093] SIMS data can indicate the molecular weight distribution of secondary ions with mass when etching the surface of the intermediate layer IL in a direction opposite to the stacking direction (towards the lower part of the first insulating layer DL1).

[0094] More specifically, when a target is irradiated with ions and ionization occurs, the compound structure may rearrange to form individual fragments. Since the degree of disintegration of these fragments varies depending on the initial composition, the target or a component of the target can be identified based on a specific fragment (or component) with a particular peak mass.

[0095] Table 1 below shows the mass data of each fragment of the interlayer IL according to this embodiment (specifically referring to azole, which is the core structure of the interlayer). Furthermore, since in SIMS, the mass of a fragment is measured based on the amount of ion irradiation per unit charge (i.e., per unit charge), the mass may correspond to the mass per unit charge (m / z). Additionally, in intensity, AU stands for "arbitrary unit," which means any value or relative value.

[0096] [Table 1]

[0097] In other words, when the intermediate layer on the circuit pattern layer according to this embodiment is irradiated with primary ions, secondary ions containing at least one of hydrogen (H), nitrogen (N), oxygen (O), and sulfur (S) may be emitted. In this case, multiple secondary ions may be present, such as... Figure 4 As shown. Specifically, in secondary ions, C3N3Cu2 - Its strength can be greater than that of C2N2Cu - The intensity. Furthermore, according to the SIMS data of the intermediate layer in this embodiment, in the secondary ions, CN... - Its strength can be greater than that of C4H2O -The intensity. Furthermore, according to the SIMS data of the intermediate layer in this embodiment, in the secondary ions, C2N2Cu... - The strength can be greater than C 12 H 11 O4 - The strength of the interlayer is improved. Using this configuration, the interlayer in the circuit board can enhance the bonding strength between the insulating layer and the circuit pattern layer by incorporating a silane coupling agent. Specifically, by using components exhibiting the aforementioned ionic strength, the interlayer can have an increased crosslinking density, thereby effectively preventing moisture penetration. That is, the thickness of the interlayer can be reduced without changing the silane content through baking, pressing, etc., thereby increasing the density. More specifically, during baking, moisture condensation and blistering can be more effectively prevented, while excessive shrinkage during the stacking process is reduced. Therefore, the molecular weight per unit area of ​​the interlayer can potentially increase. Thus, by suppressing moisture penetration into the interlayer, the bonding strength or adhesion between the insulating layer and the circuit pattern layer can be improved. Furthermore, delamination can also be suppressed.

[0098] Furthermore, the silane concentration in the intermediate layer can be higher than that in the insulating layer. In other words, the silane concentration in the intermediate layer can be higher than that in the insulating layer. Furthermore, the silane concentration in the intermediate layer can be higher than that in the circuit pattern layer. In other words, the silane concentration in the intermediate layer can be higher than that in the circuit pattern layer. Therefore, even when the roughness is reduced as described above, the bonding strength between the circuit pattern layer and the insulating layer can be improved.

[0099] Furthermore, the above description of the first insulating layer DL1, the second insulating layer DL2, the intermediate layer IL, and the circuit pattern layer CP can be applied to a region of a circuit board (having a stacked structure of a first insulating layer, a second insulating layer, an intermediate layer, and a circuit pattern layer). For example, the description of the first insulating layer DL1, the second insulating layer DL2, the intermediate layer IL, and the circuit pattern layer CP can be applied to the first insulating layer, the second insulating layer, the first intermediate layer, and the first circuit pattern layer (or the first electrode layer) described below. Furthermore, the description of the first insulating layer DL1, the second insulating layer DL2, the intermediate layer IL, and the circuit pattern layer CP can also be applied to the second insulating layer, the third insulating layer, the second intermediate layer, and the second circuit pattern layer (or the second electrode layer) described below. Furthermore, the description of the first insulating layer DL1, the second insulating layer DL2, the intermediate layer IL, and the circuit pattern layer CP can be applied to all the first to third insulating layers, the first and second intermediate layers, the first and second circuit pattern layers (or the first and second electrode layers).

[0100] Figure 5The results of advanced polymer chromatography (APC) performed on the intermediate layer of the circuit board according to this embodiment before and after baking are shown. Figure 6 The results of a reliability test performed on the circuit board according to this embodiment are shown.

[0101] Reference Figure 5 The results of APC performed on the intermediate layer during or before baking are shown. The x-axis represents time and can be correlated with molecular weight. The y-axis represents the relative area ratio. Furthermore, Table 2 below shows the area variation (%) at different molecular weights (peaks 2-7, at broad peaks)

[0102] [Table 2]

[0103] Referring to Table 2, it is shown that the area of ​​peak 5, with a relatively large molecular weight, increased after baking compared to before baking, while the area at the broadening point decreased after baking compared to before baking. In other words, it can be seen that the density of the intermediate layer increased due to baking. Furthermore, referring to... Figure 6 As shown in Table 3 below, delamination is suppressed and peel strength is improved after baking the intermediate layer. Therefore, it can be seen that the reliability of the circuit board is improved. Figure 6 In the diagram, the y-axis represents the relative value of the peel strength. The unit of peel strength can be kgf / cm. Furthermore, compared to the unbaked comparative example, the bond strength of Example 1 is 1.3 times that of the comparative example. Additionally, the bond strength of Examples 2 and 3 is approximately 1.6 times that of the comparative example.

[0104] [Table 3]

[0105] Figure 7 This is a diagram illustrating the manufacturing sequence of a circuit board according to an embodiment. (Refer to...) Figure 7 In embodiment (a), a first insulating layer DL1 is prepared. The first insulating layer DL1 may be a core layer or a coreless layer. Alternatively, the first insulating layer DL1 may be an insulating layer disposed on the upper part of the inner stacked layer region as described above. When the first insulating layer DL1 is a core layer, the first insulating layer DL1 may be a copper-clad laminate (CCL). Furthermore, a process of forming a through-hole through the first insulating layer DL1 may be performed. Although not shown, the through-hole may be formed and filled with a conductive material.

[0106] The circuit pattern layer CP' can be stacked on the upper and lower surfaces of the first insulating layer DL1. The circuit pattern layer CP' can have various patterns using dry film or the like.

[0107] Reference Figure 7(b) A circuit pattern layer CP can be formed by etching a predetermined pattern onto the first insulating layer DL1. A portion of the first insulating layer DL1 can be exposed or left open. Furthermore, the upper part of the circuit pattern layer CP can have a protrusion PT, which can be formed by etching.

[0108] Reference Figure 7 (c) An intermediate layer IL can be formed on the circuit pattern layer CP. A process such as masking can be performed to form the intermediate layer IL on the circuit pattern layer CP. Furthermore, the intermediate layer IL can be baked.

[0109] Reference Figure 7 (d) A second insulating layer DL2' can be formed on top of the first intermediate layer IL1 to cover the intermediate layer IL and the circuit pattern layer CP. Then, heat and pressure can be applied. Thus, the second insulating layer, the intermediate layer IL, the circuit pattern layer CP, and the first insulating layer DL1 can be bonded to each other. Depending on its position on the circuit board, the second insulating layer can be a solder resist layer or an insulating layer.

[0110] Figure 8 This is a diagram of the circuit board according to the first embodiment. Figure 9 This is a plan view of the circuit board according to the first embodiment. Figure 10 yes Figure 8 Enlarged view of K1, Figure 11 yes Figure 8 A magnified view of K2.

[0111] Reference Figures 8 to 11 The circuit board 100A according to the first embodiment may include an insulating layer 110, an electrode layer 120, and an intermediate layer 130. Except as described below, the above description of the insulating layer, the circuit pattern layer, and the intermediate layer can be applied to the insulating layer 110, the electrode layer 120, and the intermediate layer 130.

[0112] Specifically, the insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The first insulating layer 111 and the second insulating layer 112 may contain insulating material as an inner stacked layer region in the circuit board 100A. The first insulating layer 111 and the second insulating layer 112 may be made of the same or different materials. The boundary between the first insulating layer 111 and the second insulating layer 112 may be distinguishable or not, depending on the analytical method. Furthermore, the third insulating layer 113 may be a photoresist layer.

[0113] Furthermore, the first insulating layer 111 may be located between the second insulating layers 112. The second insulating layer 112 may be disposed on the upper and lower surfaces of the first insulating layer 111.

[0114] Furthermore, the third insulating layer 113 may be located on the upper surface or the lower surface of the second insulating layer 112. In the following description, the stacking direction (X-axis direction) will be used.

[0115] The second insulating layer 112 can be disposed on the first insulating layer 111, and the third insulating layer 113 can be located on the second insulating layer 112.

[0116] Furthermore, electrode layer 120 may include a first electrode layer 121 and a second electrode layer 122. The first electrode layer 121 may include a first circuit pattern layer 121a and a first through electrode 121b. The second electrode layer 122 may include a second circuit pattern layer 122a and a second through electrode 122b. Each circuit pattern layer may be a pad and / or trace for each electrode layer. The through electrode may be a via electrode connected to a circuit pattern layer. For example, the through electrode may be disposed between multiple circuit pattern layers disposed on different layers.

[0117] The first circuit pattern layer 121a may be disposed on each of the upper and lower surfaces of the first insulating layer 111. The first through electrode 121b may pass through the first insulating layer 111 and may contact the first circuit pattern layer 121a.

[0118] The second circuit pattern layer 122a may be disposed on each of the upper and lower surfaces of the second insulating layer 112. The second through electrode 122b may pass through the second insulating layer 112 and may contact the second circuit pattern layer 122a.

[0119] Intermediate layer 130 may include a first intermediate layer 131 and a second intermediate layer 132. The first intermediate layer 131 may be disposed between the first circuit pattern layer 121a and the second insulating layer 112. In addition, the second intermediate layer 132 may be disposed between the second circuit pattern layer 122a and the third insulating layer 113.

[0120] Furthermore, the first insulating layer 111 and the second insulating layer 112 may include vias or through holes V1 and V2. The through holes may include a first through hole V1 penetrating the first insulating layer 111 and a second through hole V2 penetrating the second insulating layer 112. Additionally, each of the through holes V1 and V2 described above may have a through electrode.

[0121] Furthermore, the second insulating layer 112 may cover at least a portion of the first circuit pattern layer 121a. In this case, the first intermediate layer 131 may be located outside the second via V2 of the second insulating layer 112. For example, when the area of ​​the second via V2 increases in the stacking direction based on the center of the hole in a partial region, the second via V2 or the second through electrode 122b may partially overlap with the first intermediate layer 131 in the stacking direction.

[0122] However, in other cases besides this structure, the first intermediate layer 131 may not overlap with the second via V2 or the second through electrode 122b in the stacking direction (X-axis direction).

[0123] In addition, the first through-hole V1 or the first through electrode 121b may partially overlap with the first intermediate layer 131 or the second intermediate layer 132 in the stacking direction (X-axis direction).

[0124] Furthermore, the third insulating layer 113 may cover at least a portion of the second circuit pattern layer 122a. The third insulating layer 113 may include an opening OP for electrical connection to semiconductor elements, interposers, packaging substrates, etc. The second circuit pattern layer 122a may be exposed through the opening OP. In addition, a portion of the sidewalls of the intermediate layer IL may also be exposed through the opening OP.

[0125] The second intermediate layer 132 may be located outside the opening OP of the third insulating layer 113. Depending on the structure of the opening OP, the opening OP may overlap with the second intermediate layer IL in the stacking direction (X-axis direction), or it may not overlap.

[0126] Furthermore, when the opening OP overlaps with the first through-hole and the second through-hole in the stacking direction, the intermediate layer can overlap with the opening OP and the first and second through-holes according to the width between the opening OP and the first and second through-holes. For example, when the area of ​​the first through-hole V1 or the first through-electrode 121b is larger than the area of ​​the second through-hole V2 or the second through-electrode 122b, the first through-hole V1 or the first through-electrode 121b can at least partially overlap with the first intermediate layer 131 in the stacking direction.

[0127] The first intermediate layer 131 and the second intermediate layer 132 can contact the first circuit pattern layer 121a and the second circuit pattern layer 122a, as well as the second insulating layer 112 and the third insulating layer 113, and improve the bonding strength between the first circuit pattern layer 121a and the second circuit pattern layer 122a, which are made of different materials, and the second insulating layer 112 and the third insulating layer 113.

[0128] Furthermore, when the first intermediate layer 131 on the first circuit pattern layer 121a is irradiated with primary ions, the first intermediate layer on the first circuit pattern layer can emit secondary ions containing at least one of nitrogen (N), oxygen (O), and sulfur (S) upon irradiation with primary ions, and among these secondary ions, C3N3Cu2 - Its strength can be greater than that of C2N2Cu -The intensity. This description can also be applied to the above description of the intermediate layer. Similarly, when the second intermediate layer 132 on the second circuit pattern layer 122a is irradiated with primary ions, the second intermediate layer 132 on the second circuit pattern layer 122a can emit secondary ions containing at least one of nitrogen (N), oxygen (O), and sulfur (S) upon irradiation with primary ions, and among these secondary ions, C3N3Cu2 - Its strength can be greater than that of C2N2Cu - The intensity.

[0129] Furthermore, the first circuit pattern layer 121a according to this embodiment may include a first surface S1 and a second surface S2. The first surface S1 may be in contact with the first insulating layer 111. For example, the first through electrode 121b may be in contact with the first surface S1 of the first circuit pattern layer 121a. The second surface S2 may face the first surface S1 and may be in contact with the second insulating layer 112.

[0130] As described above, the second surface S2 of the first circuit pattern layer 121a may include an uneven structure or protrusions. Furthermore, based on the second surface S2, the first intermediate layer 131 may be disposed on at least a portion of the second surface S2. For example, the first intermediate layer 131 may be disposed on the entire area of ​​the second surface S2 except for the area where the second through electrode 122b is disposed. Therefore, the bonding strength between the second insulating layer 112 and the first electrode layer 121 can be further improved.

[0131] Furthermore, the second circuit pattern layer 122a may include a third surface S3 and a fourth surface S4. The third surface S3 may contact the second insulating layer 112. For example, the second through electrode 122b may contact the third surface S3 of the second circuit pattern layer 122a. The fourth surface S4 may face the third surface S3 and may contact the third insulating layer 113.

[0132] Furthermore, the fourth surface S4 of the second circuit pattern layer 122a may include a concave-convex structure or protrusions. Based on the fourth surface S4, the second intermediate layer 132 may be disposed on at least a portion of the fourth surface S4. Therefore, the second intermediate layer 132 may contact at least a portion of the fourth surface S4. For example, the second intermediate layer 132 may be disposed on the entire area of ​​the fourth surface S4 except for the opening OP region. Therefore, the bonding strength between the third insulating layer 113 and the second electrode layer 122 can be further improved.

[0133] Figure 12 This is a diagram of the circuit board according to the second embodiment.

[0134] Reference Figure 12The circuit board 100B according to the second embodiment may include an insulating layer 110, an electrode layer 120, and an intermediate layer 130. Except as described below, the above description of the insulating layer, electrode layer, and intermediate layer can be applied to the insulating layer 110, electrode layer 120, and intermediate layer 130.

[0135] According to this embodiment, the intermediate layer 130 may consist only of the second intermediate layer 132. That is, the first intermediate layer may not exist on the first circuit pattern layer 121a. Furthermore, the intermediate layer 130 may be located on the second circuit pattern layer 122a.

[0136] Using this structure, the second intermediate layer 132 can be disposed between the third insulating layer 113 and the second circuit pattern layer or the second electrode layer 122, thereby improving the bonding strength between the third insulating layer 113 and the second circuit pattern layer or the second electrode layer 122.

[0137] Figure 13 This is a view of the circuit board according to the third embodiment.

[0138] Reference Figure 13 The circuit board 100C according to the third embodiment may include an insulating layer 110, an electrode layer 120, and an intermediate layer 130. Except as described below, the above description of the insulating layer, electrode layer, and intermediate layer can be applied to the insulating layer 110, electrode layer 120, and intermediate layer 130.

[0139] According to this embodiment, the intermediate layer 130 may consist only of the first intermediate layer 131. That is, the second intermediate layer may not exist on the second circuit pattern layer 122a. Furthermore, the intermediate layer 130 may be located on the first circuit pattern layer 121a.

[0140] Using this structure, the first intermediate layer 131 can be disposed between the second insulating layer 112 and the first circuit pattern layer or the first electrode layer 121, thereby improving the bonding strength between the second insulating layer 112 and the first circuit pattern layer or the first electrode layer 121.

[0141] Figure 14 This is a view of the circuit board according to the fourth embodiment.

[0142] According to the fourth embodiment, the circuit board 100D may include an insulating layer 110, an electrode layer 120, and an intermediate layer 130. Except as described below, the above description of the insulating layer, electrode layer, and intermediate layer can be applied to the insulating layer 110, electrode layer 120, and intermediate layer 130.

[0143] According to this embodiment, the intermediate layer 130 may include a first intermediate layer 131 and a second intermediate layer 132. Similar to the intermediate layer of the circuit board according to the first embodiment, the intermediate layer 130 according to this embodiment may be located between the first circuit pattern layer 121a and the second insulating layer 112, or between the second circuit pattern layer 122a and the third insulating layer 113. With this structure, the first intermediate layer 131 and the second intermediate layer 132 can improve the bonding strength between the second insulating layer 112 and the first circuit pattern layer (or the first electrode layer 121), or improve the bonding strength between the third insulating layer 113 and the second circuit pattern layer (or the second electrode layer 122).

[0144] However, in this embodiment, the intermediate layer 130 may be disposed in a portion of the region between the first circuit pattern layer 121a and the second insulating layer 112, or in a portion of the region between the second circuit pattern layer 122a and the third insulating layer 113. In this embodiment, the intermediate layer 130 may be located between the insulating layer and the circuit pattern layer depending on the volume or area of ​​the circuit pattern layer or via. For example, the intermediate layer 130 may be disposed between an electrode layer on which multiple circuit pattern layers are disposed and an insulating layer in contact therewith. For example, when multiple circuit pattern layers are disposed, or when the area of ​​the circuit pattern layer disposed on the second electrode layer is larger than the area disposed on the first electrode layer, a larger intermediate layer may be disposed on the second electrode layer than on the first electrode layer to improve the bonding strength. Therefore, depending on the arrangement of the circuit pattern layers, a decrease in the bonding strength between the insulating layer and the circuit pattern layer can be prevented.

[0145] Furthermore, multiple intermediate layers can be provided within the electrode layer on which multiple through electrodes are disposed. This improves the bonding strength between the circuit pattern layer and the insulating layer.

[0146] Figure 15 This is a cross-sectional view showing a semiconductor package according to the first embodiment. Figure 16 This is a cross-sectional view showing a semiconductor package according to the second embodiment. Figure 17 This is a cross-sectional view showing a semiconductor package according to a third embodiment. Figure 18 This is a cross-sectional view showing a semiconductor package according to the fourth embodiment. Figure 19 This is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0147] In the various semiconductor packages described below, the aforementioned circuit board may be located in a portion of the area or may correspond to a single board.

[0148] Reference Figure 15 The semiconductor package of the first embodiment may include a first substrate 1100, a second substrate 1200 and a semiconductor element 1300.

[0149] The first substrate 1100 may be a "packaging substrate" or a "circuit substrate," or may include either a packaging substrate or a circuit substrate. For example, the first substrate 1100 may provide space for bonding at at least one external substrate. The external substrate may be a second substrate 1200 bonded to the first substrate 1100. Furthermore, the external substrate may be a motherboard included in an electronic device bonded to the lower portion of the first substrate 1100.

[0150] Furthermore, although not shown in the accompanying drawings, the first substrate 1100 can provide space for mounting at least one semiconductor element.

[0151] The first substrate 1100 may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0152] The second substrate 1200 can be disposed on the first substrate 1100.

[0153] The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide space for mounting at least one semiconductor element. The second substrate 1200 may be connected to at least one semiconductor element 1300. For example, the second substrate 1200 may provide space for mounting a first semiconductor element 1310 and a second semiconductor element 1320. The second substrate 1200 may electrically connect the first semiconductor element 1310 and the second semiconductor element 1320, and electrically connect the first semiconductor element 1310 and the second semiconductor element 1320 to the first substrate 1100. That is, the second substrate 1200 may perform horizontal connections between multiple semiconductor elements and vertical connections between semiconductor elements and the packaging substrate.

[0154] exist Figure 15 The diagram shows two semiconductor elements 1310 and 1320 disposed on the second substrate 1200, but the invention is not limited thereto. For example, one semiconductor element or three or more semiconductor elements may be disposed on the second substrate 1200.

[0155] The second substrate 1200 may be disposed between at least one semiconductor element 1300 and the first substrate 1100.

[0156] In one embodiment, the second substrate 1200 may be an active interposer used as a semiconductor element. When the second substrate 1200 is used as a semiconductor element, the semiconductor package of this embodiment may have a vertically stacked structure on the first substrate 1100 and serve as multiple logic chips. The logic chip functionality may include both active and passive element functionality. For active elements, unlike passive elements, their current and voltage characteristics may not be linear, while for active interposers, the active interposer may have the functionality of an active element. Furthermore, the active interposer may serve as a corresponding logic chip and perform signal transmission functions between the second logic chip disposed on it and the first substrate 1100.

[0157] According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may perform a signal relay function between the semiconductor element 1300 and the first substrate 1100, and may function as a passive element such as a resistor, capacitor, or inductor. For example, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speed, the number of terminals in the semiconductor element 1300 may gradually increase. That is, the increased number of terminals provided in the semiconductor element 1300 leads to a decrease in the width of the terminals or the spacing between multiple terminals. In this case, the first substrate 1100 may be connected to the motherboard of an electronic device. Therefore, in order to make the electrodes disposed on the first substrate 1100 have the width and spacing to connect with the semiconductor element 1300 and the motherboard, there is a problem that the thickness of the first substrate 1100 increases or the layer structure of the first substrate 1100 becomes more complex. Therefore, in the first embodiment, the second substrate 1200 may be disposed on the first substrate 1100 and the semiconductor element 1300. Furthermore, the second substrate 1200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor element 1300.

[0158] Semiconductor element 1300 can be a logic chip, a memory chip, etc. A logic chip can be a CPU, a GPU, etc. For example, a logic chip can be an AP that includes at least one of a CPU, GPU, digital signal processor, encryption processor, microprocessor, and microcontroller, or an analog-to-digital converter, ASIC, etc., or a chipset that includes a specific combination of the above components. Furthermore, a memory chip can be a stacked memory, such as HBM. Additionally, a memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0159] On the other hand, the semiconductor package according to the first embodiment may include a connection portion.

[0160] For example, a semiconductor package may include a first connection portion 1410 disposed between a first substrate 1100 and a second substrate 1200. The first connection portion 1410 may electrically connect the first substrate 1100 and the second substrate 1200 while bonding the first substrate 1100 to the second substrate 1200.

[0161] For example, a semiconductor package may include a second connection portion 1420 disposed between a second substrate 1200 and a semiconductor element 1300. The second connection portion 1420 may electrically connect the second substrate 1200 and the semiconductor element 1300 while bonding the semiconductor element 1300 to the second substrate 1200.

[0162] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first substrate 1100. The third connection portion 1430 can electrically connect the first substrate 1100 and the motherboard while bonding the first substrate 1100 to the motherboard.

[0163] In this configuration, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 can electrically connect multiple components using at least one of the following bonding methods: wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 function to electrically connect multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as having electrical connections rather than solder or wires.

[0164] Wire bonding methods can refer to electrically connecting multiple components using wires such as gold (Au). Alternatively, solder bonding methods can use materials containing at least one of tin (Sn), silver (Ag), and copper (Cu) to electrically connect multiple components. Furthermore, direct metal-to-metal bonding methods can refer to directly bonding multiple components by applying heat and pressure between them to induce recrystallization, without the need for components such as solder, wires, or conductive adhesives. Additionally, direct metal-to-metal bonding methods can be bonding methods performed by a second connection portion 1420. In this case, the second connection portion 1420 can be a metal layer formed between the multiple components through recrystallization.

[0165] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 can be joined together by a thermocompression bonding method. The thermocompression bonding method can refer to applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 to directly join the multiple components.

[0166] In this case, on at least one of the first substrate 1100 and the second substrate 1200, an electrode having a first connecting portion 1410, a second connecting portion 1420, and a third connecting portion 1430 may be provided with a protrusion that protrudes outward from the insulating layer of the corresponding substrate. The protrusion may protrude outward from either the first substrate 1100 or the second substrate 1200.

[0167] A protrusion may be referred to as a bump, a pillar, or a support. Preferably, the protrusion may be one of the electrodes of a second substrate 1200 having a second connection portion 1420 thereon for bonding with a semiconductor element 1300. That is, as the terminal spacing of the semiconductor element 1300 becomes smaller, short circuits may occur between the multiple second connection portions 1420 that are respectively connected to multiple terminals of the semiconductor element 1300 by a conductive adhesive (e.g., solder). Therefore, in this embodiment, thermoforming can be performed to reduce the volume of the second connection portion 1420. Accordingly, in this embodiment, the electrodes of the second substrate 1200 having the second connection portion 1420 thereon may include protrusions to ensure alignment accuracy, diffusion force, and diffusion prevention capability, which prevents intermetallic compounds (IMCs) formed between the conductive adhesive (e.g., solder) and the protrusion from diffusing into the interposer and / or substrate.

[0168] In addition, further reference Figure 16 The semiconductor package of the second embodiment may further include a connecting member 1210.

[0169] The connection member 1210 may be referred to as a bridging substrate. For example, the connection member 1210 may include a redistribution layer. The connection member 1210 may be used to horizontally electrically connect multiple semiconductor elements to each other. For example, since the area required for semiconductor elements is often too large, the connection member 1210 may include a redistribution layer. Because the circuit patterns of semiconductor packages and semiconductor elements differ greatly in width and length, a buffering function for the circuit patterns used for electrical connections may be required. This buffering function refers to providing an intermediate dimension between the dimensions (such as width or length) of the circuit pattern of the semiconductor package and the dimensions (such as width or length) of the circuit pattern of the semiconductor element, and the redistribution layer may include the functionality to perform this buffering function.

[0170] In this embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may contain organic materials. For example, the connecting member 1210 may include an organic substrate containing organic materials instead of a silicon substrate. The connecting member 1210 may be embedded in the second substrate 1200.

[0171] Therefore, the second substrate 1200 may include a cavity, and the connecting member 1210 may be disposed in the cavity of the second substrate 1200. The connecting member 1210 can horizontally connect a plurality of semiconductor elements disposed on the second substrate 1200 to each other.

[0172] Reference Figure 17 The semiconductor package of the third embodiment may include a second substrate 1200 and a semiconductor element 1300. In this case, compared with the semiconductor package of the first embodiment, the semiconductor package of the third embodiment may have a structure that omits the first substrate 1100.

[0173] In other words, the second substrate 1200 of the second embodiment can be used as an intermediary layer and also as a packaging substrate.

[0174] The first connecting portion 1410 provided on the lower surface of the second substrate 1200 can connect the second substrate 1200 to the motherboard of an electronic device.

[0175] Reference Figure 18 The semiconductor package of the fourth embodiment may include a first substrate 1100 and a semiconductor element 1300.

[0176] In this case, the semiconductor package of the fourth embodiment may have a structure that omits the second substrate 1200 compared to the semiconductor package of the first embodiment.

[0177] In other words, the first substrate 1100 of the third embodiment can be used as a packaging substrate, and also as a connector between the semiconductor element 1300 and the motherboard. For this purpose, the first substrate 1100 may include a connecting member 1110 for connecting multiple semiconductor elements to each other. The connecting member 1110 may be an organic bridge for connecting multiple semiconductor elements to each other.

[0178] Reference Figure 19 Compared to the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment may further include a third semiconductor element 1330. For this purpose, a fourth connection portion may also be provided on one surface of the first substrate 1100.

[0179] Therefore, the semiconductor package of the fifth embodiment can have a structure in which semiconductor elements are mounted on the upper and lower sides. In this case, the third semiconductor element 1330 can have a configuration where... Figure 16 The structure on the lower surface of the second substrate 1200 in the semiconductor package.

[0180] Furthermore, the connecting member 1110 can be embedded in the first substrate 1100. The connecting member 1110 can horizontally connect the first semiconductor element 1310 and the second semiconductor element 1320.

[0181] Furthermore, the first substrate 1100 may include a conductive bonding portion 1450. The conductive bonding portion 1450 may protrude from the first substrate 1100 toward the second semiconductor element 1320. The conductive bonding portion 1450 may be referred to as a bump or a pillar. The conductive bonding portion 1450 may be configured to have a protruding structure on an electrode disposed on the uppermost side of the first substrate 1100.

[0182] The third semiconductor element 1330 may be disposed on the conductive connection portion 1450. In this case, the third semiconductor element 1330 can be connected to the first substrate 1100 through the conductive connection portion 1450. Furthermore, the second connection portion 1420 may be disposed between the first semiconductor element 1310, the second semiconductor element 1320, and the third semiconductor element 1330.

[0183] Therefore, the third semiconductor element 1330 can be electrically connected to the first semiconductor element 1310 and the second semiconductor element 1320 through the second connection portion 1420.

[0184] In other words, the third semiconductor element 1330 can be connected to the first substrate 1100 through the conductive connection portion 1450, and connected to the first semiconductor element 1310 and the second semiconductor element 1320 through the second connection portion 1420.

[0185] In this configuration, the third semiconductor element 1330 can receive electrical signals and / or power through the conductive connection portion 1450. Furthermore, the third semiconductor element 1330 can transmit and receive communication signals with the first semiconductor element 1310 and the second semiconductor element 1320 through the second connection portion 1420.

[0186] The semiconductor package of the fifth embodiment can supply electrical signals and / or power to the third semiconductor element 1330 via the conductive junction 1450, thereby providing sufficient power to drive the third semiconductor element 1330 or smoothly controlling the power operation.

[0187] Therefore, this embodiment can improve the driving characteristics of the third semiconductor element 1330. That is, this embodiment can solve the problem of insufficient power supplied to the third semiconductor element 1330. Furthermore, this embodiment provides at least one of a power signal, a power signal, and a communication signal to the third semiconductor element 1330 via different paths via the conductive junction 1450 and the second connection 1420. Therefore, this embodiment can solve the problem of communication signal loss caused by the power signal. For example, this embodiment can minimize the mutual interference between the power signal and the communication signal.

[0188] On the other hand, the third semiconductor element 1330 in the fifth embodiment may have a package-on-package (POP) structure, wherein multiple package substrates are stacked and disposed on the first substrate 1100. For example, the third semiconductor element 1330 may be a memory package including a memory chip. Furthermore, the memory package may be coupled to the conductive bonding portion 1450. In this case, the memory package may not be connected to the first semiconductor element 1310 and the second semiconductor element 1320.

[0189] In addition, Figure 15 In the modified example, the semiconductor package may include a first substrate 1100 and a first semiconductor element 1310 and a second semiconductor element 1320 disposed on the first substrate 1100. Furthermore, the semiconductor package may include a first connection portion 1410 disposed between the first substrate 1100 and the first semiconductor element 1310 and the second semiconductor element 1320. That is, the semiconductor package may have a portion 1410 that omits... Figure 15 The structure of the second substrate and the second connecting part.

[0190] On the other hand, when a circuit board having the features of the present invention described above is used in information technology (IT) devices or home appliances such as smartphones, servers, or televisions (TVs), it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants and solve problems such as leakage current or short circuits between terminals, or open circuits at terminals supplying power to the semiconductor chip. Furthermore, when the circuit board performs a signal transmission function, it can solve noise problems. Therefore, a circuit board having the features of the present invention described above can maintain stable functionality in IT devices or home appliances, thereby enabling functional integrity or technical interoperability between the entire product and the circuit board to which the present invention is applied.

[0191] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, the circuit board can solve the problem of signal distortion transmitted to the transportation device, or safely protect the semiconductor chip controlling the transportation device from external influences, and further improve the stability of the transportation device by solving the problems of leakage current or electrical short circuit between terminals or electrical open circuit at the terminals supplying power to the semiconductor chip. Therefore, functional integrity or technical interoperability can be achieved between the transportation device and the circuit board to which the present invention is applied.

[0192] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, but are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., exemplified in each embodiment can be combined or modified by those skilled in the art and implemented in other embodiments. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0193] While the above description focuses on embodiments, it is merely illustrative and does not limit the scope of the embodiments. Furthermore, those skilled in the art will recognize that various modifications and applications, not illustrated above, can be made without departing from the essential characteristics of the embodiments. For example, various components specifically shown in the embodiments can be modified and implemented. Moreover, differences associated with these modifications and applications should be interpreted as including within the scope of the embodiments as defined in the appended claims.

Claims

1. A circuit board, comprising: First insulating layer; A first circuit pattern layer is disposed on at least one of the upper and lower surfaces of the first insulating layer; A second insulating layer covers the first circuit pattern layer; as well as A first intermediate layer is disposed between the first circuit pattern layer and the second insulating layer. When the first intermediate layer on the first circuit pattern layer is irradiated with primary ions, it emits secondary ions containing at least one of hydrogen (H), nitrogen (N), oxygen (O), and sulfur (S). In the secondary ions, C3N3Cu2 - Its strength is greater than that of C2N2Cu - The intensity.

2. The circuit board according to claim 1, wherein, In the secondary ions, CN - Its strength is greater than that of C4H2O - The intensity.

3. The circuit board according to claim 1, wherein, In the secondary ions, C4H2O - Its strength is greater than that of C3N3Cu2 - The intensity.

4. The circuit board according to claim 1, wherein, In the secondary ions, C2N2Cu - The strength is greater than C 12 H 11 O4 - The intensity.

5. The circuit board according to claim 1, comprising a first electrode layer having the first circuit pattern layer and a first through electrode passing through the first insulating layer and in contact with the first circuit pattern layer.

6. The circuit board according to claim 5, wherein, The first circuit pattern layer includes a first surface that contacts the first insulating layer and a second surface that contacts the second insulating layer and faces the first surface.

7. The circuit board according to claim 6, wherein, The second surface has an uneven structure.

8. The circuit board according to claim 6, wherein, The first intermediate layer is disposed on at least a portion of the second surface.

9. The circuit board according to claim 6, wherein, The first through electrode is in contact with the first surface.

10. The circuit board according to claim 1, comprising: A second circuit pattern layer is disposed on at least one of the upper and lower surfaces of the second insulating layer; A third insulating layer covers the second circuit pattern layer; as well as The second intermediate layer is disposed between the second circuit pattern layer and the third insulating layer.

Images