Optoelectronic modulator and method of manufacturing the same, optoelectronic modulation system

Abstract

The application discloses an optoelectronic modulator and a preparation method and an optoelectronic modulation system thereof, and relates to the technical field of optoelectronic devices. The semiconductor structure comprises a waveguide layer, a plurality of electrodes, a planarization layer and a first substrate. The waveguide layer is provided with an identification mark on one side surface. The electrodes are arranged on the surface of the waveguide layer; and the identification mark is configured to realize the position alignment of the waveguide layer and the electrodes. The planarization layer is arranged on the side of the waveguide layer provided with the identification mark; and the surface of the planarization layer away from the waveguide layer is arranged in a planarization mode. The first substrate is arranged on the side of the planarization layer away from the waveguide layer and is bonded to the planarization layer; and the dielectric constant of the first substrate is less than 5. When the optoelectronic modulator is prepared, the first substrate with a low dielectric constant is arranged on the front surface of the waveguide layer, so that the silicon substrate with a high dielectric constant on the back surface can be thinned or removed based on the support of the first substrate, thereby improving the photoelectric response bandwidth of the device and the reliability of the structure while reducing the preparation difficulty.

Description

Technical Field

[0001] This application belongs to the field of optoelectronic equipment technology, specifically relating to an optoelectronic modulator and its preparation method, and an optoelectronic modulation system. Background Technology

[0002] With the development of intelligent driving, artificial intelligence, high-definition video streaming, and cloud services, the amount of data requiring transmission and processing is increasing. Currently, mainstream central processing units (CPUs) cannot process optical signals; they are designed for processing electrical signals. However, the transmission loss of optical signals, especially over long distances, is far lower than that of electrical signals. This makes the conversion between electro-optical signals a crucial step in data transmission, leading to the development of optoelectronic modulators.

[0003] Current optoelectronic modulators, especially those made of thin-film lithium niobate or lithium tantalate, have achieved ultra-high bandwidth (>100 GHz) electro-optic modulation due to their superior electro-optic effect, wide transparency window, and low optical loss. Currently, silicon substrates are typically used to fabricate optoelectronic modulators so that their fabrication process can be matched with that of metal-oxide-semiconductor (MOSFET) devices.

[0004] However, the high dielectric constant of silicon substrates affects the further improvement of the bandwidth of optoelectronic modulators. For example, in traveling wave electrode modulators, in order to obtain the maximum bandwidth, it is necessary to achieve a good match between the microwave effective refractive index (nanometer) and the optical wavegroup refractive index (ng≈2.2). However, the presence of silicon substrates will significantly increase the microwave effective refractive index, resulting in phase mismatch between the two and severely limiting the response bandwidth of optoelectronic modulators. Summary of the Invention

[0005] This application provides an optoelectronic modulator and its fabrication method, as well as an optoelectronic modulation system. The aim is to fabricate an optoelectronic modulator with high bandwidth and good reliability with low fabrication difficulty by setting a substrate with a low dielectric constant on the front side of the device.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide an optoelectronic modulator, which includes a waveguide layer, electrodes, a planarization layer, and a first substrate.

[0007] An identification mark is provided on one side surface of the waveguide layer. Electrodes are disposed on the surface of the waveguide layer; the identification mark is configured to align the waveguide layer and the electrodes. A planarization layer is located on the side of the waveguide layer with the identification mark; the surface of the planarization layer away from the waveguide layer is planarized. A first substrate is disposed on the side of the planarization layer away from the waveguide layer and is bonded to the planarization layer; wherein the dielectric constant of the first substrate is less than 5.

[0008] In the optoelectronic modulator provided in this application embodiment, by setting a first substrate on the front side of the optoelectronic modulator, it is convenient to use the first substrate as a base to reduce or even remove the silicon substrate located on the back side of the device, which is relied upon when fabricating key structures such as the waveguide layer of the optoelectronic modulator. This solves the problem of mismatch between the effective refractive index of microwaves and the refractive index of optical wave groups caused by the silicon substrate, thereby improving the bandwidth of the optoelectronic modulator. At the same time, the newly added first substrate located on the front side of the device has a low dielectric constant (at least below 5). While providing better mechanical support and ensuring structural reliability for subsequent fabrication steps and long-term use of the optoelectronic modulator, the low dielectric constant also avoids increasing the effective refractive index of microwaves and avoids limiting the bandwidth of the optoelectronic modulator. That is, the optoelectronic modulator provided in this application embodiment can achieve a balance between structural reliability and bandwidth performance, which is conducive to the further industrialization of optoelectronic modulators.

[0009] Furthermore, the first substrate is bonded to the planarization layer, and the bonding connection is a conventional fabrication process in the field of semiconductor devices, especially in the field of MOSFETs. That is, the optoelectronic modulator provided in this application embodiment is also compatible with the fabrication process of MOSFETs, which is conducive to achieving large-scale integration. At the same time, this bonding process does not require a high-precision etching process. Compared with the solution of hollowing out the silicon substrate, the fabrication difficulty of the optoelectronic modulator provided in this application embodiment is lower, which is conducive to improving the fabrication efficiency and product yield.

[0010] Meanwhile, the first substrate is connected to the key structure (including the waveguide layer and electrodes) through a planarization layer, which facilitates the use of the planarization layer to eliminate the difference in thermal expansion coefficients between the first substrate and the key structure. This avoids defects such as peeling and warping of the first substrate relative to the key structure in subsequent process steps, such as thinning or removing the second substrate, thereby further improving the structural reliability and product yield of the optoelectronic modulator.

[0011] In some embodiments, the dielectric constant of the first substrate is less than or equal to 3.8.

[0012] In some embodiments, the material of the first substrate includes one or more of quartz, sapphire, and diamond.

[0013] In some embodiments, the material of the planarization layer includes one or more of a polymer and silicon oxide.

[0014] In some embodiments, the dielectric constant of the planarization layer is less than 5.

[0015] In some embodiments, the elasticity of the planarization layer is greater than that of the first substrate.

[0016] In some embodiments, the waveguide layer is made of one or more of lithium niobate, lithium tantalate, barium titanate, and lead zirconate titanate.

[0017] In some embodiments, the optoelectronic modulator further includes a protective layer located between the waveguide layer and the planarization layer; wherein the refractive index of the protective layer is less than that of the waveguide layer.

[0018] In some embodiments, the optoelectronic modulator further includes a second substrate located on the side of the waveguide layer away from the first substrate; the dielectric constant of the first substrate is less than that of the second substrate, and the thickness of the first substrate is greater than that of the second substrate.

[0019] In some embodiments, the thickness of the second substrate is 0 μm to 200 μm.

[0020] In some embodiments, the difference in the coefficients of thermal expansion between the first substrate and the waveguide layer is smaller than the difference in the coefficients of thermal expansion between the second substrate and the waveguide layer.

[0021] In some embodiments, the coefficient of thermal expansion of the first substrate is smaller than that of the second substrate.

[0022] In some embodiments, the photoelectric modulator further includes a contact structure located on the side of the electrode away from the first substrate, and the contact structure is electrically connected to the electrode.

[0023] In a second aspect, a photoelectric modulation system is provided, comprising a light-emitting structure and a photoelectric modulator provided in any embodiment of the first aspect. The light-emitting structure is configured to generate an optical signal and transmit the optical signal to the photoelectric modulator.

[0024] The technical effects brought about by the structural design of the optoelectronic modulation system in the second aspect can be referred to the technical effects brought about by the optoelectronic modulator in any embodiment of the first aspect, and will not be repeated here.

[0025] Thirdly, a method for fabricating a photoelectric modulator is provided, the method comprising: A waveguide layer and electrodes are formed on a second substrate; an identification mark is provided on the surface of the waveguide layer away from the second substrate; electrodes are disposed on the surface of the waveguide layer; the identification mark is configured to achieve positional alignment of the waveguide layer and electrodes. A planarization layer is formed on the side of the waveguide layer away from the second substrate; the surface of the planarization layer away from the waveguide layer is planarized. A first substrate is formed on the side of the planarization layer away from the waveguide layer; the first substrate is bonded to the planarization layer; wherein the dielectric constant of the first substrate is less than 5. At least a portion of the second substrate away from the first substrate is removed to reduce the thickness of the second substrate to a target thickness.

[0026] In the method for fabricating an optoelectronic modulator provided in this application embodiment, a second substrate with a high dielectric constant is used to fabricate key structures such as waveguide layers and electrodes, thereby obtaining key structures with high performance. Subsequently, the device is inverted to form a first substrate with a low dielectric constant as a support substrate. The second substrate with a high dielectric constant is thinned or even removed, so that the silicon substrate (i.e., the second substrate) can be used to fabricate key structures such as waveguide layers. This fabrication process is compatible with MOSFET fabrication processes, which is beneficial for achieving large-scale integration. At the same time, after the key structure is fabricated, the first substrate with a low dielectric constant is formed by inverting it on the front side of the device, thereby replacing the support function of the second substrate. Even if the second substrate is thinned or removed, it does not affect the structural reliability of the device. At the same time, it can also solve the problem of bandwidth limitation caused by the high dielectric constant second substrate.

[0027] This preparation method only requires large-area thinning of the second substrate, without the need for high-precision etching, making the preparation less difficult and improving preparation efficiency and product yield.

[0028] In some embodiments, the material of the planarization layer includes resin, wherein forming the planarization layer on the side of the waveguide layer away from the second substrate includes: spin-coating the resin material on the side of the waveguide layer away from the second substrate to form the planarization layer.

[0029] In some embodiments, forming a first substrate on the side of the planarization layer away from the waveguide layer includes: The target surface of the first substrate is pretreated; the pretreatment includes one or more of planarization, cleaning, and activation treatments. The orientations of the planarization layer and the second substrate are interchanged, and the planarization layer is bonded to the target surface.

[0030] In some embodiments, removing the portion of the second substrate that is away from the first substrate to reduce the thickness of the second substrate to a target thickness includes: removing the portion of the second substrate that is away from the first substrate to reduce the thickness of the second substrate to 0 μm to 200 μm.

[0031] In some embodiments, before forming a planarization layer on the side of the waveguide layer away from the second substrate, the fabrication method further includes: forming a protective layer on the side of the waveguide layer away from the second substrate; the planarization layer is located on the side of the protective layer away from the second substrate; wherein the refractive index of the protective layer is less than the refractive index of the waveguide layer.

[0032] In some embodiments, the fabrication method further includes: forming a through-hole on the surface of the second substrate away from the first substrate; the through-hole at least penetrates the second substrate and exposes an electrode. A conductive material is filled into the through-hole to form a contact structure; the contact structure is electrically connected to the electrode. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0034] Figure 1 A cross-sectional view of an optoelectronic modulator provided in an embodiment of this application; Figure 2 Another cross-sectional view of the photoelectric modulator provided in the embodiments of this application; Figure 3 This is a flowchart illustrating the fabrication process of the optoelectronic modulator provided in an embodiment of this application. Figures 4-11 Cross-sectional views corresponding to each fabrication step of the optoelectronic modulator provided in the embodiments of this application; Figure 12 This is a schematic diagram of a photoelectric modulation system provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0036] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the aforementioned particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0038] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0039] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0040] This application provides an optoelectronic modulator 100. Figure 1 This is a cross-sectional view of the optoelectronic modulator 100 provided in an embodiment of this application.

[0041] In some embodiments, see Figure 1The optoelectronic modulator 100 includes a waveguide layer 1, an electrode 2, a planarization layer 3, and a first substrate 4.

[0042] Among them, the waveguide layer 1 serves as the core structure of the optoelectronic modulator 100, which is used to achieve low-loss confinement and transmission of optical signals. For example, it can guide the optical signal to a region that can interact with the electric field generated by the electrode 2 in order to achieve electro-optic modulation.

[0043] For example, the material of the waveguide layer 1 may include one or more of lithium niobate, lithium tantalate, barium titanate, and lead zirconate titanate (PZT) to enable the manufactured optoelectronic modulator 100 to have a high optoelectronic response bandwidth.

[0044] Alternatively, by way of example, the material of the waveguide layer 1 may also include other materials that may enable optoelectronic modulation, such as barium titanate or aluminum nitride. The materials can be flexibly selected for specific application scenarios, and the embodiments of this application do not impose any restrictions on this.

[0045] For example, see Figure 1 The waveguide layer 1 may include a planar layer 11 and a ridge waveguide 12. The ridge waveguide 12 may have a high refractive index. The waveguide layer 1 with the ridge waveguide 12 can effectively balance optical confinement and transmission loss.

[0046] For example, the refractive index, width and depth (i.e., the height of the ridge) of the ridge waveguide 12 can be flexibly set according to requirements or application scenarios, and the embodiments of this application do not limit this.

[0047] For example, in addition to the ridge structure (including the planar layer 11 and the ridge waveguide 12), the waveguide layer 1 may also include other structural designs. This application embodiment does not limit this. For example, it may also be a photonic crystal waveguide, a planar waveguide, a loaded strip waveguide, a channel waveguide, a slot waveguide, or a hybrid plasma waveguide, etc.

[0048] One side surface of the waveguide layer 1 is provided with an identification mark, for example, using Figure 1 Taking the orientation as an example, the identification mark can be set on the lower surface of waveguide layer 1 (not shown in the figure).

[0049] It is understandable that the side of waveguide layer 1 with the identification mark is the front side of photoelectric modulator 100. The front side of photoelectric modulator 100 refers to the side that is processed and operated by key photolithography, deposition, etching and other processes during the fabrication of photoelectric modulator 100. For example, the fabrication of waveguide layer 1 or electrode 2 is achieved by processing or operating on the front side of photoelectric modulator 100.

[0050] For example, the identification mark can be a physical mark or a special mark that can be distinguished from the surrounding structure and can be identified by humans or acquisition devices such as cameras. During the preparation process, such as region division, photolithography patterning, structure alignment, and positioning of process steps, the identification mark can be used as a reference to achieve high-precision alignment.

[0051] For example, the identification mark is configured at least to achieve the positional alignment of waveguide layer 1 and electrode 2, wherein the alignment process of waveguide layer 1 and electrode 2 is a front-side operation process, that is, the identification mark is limited to a mark used when performing front-side process operations.

[0052] It is understood that the identification mark can be reused or additional marks can be set to achieve alignment of the back structure when performing back operation processes. This application does not limit the related representation or operation processes of the back.

[0053] See Figure 1 Electrode 2 is disposed on the surface of waveguide layer 1.

[0054] The electrode 2 is used to apply an electric field around the waveguide of the waveguide layer 1, thereby modulating the optical signal by utilizing the change in the electric field.

[0055] For example, see Figure 1 The electrode 2 can be disposed on both sides of the ridge waveguide 12 along a direction parallel to the planar layer 11, so as to realize photoelectric modulation in the lateral direction.

[0056] Alternatively, in other embodiments, the electrode 2 may also be positioned longitudinally along the waveguide (e.g., ridge waveguide 12), for example, as... Figure 1 Taking the orientation as an example, electrode 2 can be set above or below the ridge waveguide 12. This application embodiment does not limit the setting position of electrode 2.

[0057] For example, the “position alignment” in the aforementioned use of identification marks to achieve the position alignment of waveguide layer 1 and electrode 2 can be understood as making the relative positional relationship between electrode 2 and waveguide (e.g., ridge waveguide) conform to the expected design in order to improve the modulation accuracy of the optoelectronic modulator.

[0058] For example, see Figure 1 The photoelectric modulator 100 may include a plurality of electrodes 2.

[0059] For example, see Figure 1The multiple electrodes 2 can all be disposed on the side surface of the waveguide layer 1 with the identification mark (i.e., disposed on the front side), or the multiple electrodes 2 can all be disposed on the side surface of the waveguide layer 1 away from the identification mark (i.e., disposed on the back side), or the multiple electrodes 2 can also be disposed separately on the side surface of the waveguide layer 1 with the identification mark and the side surface away from the identification mark. All of these different distribution methods of the electrodes 2 can achieve modulation of the optical signal in the waveguide layer 1.

[0060] For example, the structure of electrode 2 can be designed as a traveling wave electrode, which makes it possible for the photoelectric modulator 100 to load a high-frequency electrical signal to achieve optical wave modulation.

[0061] For example, the material of the electrode 2 may include a metallic material, such as titanium or gold.

[0062] The planarization layer 3 is located on the side of the waveguide layer 1 with the identification mark, that is, the planarization layer 3 is disposed on the front side. The surface of the planarization layer 3 away from the waveguide layer 1 (i.e. the front side) is planarized, that is, the surface of the planarization layer 3 away from the waveguide layer 1 is a flat surface without structural undulations. For example, its flatness and roughness meet the requirements of bonding connection for the degree of planarization.

[0063] See Figure 1 The first substrate 4 is disposed on the side of the planarization layer 3 away from the waveguide layer 1, that is, the first substrate 4 is disposed on the front side of the optoelectronic modulator 100.

[0064] The first substrate 4 is bonded to the planarization layer 3, wherein the dielectric constant of the first substrate 4 is less than 1.7.

[0065] It is understood that the embodiments of this application do not limit the specific bonding method of the bonding connection.

[0066] In some other embodiments, to ensure compatibility with mature MOSFET fabrication processes (such as CMOS fabrication processes) and achieve large-scale integration, optoelectronic modulators are typically fabricated using silicon substrates. For example, lithium niobate-on-insulator (LNI) wafers or lithium tantalate wafers are fabricated on a silicon substrate, i.e., waveguide layers are placed on the back side of the silicon substrate. However, the high dielectric constant of the silicon substrate (εr≈11.7) limits further bandwidth increases. For example, in optoelectronic modulators made with traveling wave electrodes, the high dielectric constant of the silicon substrate increases the effective refractive index of microwaves (e.g., 3.5~4.0), resulting in a decrease in the phase velocity of microwaves. In waveguides, especially in thin-film lithium niobate or lithium carbonate waveguides, the optical group refractive index is low (e.g., 2.2). This mismatch between the effective refractive index of microwaves and the optical group refractive index leads to an accumulated phase difference between microwaves and light waves during propagation, causing the optoelectronic interaction efficiency to decay rapidly with increasing frequency, thus lowering the bandwidth limit.

[0067] In other embodiments, a "hollowed-out silicon substrate" approach is used, that is, etching is performed on the back side of the silicon substrate (the side surface away from the waveguide layer) to completely remove the portion of the silicon substrate below the electrodes. This allows the microwaves to be mainly distributed in air or silicon oxide with low dielectric constant, thereby reducing or avoiding the problem of mismatch between the effective refractive index of the microwaves and the refractive index of the optical wavegroup. However, after hollowing out part of the silicon substrate, the mechanical strength of the optoelectronic modulator decreases. The waveguide layer suspended due to the hollowing out of the silicon substrate is easily damaged during subsequent packaging or long-term use, which seriously affects the reliability and lifespan of the device. Furthermore, when performing deep etching to hollow out the back side of the silicon substrate, the etching precision requirements are high, the fabrication is difficult, the yield is low, and the cost is high, which is not conducive to large-scale industrial production.

[0068] In addition, in the two other embodiments mentioned above, the material of the waveguide layer (e.g., thin-film lithium niobate or lithium tantalate) has a large difference in the coefficient of thermal expansion with respect to the silicon substrate. This results in significant stress between the silicon substrate and the waveguide layer when the ambient temperature changes, which further affects the reliability of the device.

[0069] In the optoelectronic modulator 100 provided in this application embodiment, by setting a first substrate 4 on the front side of the optoelectronic modulator 100, it is convenient to use the first substrate 4 as a substrate to reduce or even remove the silicon substrate located on the back side of the device, which is relied upon when fabricating key structures such as the waveguide layer 1 of the optoelectronic modulator 100. This solves the problem of mismatch between microwave effective refractive index and optical wavegroup refractive index caused by the silicon substrate, and improves the bandwidth of the optoelectronic modulator 100. At the same time, the newly added first substrate 4 located on the front side of the device has a low dielectric constant (at least below 5). While providing better mechanical support and ensuring structural reliability for subsequent fabrication steps and long-term use of the optoelectronic modulator 100, the low dielectric constant also avoids increasing the microwave effective refractive index and avoids limiting the bandwidth of the optoelectronic modulator 100. That is, the optoelectronic modulator 100 provided in this application embodiment can achieve a balance between structural reliability and bandwidth performance, which is conducive to the further industrial development of the optoelectronic modulator 100.

[0070] Furthermore, the first substrate 4 is bonded to the planarization layer 3. This bonding connection is a conventional fabrication process in the field of semiconductor devices, especially MOSFETs. In other words, the optoelectronic modulator 100 provided in this embodiment is also compatible with the fabrication process of MOSFETs, which is beneficial for achieving large-scale integration. At the same time, this bonding process does not require a high-precision etching process. Compared with the solution of hollowing out the silicon substrate, the fabrication difficulty of the optoelectronic modulator 100 provided in this embodiment is lower, which is beneficial for improving fabrication efficiency and product yield.

[0071] Meanwhile, the first substrate 4 is connected to the key structure (including waveguide layer 1 and electrode 2) through the planarization layer 3, which facilitates the use of the planarization layer 3 to resolve the difference in thermal expansion coefficient between the first substrate 4 and the key structure, thereby avoiding defects such as peeling and warping of the first substrate 4 relative to the key structure, and further improving the structural reliability and product yield of the optoelectronic modulator 100.

[0072] In some embodiments, the dielectric constant of the first substrate 4 is less than or equal to 3.8, thereby ensuring that the first substrate 4 has a limited effect on the effective refractive index of microwaves and effectively improving the bandwidth limit of the optoelectronic modulator 100.

[0073] In some embodiments, the material of the first substrate 4 includes one or more of quartz, sapphire, and diamond, thereby ensuring that the first substrate 4 has a low dielectric constant and good mechanical support, while taking into account the bandwidth and structural reliability requirements of the optoelectronic modulator 100.

[0074] In some embodiments, the material of the planarization layer 3 includes one or more of polymers and silicon oxide. For example, the planarization layer 3 can be a resin. These material types can ensure that the planarization layer 3 can be bonded to the first substrate 4 while being designed to have good thermal expansion coefficient difference mitigation performance, so as to solve the problem of reduced structural reliability caused by the difference in thermal expansion coefficient between the first substrate 4 and key structures such as the waveguide layer 1.

[0075] For example, the elasticity of the planarization layer 3 is greater than that of the first substrate 4, thereby using the elastic buffering effect to dissipate the stress caused by the difference in thermal expansion coefficients between the first substrate 4 and key structures such as the waveguide layer 1, thereby improving the structural reliability of the optoelectronic modulator 100.

[0076] For example, the dielectric constant of the planarization layer 3 is less than 5. For instance, the dielectric constant of the planarization layer 3 can be less than 3.8. This allows the planarization layer 3 to achieve bonding connection with the first substrate 1 and to relieve stress caused by the difference in thermal expansion coefficients, while also avoiding the introduction of a high dielectric constant. This further ensures that the optoelectronic modulator 100 has a high bandwidth limit.

[0077] In some embodiments, see Figure 1 The optoelectronic modulator 100 also includes a protective layer 5, which is located between the waveguide layer 1 and the planarization layer 3, wherein the refractive index of the protective layer 5 is less than the refractive index of the waveguide layer 1.

[0078] By placing a low-refractive-index protective layer 5 between the planarization layer 3 and the waveguide layer 1, the optical signal can be strictly confined within the waveguide layer 1, avoiding excessive loss during photoelectric modulation and thus improving the modulation effect of the photoelectric modulator 100.

[0079] For example, see Figure 1 When the electrode 2 is positioned on the front side, the protective layer 5 also covers the surface of the waveguide layer 1 and the surface of the electrode 2, thereby providing physical protection for the waveguide layer 1 and the electrode 2 and preventing damage to key structures such as the waveguide layer 1 and the electrode 2 caused by the subsequent fabrication of the planarization layer 3 and the first substrate 4.

[0080] Figure 2 Another cross-sectional view of the optoelectronic modulator 100 provided in an embodiment of this application.

[0081] In some embodiments, see Figure 2 The optoelectronic modulator 100 may further include a second substrate 6, which is located on the side of the waveguide layer 1 away from the first substrate 4. The dielectric constant of the first substrate 4 is less than that of the second substrate 6, and the thickness of the first substrate 4 is greater than that of the second substrate 6.

[0082] For example, the thickness of the second substrate 6 is 0 μm to 200 μm, for example, it can be 0 μm (see...). Figure 1 ), 13.5μm, 143.25μm or 200μm.

[0083] For example, the material of the first substrate 4 may include silicon, that is, the first substrate 4 may be a thin silicon substrate.

[0084] That is, in this embodiment, a substrate with a high dielectric constant but a thin thickness can be retained on the back side of the optoelectronic modulator 100 so that, under the control of this thickness, the influence of the second substrate 6 on the bandwidth limit of the optoelectronic modulator 100 can be limited to an acceptable range. At the same time, the second substrate 6 can be used in conjunction with the first substrate 4 to improve the mechanical properties of the optoelectronic modulator 100, thereby further improving the structural reliability and product yield of the optoelectronic modulator 100.

[0085] For example, the difference in thermal expansion coefficients between the first substrate 4 and the waveguide layer 1 is smaller than the difference in thermal expansion coefficients between the second substrate 6 and the waveguide layer 1. That is, in addition to using the planarization layer 3 to resolve the stress problem caused by the difference in thermal expansion coefficients, the difference in thermal expansion coefficients between the thicker and lower dielectric constant first substrate 4 and the waveguide layer 1 can be reduced (at least smaller than the difference in thermal expansion coefficients between the second substrate 6 and the waveguide layer 1), thereby further reducing the stress problem caused by the difference in thermal expansion coefficients and improving the structural reliability and product yield of the optoelectronic modulator 100.

[0086] For example, by ensuring that the coefficient of thermal expansion of the first substrate 4 is less than that of the second substrate 6, the deformation of the first substrate 4 during temperature changes can be reduced, thereby reducing defects caused by thermal expansion and improving the structural reliability and product yield of the optoelectronic modulator 100.

[0087] In some embodiments, see Figure 1 and Figure 2 The photoelectric modulator 100 may also include a contact structure 7, which is located on the side of the electrode 2 away from the first substrate 4 and is electrically connected to the electrode 2.

[0088] That is, the contact structure 7 used to realize the external connection of electrode 2 can be set on the back side of the photoelectric modulator 100 so as to realize the external connection of electrode 2 without affecting the relatively precise optical structure design on the front side, thereby improving the modulation accuracy of photoelectric modulator 100. In addition, in this embodiment, the first substrate 4 is located on the front side, while the contact structure 7 is set on the back side, which can avoid making deep holes in the first substrate 7 or other structures, thus realizing the external connection of electrode 2, and the overall fabrication difficulty is low.

[0089] For example, see Figure 1 In the case where the optoelectronic modulator 100 does not include the second substrate 6 and the electrode 2 is disposed on the front side, the contact structure 7 extends at least through the waveguide layer 1 so as to be electrically connected to the electrode 2.

[0090] For example, see Figure 2 In the case where the optoelectronic modulator 100 also includes a second substrate 6, the contact structure 7 also penetrates the second substrate 6 to be electrically connected to the electrode 2. The second substrate 6 is thin, so there is no need to perform deep hole etching with a high aspect ratio.

[0091] For example, see 1 and Figure 2 The optoelectronic modulator 100 may also include a buried oxide layer 8, which is disposed on the surface of the waveguide layer 1 away from the first substrate 4, so as to provide physical protection for the waveguide layer 1 and to confine the optical signal within the waveguide layer 1. That is, the refractive index of the buried oxide layer 8 may also be less than the refractive index of the waveguide layer 1.

[0092] For example, the buried oxide layer 8 and the protective layer 5 can be made of the same material, such as silicon oxide.

[0093] For example, see 1 and Figure 2 In the case where the photoelectric modulator 100 also includes a buried oxide layer 8, the contact structure 7 also penetrates the buried oxide layer 8 in order to be electrically connected to the electrode 2.

[0094] This application also provides a method for fabricating a photoelectric modulator 100. Figure 3This is a flowchart illustrating the fabrication process of the photoelectric modulator 100 provided in an embodiment of this application. Figures 4-11 These are cross-sectional views corresponding to each preparation step.

[0095] See Figure 3 The preparation method includes: S1: See Figure 4 Waveguide layer 1 and electrode 2 are formed on the second substrate 6.

[0096] In this design, an identification mark is provided on the surface of the waveguide layer 1 away from the second substrate 6, and the electrode 2 is disposed on the surface of the waveguide layer 1. The identification mark is configured to achieve the alignment of the waveguide layer 1 and the electrode 2.

[0097] For example, the electrode 2 can be located on the side surface of the waveguide layer 1 with the identification mark, and / or on the side surface of the waveguide layer 1 away from the identification mark. For example, the electrode 2 can be formed on the second substrate 6 first, and then the waveguide layer 1 can be laid at the position corresponding to the electrode 2 using the identification mark. Alternatively, the waveguide layer 1 can be formed first, and then the electrode 2 can be set at the target position of the waveguide layer 1 using the identification mark to achieve position alignment between the two.

[0098] For example, see Figure 5 Before step S2, the preparation method further includes: S12: A protective layer 5 is formed on the side of the waveguide layer 1 away from the second substrate 6, and the refractive index of the protective layer 5 is less than that of the waveguide layer 1.

[0099] S2: See Figure 6 A planarization layer 3 is formed on the side of waveguide layer 1 away from the second substrate 6.

[0100] See Figure 6 The planarization layer 3 is located on the side of the protective layer 5 away from the second substrate 6, and the surface of the planarization layer 3 away from the waveguide layer 1 is planarized.

[0101] For example, a silicon oxide layer can be deposited by chemical vapor deposition or magnetron sputtering, and then planarized by chemical mechanical polishing to form a planarization layer 3.

[0102] Alternatively, as an example, a silicon oxide layer can be formed first, followed by spin-coating a resin layer with a low dielectric constant onto the silicon oxide layer, and planarizing the resin layer to form a planarization layer 3, thereby providing a high-quality bonding interface.

[0103] S3: See also Figure 7 and Figure 8 A first substrate 4 is formed on the side of the planarization layer 3 away from the waveguide layer 1.

[0104] The first substrate 4 is bonded to the planarization layer 3, and the dielectric constant of the first substrate 4 is less than 1.7.

[0105] For example, step S3 includes: S31: See also Figure 7 The target surface of the first substrate 4 is pretreated.

[0106] The pretreatment includes one or more of the following: planarization, cleaning, and activation.

[0107] S32: See also Figure 8 The planarization layer 3 and the second substrate 6 are interchanged, and the planarization layer 3 is bonded to the target surface of the first substrate 4.

[0108] That is, the photoelectric modulator 100, which forms the planarization layer 3, is inverted, that is, the planarization layer 3 faces downward, which facilitates bonding connection.

[0109] For example, the bonding connection can be a bonding connection achieved by means of direct bonding or resin adhesive bonding.

[0110] S4: See also Figure 9 At least a portion of the second substrate 6 that is away from the first substrate 4 is removed so that the thickness of the second substrate 6 is reduced to the target thickness.

[0111] For example, in this step, the thickness of the second substrate 6 can be reduced to 0 μm to 200 μm.

[0112] For example, the thickness of the silicon substrate (second substrate 6) can be precisely reduced to 0μm~200μm by mechanical grinding combined with chemical mechanical polishing.

[0113] Alternatively, by way of example, the silicon substrate can be completely removed by wet etching or reactive ion etching, based on the thinning process described in the foregoing embodiments.

[0114] See Figure 9 In this step, since the optoelectronic modulator 100 is inverted and the second substrate 6 faces upward, it is convenient to perform a thinning operation on it. At this time, the first substrate 4 is located below as the substrate, which can avoid damage to key structures such as the waveguide layer 1 during the thinning process.

[0115] In the fabrication method of the optoelectronic modulator 100 provided in this application embodiment, the key structures such as the waveguide layer 1 and the electrode 2 are fabricated using a second substrate 6 with a high dielectric constant, thereby obtaining a key structure with high performance. Subsequently, the device is inverted to form a first substrate 4 with a low dielectric constant as a supporting substrate. The second substrate 6 with a high dielectric constant is thinned or even removed, so that the key structures such as the waveguide layer 1 can be fabricated using a silicon substrate (i.e., the second substrate 6). This fabrication process is compatible with the MOSFET fabrication process, which is beneficial for achieving large-scale integration. At the same time, after the key structure is fabricated, the first substrate 4 with a low dielectric constant is formed by inverting it on the front side of the device, thereby replacing the supporting function of the second substrate 6. Even if the second substrate 6 is thinned or removed, it does not affect the structural reliability of the device. At the same time, it can also solve the problem of bandwidth limitation caused by the high dielectric constant second substrate 6.

[0116] This preparation method only requires large-area thinning of the second substrate 6, without the need for high-precision etching, making the preparation less difficult and improving preparation efficiency and product yield.

[0117] In some embodiments, see Figure 10 and Figure 11 The preparation method also includes: A contact structure 7 is formed on the side of electrode 2 away from the first substrate 4, so that the contact structure 7 is electrically connected to electrode 2.

[0118] For example, when the photoelectric modulator 100 includes a second substrate 6, the fabrication method further includes: S51: See also Figure 10 A through hole H is formed on the surface of the second substrate 6 on the side away from the first substrate 4.

[0119] The via H penetrates at least through the second substrate 6, and the via H exposes the electrode 2.

[0120] For example, the via location can be defined by photolithography, and vertical vias can be etched using deep reactive ion etching or reactive ion etching techniques until the electrode 2 is exposed.

[0121] For example, before step S52, the method further includes: forming an insulating layer 9 on the inner wall of the through hole H to prevent the subsequently formed contact structure 7 from affecting key structures such as the waveguide layer 1.

[0122] S52: See also Figure 11 Conductive material is filled into the through hole H to form a contact structure 7, which is electrically connected to the electrode 2.

[0123] For example, the contact structure 7 can be fabricated by depositing a seed layer on the inner wall of the through hole H and then filling the through hole with electrochemical copper plating, thereby achieving a low-resistance, high-frequency vertical interconnect from the back side of the optoelectronic modulator 100 to the front electrode 2.

[0124] The following provides two specific embodiments based on the above preparation method.

[0125] Example 1: S101: Provide a modulator wafer with the front side already processed (i.e., waveguide layer 1 and electrode 2 have been formed on the second substrate 6).

[0126] A 6-inch X-cut lithium niobate on insulator wafer is selected, and its structure from bottom to top is as follows: a 625-micrometer-thick silicon substrate (i.e., the second substrate 6), a 2-micrometer-thick buried oxide layer (SiO2) (i.e., buried oxide layer 8), and a 600-nanometer-thick thin film lithium niobate layer (i.e., waveguide layer 1).

[0127] The wafer has completed the fabrication of front-side devices using standard micro-nano fabrication processes. For example, a 300-nanometer-thick optical waveguide was defined on a thin lithium niobate layer using photolithography and dry etching techniques. A 1-micrometer-thick metal electrode 2 (such as a Ti / Au traveling wave electrode) was fabricated using electron beam evaporation and lift-off processes. This electrode 2 is used to load high-frequency electrical signals to modulate optical waves.

[0128] S102: Silicon oxide (i.e., protective layer 5) is deposited on the front side and resin (i.e., planarization layer 3) is spin-coated to form a bonding layer.

[0129] Among them, silicon oxide deposition: The LNOI wafer with the front side processed is placed in a plasma chemical vapor deposition (PECVD) device, and a silicon oxide layer with a thickness of 0.5 micrometers is deposited at a temperature of 350°C using TEOS (tetraethoxysilane) and O2 as precursors.

[0130] The process includes spin-coating the resin layer: The lithium niobate wafer with the front side processed is placed on a spin coater, and BCB resin is spin-coated at 3000 rpm for 30 seconds to form a uniform resin layer with a thickness of approximately 3 micrometers. The wafer is then placed on a hot plate and subjected to a thermosetting treatment at 250°C in a nitrogen atmosphere for 1 hour to allow the BCB resin to fully cross-link and form a stable bonding interface layer.

[0131] S103: Bonded to the quartz substrate (i.e., the first substrate 4).

[0132] Quartz substrate preparation: A 6-inch quartz wafer with a thickness of 500 micrometers was selected as quartz substrate 6, with a coefficient of thermal expansion (CTE) of 0.5 × 10⁻⁶. -6 / K, dielectric constant 3.8. The quartz substrate and the aforementioned lithium niobate wafer were cleaned in standard RCA cleaning solution and dried with high-purity nitrogen. The cleaned quartz substrate was then placed in an oxygen plasma chamber for activation treatment at a power of 80 W for 60 seconds to improve surface wettability and adhesion.

[0133] Among them, resin bonding: the activated quartz substrate and the spin-coated BCB resin LNOI wafer (device side down) are aligned and bonded in a vacuum bonding equipment, a pressure of 0.2 MPa is applied, and the bonding is completed at 200°C for 30 minutes.

[0134] S104: Thinning of the back side of the silicon substrate.

[0135] First, coarse grinding (rapid thinning) is performed: A diamond grinding wheel is used to mechanically grind the back side of the bonded wafer's silicon substrate. A 20-micron (approximately 800 mesh) diamond grinding wheel is selected, the grinding pressure is set to 0.5 MPa, the working disk rotation speed is 60 rpm, the grinding slurry is deionized water, and the temperature is controlled at 22±1℃. The coarse grinding stage aims for a high removal rate, rapidly thinning the silicon substrate thickness from 625 microns to 150 microns, removing approximately 475 microns. During the grinding process, a laser displacement sensor is used to monitor the wafer thickness in real time to ensure uniform thinning. After coarse grinding, the wafer surface exhibits noticeable grinding marks, with a surface roughness Ra of approximately 0.5-1.0 microns.

[0136] Following this, fine grinding and chemical mechanical polishing (CMP) were performed: a 3-micron (approximately 4000 mesh) fine grinding wheel was used for final mechanical grinding. The grinding pressure was further reduced to 0.2 MPa, the working disc rotation speed was 40 rpm, and a small amount of surfactant was added to the polishing slurry to reduce frictional heat. During this stage, the silicon substrate was thinned from 50 microns to 20 microns, removing approximately 30 microns of thickness, with the feed rate controlled below 1 micron / min. The main purpose of fine grinding was to remove the subsurface damage layer introduced by intermediate grinding and to provide a smooth substrate for subsequent chemical mechanical polishing. After fine grinding, the wafer surface roughness Ra was less than 0.1 microns, and the thickness uniformity (TTV) was better than 2 microns.

[0137] CMP (Continuous Metal Polishing) was used to remove the residual damage layer introduced by mechanical polishing and further reduce the silicon substrate thickness to the target value. A silicon-based CMP polishing slurry (mainly composed of colloidal silica abrasive, pH adjuster, and oxidant) was used, with an abrasive particle size of 50-100 nm. A soft polyurethane polishing pad (such as IC1000) was selected. Process parameters were set as follows: polishing pressure 0.1-0.2 MPa, polishing head speed 60-80 rpm, polishing pad speed 50-70 rpm, polishing slurry flow rate 150-200 mL / min, and polishing time 5-8 minutes. During polishing, an online thickness monitoring system (such as infrared interferometry or eddy current sensing) was used to control the polishing endpoint in real time, precisely reducing the silicon substrate thickness from 20 μm to 15 μm (or a target thickness within the range of 5-100 μm). After CMP, the silicon substrate surface roughness Ra was less than 0.5 nm, TTV was less than 1 μm, and there were no scratches, microcracks, or residual stress layers.

[0138] S105: Create a through hole H to bring out electrode 2.

[0139] First, photolithography and etching are performed to define the vias: A thick layer of photoresist is spin-coated onto the thinned silicon substrate, and the via pattern is defined using photolithography. The via diameter is 30 micrometers, and its position is aligned with the pad area of ​​the front metal electrode. The wafer is then loaded into a DRIE (Dual In-line Etching) device, and the silicon substrate is vertically etched using a Bosch process (alternating SF6 etching and C4F8 passivation). The etching depth is 15 micrometers, precisely stopping at the buried oxide layer surface to form the vias.

[0140] Following this, an insulating layer, seed layer deposition, and electrochemical copper plating are performed: a 0.5 μm thick SiO2 insulating layer is deposited on the inner wall of the via and the silicon surface using PECVD. Then, a Ti / Cu seed layer (Ti 50 nm, Cu 200 nm) is sequentially deposited on the insulating layer by sputtering. Next, the wafer is immersed in a copper sulfate electroplating solution, using the seed layer within the via as the cathode for electrochemical copper plating until copper completely fills the via and forms a capping layer on the surface. Excess copper and seed layer on the back side of the silicon substrate are removed using CMP, making the copper pillars of the via flush with the silicon surface. Finally, a redistribution layer (RDL) and pads (not shown in the figure) connected to the via are sputtered and patterned on the back side, completing the via structure (i.e., contact structure 7), allowing electrode 2 to be led out from the back side for direct packaging with the driver chip.

[0141] A thin-film lithium niobate modulator with a reduced silicon substrate was fabricated using the above-described embodiment. This device significantly reduces the effective dielectric constant of microwave transmission by thinning the high-dielectric-constant silicon substrate to 15 micrometers and bonding it to a low-dielectric-constant quartz substrate, thereby significantly optimizing the phase matching between microwaves and light waves. Simultaneously, by retaining the continuous silicon layer and achieving vertical interconnection of electrodes through vias, the device exhibits both good mechanical strength and thermal stability.

[0142] Example 2: The main difference between this second embodiment and the first embodiment is that in this second embodiment, a sapphire substrate is used instead of a quartz substrate, and the silicon substrate is completely removed in subsequent steps.

[0143] S203: Bonded to the sapphire substrate (i.e., the second substrate 6).

[0144] A 6-inch sapphire wafer with a thickness of 500 micrometers was selected as the substrate, with a coefficient of thermal expansion of 5.0-6.7 × 10⁻⁶. -6 / K, and the coefficient of thermal expansion of lithium niobate (approximately 5.0 × 10⁻⁶). -6 / K) High matching. The sapphire substrate was directly bonded to the lithium niobate wafer that had been planarized with silicon oxide after plasma activation. After bonding, it was annealed at 200°C for 2 hours to enhance the bonding strength.

[0145] S204: Silicon substrate completely removed.

[0146] (1) Mechanical polishing: The silicon substrate 1 was thinned from 625 micrometers to 15 micrometers by mechanical polishing.

[0147] (2) Wet etching: The polished wafer is immersed in tetramethylammonium hydroxide (TMAH) solution and wet etched at 80°C until the silicon substrate is completely removed and the etching stops precisely on the surface of the buried oxide layer, exposing the buried oxide layer. TMAH has a high selectivity for silicon and an extremely low etching rate for the buried oxide layer.

[0148] (3) Surface cleaning: Rinse with deionized water and dry to obtain the exposed buried oxide layer surface.

[0149] S205: Create a through hole H to bring out electrode 2.

[0150] Photoresist was spin-coated onto the exposed buried oxide layer surface. After photolithography defined the via pattern, reactive ion etching was used to vertically etch the buried oxide layer, precisely stopping at the metal electrode surface to form the via. Subsequent steps, such as insulating layer deposition, seed layer deposition, and electrochemical copper plating, were the same as in Example 1.

[0151] By completely removing the silicon substrate, the influence of high-dielectric-constant silicon on microwave transmission can be completely eliminated. Combined with device design optimization, this further improves the modulator's bandwidth performance. Simultaneously, since the silicon substrate is completely removed, the CTE mismatch stress is further reduced, resulting in better device thermal stability.

[0152] The high CTE between sapphire substrate and lithium niobate can effectively avoid thermal stress cracking during high-temperature annealing after bonding, making it particularly suitable for device fabrication scenarios requiring high-temperature processes.

[0153] This application also provides an optoelectronic modulation system 1000. Figure 12 This is a schematic diagram of the structure of an optoelectronic modulation system 1000 provided in an embodiment of this application.

[0154] See Figure 12 The photoelectric modulation system 1000 includes a light-emitting structure 200 and a photoelectric modulator 100 provided in any of the foregoing embodiments. The light-emitting structure 200 is configured to generate an optical signal and transmit the optical signal to the photoelectric modulator 100. That is, the light-emitting structure 200 is a light source, for example, the light-emitting structure 200 can be a laser.

[0155] The technical effects brought about by the structural design of the optoelectronic modulation system 1000 can be referred to the technical effects brought about by the optoelectronic modulator 100 in any of the foregoing embodiments, and will not be repeated here.

[0156] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A photoelectric modulator, characterized in that, include: A waveguide layer, wherein an identification mark is provided on one side surface of the waveguide layer; An electrode is disposed on the surface of the waveguide layer; the identification mark is configured to achieve positional alignment between the waveguide layer and the electrode. A planarization layer is located on the side of the waveguide layer where the identification mark is located; the surface of the planarization layer away from the waveguide layer is planarized. A first substrate is disposed on the side of the planarization layer away from the waveguide layer and is bonded to the planarization layer; The dielectric constant of the first substrate is less than 5.

2. The photoelectric modulator according to claim 1, characterized in that, The material of the planarization layer includes one or more of polymers and silicon dioxide.

3. The photoelectric modulator according to claim 1, characterized in that, The material of the first substrate includes one or more of quartz, sapphire, and diamond.

4. The photoelectric modulator according to claim 1, characterized in that, Also includes: A protective layer is located between the waveguide layer and the planarization layer; wherein the refractive index of the protective layer is less than that of the waveguide layer; wherein the waveguide layer has an electro-optic coefficient, and the material of the waveguide layer includes one or more of lithium niobate, lithium tantalate, barium titanate, and lead zirconate titanate.

5. The photoelectric modulator according to claim 1, characterized in that, Also includes: The second substrate is located on the side of the waveguide layer away from the first substrate; the dielectric constant of the first substrate is less than that of the second substrate, and the thickness of the first substrate is greater than that of the second substrate.

6. The photoelectric modulator according to claim 5, characterized in that, The thickness of the second substrate is 0 μm to 200 μm.

7. The photoelectric modulator according to claim 5, characterized in that, The difference in the coefficient of thermal expansion between the first substrate and the waveguide layer is less than the difference in the coefficient of thermal expansion between the second substrate and the waveguide layer.

8. The photoelectric modulator according to claim 1, characterized in that, Also includes: A contact structure is located on the side of the electrode away from the first substrate, and the contact structure is electrically connected to the electrode.

9. A photoelectric modulation system, characterized in that, include: The photoelectric modulator as described in any one of claims 1 to 8; A light-emitting structure is configured to generate an optical signal and transmit the optical signal to the photoelectric modulator.

10. A method for fabricating a photoelectric modulator, characterized in that, include: A waveguide layer and an electrode are formed on a second substrate; an identification mark is provided on the surface of the waveguide layer away from the second substrate; the electrode is disposed on the surface of the waveguide layer; the identification mark is configured to achieve positional alignment of the waveguide layer and the electrode. A planarization layer is formed on the side of the waveguide layer away from the second substrate; The surface of the planarization layer away from the waveguide layer is planarized. A first substrate is formed on the side of the planarization layer away from the waveguide layer; the first substrate is bonded to the planarization layer; wherein the dielectric constant of the first substrate is less than 5; At least a portion of the second substrate that is away from the first substrate is removed to reduce the thickness of the second substrate to a target thickness.

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