DDR data transmission fault-tolerant method and system
By setting timing thresholds and distinction criteria in DDR data transmission, real-time analysis of signal timing, and adjustment of sampling clock phase and data transmission delay, the problem of metastable error identification is solved, and efficient fault-tolerant processing of DDR data transmission is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN YOUJING MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-03-16
- Publication Date
- 2026-06-16
AI Technical Summary
In existing DDR data transmission, metastable sampling errors caused by timing offsets are difficult to identify, leading to a decrease in data processing efficiency. Existing ECC fault tolerance mechanisms cannot accurately identify instantaneous non-fixed bit errors, resulting in passive retransmission and error accumulation.
By setting setup time threshold, hold time threshold, sampling window precision, and calibration step size, and combining the criteria for distinguishing metastable and fixed bit errors, the signal timing is analyzed in real time, and the sampling clock phase and data transmission delay are adjusted to achieve accurate error correction of metastable errors and to offload fixed bit errors to the ECC process.
It achieves accurate identification and correction of metastable errors, avoids misjudgment and error accumulation, improves data processing efficiency, adapts to the timing requirements of DDR high-speed transmission, and reduces the impact of error correction on transmission efficiency.
Smart Images
Figure CN122220142A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory data processing, specifically relating to DDR data transmission fault tolerance methods and systems. Background Technology
[0002] In high-speed transmission of DDR technology, timing skew-induced sampling errors can lead to insufficient setup or hold time between the data signal and the sampling clock, resulting in metastable sampling errors. These errors are instantaneous and non-fixed-bit, and existing fault-tolerance mechanisms such as ECC, which are based on "fixed-bit errors," cannot accurately identify them and can only passively trigger retransmissions, leading to a significant decrease in data processing efficiency. Summary of the Invention
[0003] The purpose of this invention is to provide a DDR data transmission fault-tolerant method and system to solve the problems mentioned in the background art.
[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0005] DDR data transfer fault tolerance method, including the following steps:
[0006] Start the DDR transmission and fault tolerance process, set the setup time threshold, hold time threshold, sampling window accuracy, calibration step size, error correction response delay, and determine the criteria for distinguishing metastable and fixed bit errors; Data and sampling clock signals are synchronously acquired at the DDR transmission rate, and after filtering out noise, they are transmitted to the detection process and temporarily stored in the cache. Analyze the signal timing. If the timing is off and the error is instantaneous and non-fixed, it is determined to be a metastable error and a signal is sent to the calibration and error correction process. Fixed-bit errors are sent to the ECC process for processing. Adjust the sampling clock phase and data transmission delay according to the preset step size until the timing meets the threshold requirements, then feed back the calibration parameters and send a completion signal to the error correction process; The original cached signal is retrieved, and the error is corrected by resampling based on the calibration parameters. The corrected data is then transmitted to the subsequent process. The feedback process fine-tunes timing thresholds and continuously detects, calibrates, and corrects errors.
[0007] Furthermore, the criteria for distinguishing between metastable and fixed bit errors include: metastable errors do not repeat the same position error within three consecutive transmission cycles; the number of non-fixed bit errors in a metastable error does not exceed 2 bits within a single transmission cycle; fixed bit errors are errors with fixed error bits; fixed bit errors repeat the same position error within three consecutive transmission cycles; and the number of non-fixed bit errors in a fixed bit error exceeds 2 bits within a single transmission cycle.
[0008] Furthermore, the analysis of signal timing, if a timing offset occurs and the error is instantaneous and non-fixed, is determined to be a metastable error and a signal is sent to the calibration and error correction process. This includes: the timing offset detection process analyzes the synchronously acquired signal in real time, calculates the actual setup time and actual hold time, and compares them with the corresponding thresholds to determine whether a timing offset exists; simultaneously, it retrieves historical signal data from the data cache, analyzes the distribution characteristics of the detected error bits, and if the error meets the characteristics of an instantaneous, non-fixed metastable error, it is determined to be a metastable error; after determination, the metastable error signal is immediately sent to the timing calibration process and the precise error correction process.
[0009] Furthermore, the fixed bit error is sent to the ECC process for processing, including: the timing offset detection process analyzes the synchronization signal in real time, calculates the actual setup time and the actual hold time and compares them with the corresponding thresholds. After determining that there is a timing offset, it retrieves the cached historical signal data, analyzes the error bit distribution characteristics, and if it meets the characteristics of a fixed bit error, it is determined to be a fixed bit error. Then, the fixed bit error signal is sent to the ECC process, which processes it according to the fault tolerance mechanism.
[0010] Furthermore, the step of adjusting the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements includes: the timing calibration process starts the calibration operation after receiving the metastable error signal; based on the detected timing offset, the sampling clock phase is adjusted by a preset step size, while the data transmission delay is fine-tuned; during the adjustment process, the actual setup time and hold time are detected in real time and compared with the corresponding threshold, and both are continuously adjusted until the timing meets the preset threshold requirements.
[0011] Furthermore, the step of feeding back calibration parameters and sending a completion signal to the error correction process includes: after the timing calibration process completes the timing calibration operation, immediately feeding back the calibration parameters to the timing offset detection process and the feedback process in real time, and simultaneously sending a calibration completion signal to the precision error correction process, ensuring that the signal transmission does not exceed the preset error correction response delay.
[0012] Furthermore, the step of calling the cached original signal, resampling and correcting the error according to the calibration parameters, and transmitting the corrected data to the subsequent process includes: after receiving the calibration completion signal, the precise error correction process calls the original signal in the cache corresponding to the period in which the metastable error occurs; resamples the erroneous data according to the calibration parameters; completes the precise correction of the metastable error through resampling and replaces the original erroneous data; after the error correction is completed, the corrected data is transmitted to the subsequent process, and an error correction completion signal is sent while ensuring that the preset error correction response delay is not exceeded.
[0013] Furthermore, the feedback process fine-tunes the timing threshold and continuously detects, calibrates, and corrects errors, including: the feedback process receives calibration parameters, detection results, and error correction results; updates the timing threshold and optimizes the metastable state detection accuracy accordingly; initiates a loop mechanism to continuously trigger signal acquisition, detection, calibration, and error correction; and avoids the accumulation of metastable state errors and unnecessary passive retransmissions.
[0014] This application also discloses an electronic device, including:
[0015] At least one processor; and
[0016] A memory communicatively connected to the at least one processor; wherein,
[0017] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the DDR data transmission fault-tolerant method of the present invention described above.
[0018] This application also discloses a DDR data transmission fault-tolerant system, including: a parameter configuration module for setting setup time threshold, hold time threshold, sampling window accuracy, calibration step size, and error correction response delay, and determining the criteria for distinguishing between metastable and fixed bit errors; a synchronous acquisition module for synchronously acquiring data and sampling clock signals at the DDR transmission rate, filtering noise, and transmitting the data to the detection process, while temporarily storing the data in a buffer; an error determination module for analyzing signal timing, determining metastable errors if timing is off and the error is instantaneous and non-fixed bit, and sending a signal to the calibration and error correction process; and sending fixed bit errors to the ECC process for processing; a calibration adjustment module for adjusting the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements, feeding back calibration parameters, and sending a completion signal to the error correction process; a data error correction module for calling the buffered original signal, resampling and correcting errors according to the calibration parameters, and transmitting the corrected data to the subsequent process; and a threshold fine-tuning module for feeding back the process to fine-tune the timing threshold, continuously driving the detection, calibration, and error correction processes.
[0019] Beneficial effects: This application, by clearly defining the distinction criteria between metastable and fixed-position errors and combining historical signal analysis of the data buffer, can effectively determine the two error types, solving the problem of difficulty in identifying metastable errors in the prior art and avoiding invalid processing or error accumulation caused by misjudgment. The timing offset detection, combined with a preset threshold and corresponding sampling window precision, improves the accuracy of error detection and provides a reliable basis for subsequent processing.
[0020] To address timing offsets caused by signal crosstalk and power supply noise, the system synchronously adjusts the sampling clock phase and data transmission delay with a preset calibration step size until the timing meets a preset threshold, achieving adaptive calibration of the timing offset. This calibration requires no manual intervention, reduces metastable error recurrence, and adapts to the timing requirements of high-speed DDR transmission.
[0021] By using data caching, metastable errors can be detected and the original signal can be resampled for error correction, eliminating the need for passive retransmission and reducing the impact of error correction on transmission efficiency. Error correction response latency is controlled within a reasonable range, and fixed-bit errors are offloaded to the ECC process for differentiated fault tolerance, improving overall processing efficiency. Attached Figure Description
[0022] Figure 1 This is a flowchart of the DDR data transmission fault tolerance method of the present invention.
[0023] Figure 2 This is a partial flowchart of the DDR data transmission fault tolerance method of the present invention.
[0024] Figure 3 This is a partial flowchart of the DDR data transmission fault tolerance method of the present invention.
[0025] Figure 4 This is a comparison chart of the error identification accuracy of the DDR data transmission fault tolerance method of the present invention.
[0026] Figure 5 This is a graph showing the metastable error recurrence rate variation of the DDR data transmission fault-tolerant method of the present invention. Detailed Implementation
[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0028] This invention provides a fault-tolerant method for DDR data transmission, such as... Figure 1 As shown, the steps include:
[0029] Start the DDR transmission and fault tolerance process, set the setup time threshold, hold time threshold, sampling window accuracy, calibration step size, error correction response delay, and determine the criteria for distinguishing metastable and fixed bit errors; Data and sampling clock signals are synchronously acquired at the DDR transmission rate, and after filtering out noise, they are transmitted to the detection process and temporarily stored in the cache. Analyze the signal timing. If the timing is off and the error is instantaneous and non-fixed, it is determined to be a metastable error and a signal is sent to the calibration and error correction process. Fixed-bit errors are sent to the ECC process for processing. Adjust the sampling clock phase and data transmission delay according to the preset step size until the timing meets the threshold requirements, then feed back the calibration parameters and send a completion signal to the error correction process; The original cached signal is retrieved, and the error is corrected by resampling based on the calibration parameters. The corrected data is then transmitted to the subsequent process. The feedback process fine-tunes timing thresholds and continuously detects, calibrates, and corrects errors.
[0030] The aforementioned DDR transmission and fault tolerance process includes setting setup time thresholds, hold time thresholds, sampling window accuracy, calibration step size, and error correction response delay. In practice, this specifically includes: starting the DDR data transmission system and the corresponding fault tolerance process, while simultaneously starting the timing calibration process, error detection process, precise error correction process, and feedback process to ensure that all processes work together in a normal state.
[0031] Set the setup time threshold for the sampling clock and data signals. The setup time threshold is 10 ps. Set the hold time threshold for the sampling clock and data signals. The hold time threshold is 8 ps. Set the sampling window precision for timing offset detection. The sampling window precision is ±1 ps. Set the calibration step size during timing calibration. The calibration step size is 0.5 ps. Set the error correction response delay for the error correction process. The error correction response delay should not exceed 2 ns.
[0032] The criteria for distinguishing between metastable and fixed bit errors specifically include, in practice: determining the basis for classifying metastable and fixed bit errors. Metastable errors are instantaneous errors. The error bits in a metastable error are not fixed. Within three consecutive transmission cycles, a metastable error will not repeat the same position error. Within a single transmission cycle, the number of non-fixed bit errors in a metastable error does not exceed two bits. Fixed bit errors are errors with fixed error bits. Fixed bit errors will repeat the same position error within three consecutive transmission cycles. Within a single transmission cycle, the number of non-fixed bit errors in a fixed bit error exceeds two bits.
[0033] The process of synchronously acquiring data and sampling clock signals at the DDR transfer rate, filtering out noise, and then transmitting the data to the detection process while simultaneously storing it in a buffer, specifically includes: synchronously acquiring data signals and sampling clock signals at the DDR transfer rate. The acquisition frequency is consistent with the DDR transfer rate. The acquisition frequency corresponding to DDR5 is 6400MHz. During the acquisition process, noise is filtered from the signal to ensure the integrity of the acquired signal. The filtered real-time signal is synchronously transmitted to the timing offset detection process. Simultaneously, the acquired real-time signal is temporarily stored in a data buffer for 5 transmission cycles.
[0034] like Figure 2 The analysis of signal timing, if a timing offset occurs and the error is instantaneous and non-fixed, is determined to be a metastable error, and a signal is sent to the calibration and error correction process. Specifically, this includes: a timing offset detection process that performs real-time analysis of the acquired synchronization signal; calculating the actual setup time and actual hold time of the data signal and the sampling clock; comparing the actual setup time with a set setup time threshold; comparing the actual hold time with a set hold time threshold; determining that a timing offset exists if the actual setup time is less than 10 ps or the actual hold time is less than 8 ps; simultaneously retrieving historical signal data temporarily stored in the data buffer; analyzing the distribution characteristics of the detected error bits; if the error is instantaneous and the error bits are not fixed; the number of non-fixed bit errors does not exceed 2 bits in a single transmission cycle, and the same error position does not recur in 3 consecutive transmission cycles, it is determined to be a metastable error; after determining a metastable error, a metastable error signal is immediately sent; the error signal is sent to the timing calibration process; and the error signal is simultaneously sent to the precise error correction process.
[0035] The fixed-bit error is sent to the ECC process for processing, which specifically includes: a timing offset detection process that performs real-time analysis of the acquired synchronization signal; calculating the actual setup time and actual hold time of the data signal and the sampling clock; comparing the actual setup time with a set setup time threshold; comparing the actual hold time with a set hold time threshold; if a timing offset is determined, retrieving historical signal data temporarily stored in the data buffer; analyzing the distribution characteristics of the detected error bits; if the error bits are fixed, the same position error occurs repeatedly within 3 consecutive transmission cycles; if the number of non-fixed bit errors exceeds 2 in a single transmission cycle, it is determined to be a fixed-bit error; after being determined to be a fixed-bit error, a fixed-bit error signal is immediately sent; the error signal is sent to the ECC process; the ECC process handles the fixed-bit error according to the traditional fault-tolerance mechanism.
[0036] The process of adjusting the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements specifically includes: Upon receiving a metastable error signal, the timing calibration process immediately initiates the timing calibration operation. Based on the detected timing offset, the phase of the sampling clock is adjusted by a preset calibration step size of 0.5 ps. Simultaneously, the data signal transmission delay is fine-tuned. During the adjustment process, the actual setup time and actual hold time of the data signal and the sampling clock are monitored in real time. The actual setup time is compared with a set setup time threshold of 10 ps. The actual hold time is compared with a set hold time threshold of 8 ps. The sampling clock phase and data transmission delay are continuously adjusted until the actual setup time is not less than 10 ps and the actual hold time is not less than 8 ps, ensuring that the timing meets the preset threshold requirements.
[0037] The feedback of calibration parameters and the sending of a completion signal to the error correction process specifically includes the following steps in implementation: After the timing calibration process completes the timing calibration operation, the calibration parameters are immediately fed back in real time. The calibration parameters are fed back to the timing offset detection process. The calibration parameters are simultaneously fed back to the feedback process. The timing calibration process synchronously sends a calibration completion signal. The calibration completion signal is sent to the precision error correction process. It is ensured that the transmission of the calibration completion signal does not exceed the preset error correction response delay. The error correction response delay does not exceed 2ns.
[0038] The process of calling the cached original signal, resampling and correcting it according to calibration parameters, and then transmitting the corrected data to subsequent processes includes the following steps: After receiving the calibration completion signal, the precise error correction process immediately calls the original signal temporarily stored in the data cache. The original signal called corresponds to the transmission period in which the metastable error occurred. The data cache duration is 5 transmission periods. Based on the calibration parameters fed back from the timing calibration process, the erroneous data is resampled. The resampling process strictly follows the calibrated sampling clock phase and data transmission delay. The calibration step size is 0.5 ps. Precise correction of the metastable error data is achieved through resampling. The corrected erroneous data replaces the original erroneous data. After the error correction operation is completed, the corrected data is transmitted to the subsequent data processing flow. Simultaneously, an error correction completion signal is sent. The time for sending the error correction completion signal does not exceed the preset error correction response delay. The error correction response delay does not exceed 2 ns.
[0039] The feedback process fine-tunes the timing thresholds, continuously detecting, calibrating, and correcting errors, such as... Figure 3 In practice, this includes: A feedback process receives calibration parameters from the timing calibration process. The feedback process simultaneously receives detection results from the error detection process and error correction results from the precise error correction process. Based on the received calibration parameters, detection results, and error correction results, the feedback process updates the timing thresholds in the system initialization configuration in real time. The fine-tuning range of the timing thresholds does not exceed ±1ps. The feedback process synchronously optimizes the detection accuracy of metastable sampling errors. The feedback process initiates a cyclical working mechanism, continuously triggering the timing signal synchronous acquisition process. It continuously performs precise detection of metastable sampling errors. It continuously executes timing offset adaptive calibration operations. It continuously completes precise error correction of metastable errors. Through continuous detection, calibration, and error correction, the accumulation of metastable sampling errors is avoided. Unnecessary passive retransmissions are eliminated. The continuity of DDR data transmission is ensured. The stability of DDR data processing efficiency is guaranteed.
[0040] like Figure 4The comparison chart clearly verifies the core advantages of the DDR fault-tolerant solution of this patent: under different timing offset scenarios, the accuracy of metastable error identification (90%-98%) is far superior to that of traditional ECC (15%-45%), solving the problem of failure of traditional solutions to identify instantaneous non-fixed position metastable errors; the identification rate of fixed position errors (95%-99%) is also slightly higher than that of ECC, achieving accurate differentiation of all types of errors.
[0041] From the perspective of auxiliary parameters, the larger the timing offset, the more significant the decrease in accuracy of traditional ECC (the metastable recognition rate is only 15% under high offset). However, this solution maintains an accuracy of over 90% with adaptive timing calibration of a calibration step size of 0.5ps. At the same time, the retransmission rate of this solution (2%-40%) is significantly lower than that of ECC (especially in metastable scenarios), and the error correction response delay is controlled within the 2ns threshold, which meets the design goal of "avoiding passive retransmission and improving transmission efficiency" in the patent.
[0042] In low / medium offset scenarios, the accuracy of this solution is close to 100%, which verifies the rationality of the timing threshold (10ps for setup / 8ps for hold) and the effectiveness of the metastable / fixed bit error distinction standard (3 consecutive cycles, single cycle error bit number), fully demonstrating that the solution can adapt to the fault tolerance requirements of DDR5 high-speed transmission.
[0043] like Figure 5 The graph, with DDR data transmission time on the x-axis (0-60 seconds) and metastable error recurrence rate (%) on the y-axis, compares the error recurrence trends with and without adaptive timing calibration. The uncalibrated group (traditional ECC) had an initial recurrence rate of 8%, which increased significantly over time (eventually reaching 14%), with noticeable fluctuations in the curve. This is because the traditional method cannot distinguish between metastable and fixed-position errors, and can only passively retransmit, leading to error accumulation and a continuously rising recurrence rate. The calibrated group (patented method) had an initial recurrence rate consistent with the traditional group, but it rapidly dropped below 0.5% within 5 seconds of calibration initiation, subsequently stabilizing at around 0.2%, with fluctuations <0.1%. This is because the patented method accurately detects timing offsets through setup / hold time thresholds of 10ps / 8ps, adjusts the sampling clock phase and data delay in 0.5ps steps, and combines a feedback process to fine-tune the threshold by ±1ps, continuously optimizing detection accuracy and eliminating the accumulation of metastable errors. The charts verify that the patented adaptive timing calibration can significantly reduce the metastable error recurrence rate and maintain a low recurrence level for a long time, solving the efficiency decline problem caused by passive retransmission in traditional methods.
[0044] In DDR transmission, the intensity of signal crosstalk and power supply noise changes dynamically. The existing fixed threshold of "3 transmission cycles, 2 bit errors" cannot adapt to the dynamic changes in timing offset to a certain extent, and is prone to misjudgment, such as the threshold being too lenient in low noise and too strict in high noise. Therefore, this application further provides a dynamic quantization discrimination method for metastable and fixed bit errors based on timing offset quantization characteristics. It adopts the core logic of quantization calculation and dynamic adaptive threshold, and realizes error type determination through mathematical modeling of timing offset and the spatiotemporal distribution of error bits, including:
[0045] Input dataset Include: Timing offset quantization parameter: The actual settling time of the data signal and the sampling clock within each transmission cycle Actual holding time Preset establishment time threshold Preset hold time threshold ; Error bit distribution parameters: continuous Set of error bit locations for each transmission cycle ,in For the first Error bit location vector for each transmission cycle , The total number of bits in a single period of data. Indicates the first Bit error, Indicates the first (Number of bits normal); Number of error bits within a single cycle (Right now middle (number of elements); Basic transmission parameters: Total number of transmission cycles (Taking 5 consecutive transmission cycles within the sliding window, adapting to the original design of 5-cycle buffer), total number of bits of data per cycle. Timing offset sensitivity coefficient (Experience points, take) (Adapted to DDR5 6400MHz transmission rate). The setup time and hold time of the input are quantized and calculated to obtain the comprehensive timing offset, and the existence of timing offset is determined, laying the foundation for subsequent error type determination.
[0046] 1. Calculate the first... Establishment time offset for each cycle Maintain time offset :
[0047] ;
[0048] 2. Calculate the overall timing offset (Normalization process), if If a timing offset is detected, proceed to the subsequent error type determination; if There is no timing offset and no error.
[0049] ;
[0050] Parameter meaning: Establish time offset weights, take... (Setup time has a greater impact on sampling errors in DDR transmission); Parameter meaning: Maintain time offset weight, take ;
[0051] The maximum value among the preset thresholds is used for normalization, making... ;
[0052] Output: Timing offset determination result ( (Existing offset), combined timing offset .
[0053] The spatial distribution entropy of error bits is calculated. Spatial distribution entropy is used to quantitatively characterize the dispersion of error bits within a single period. Metastable errors are instantaneous non-fixed bit errors with high error bit dispersion and large distribution entropy; fixed bit errors are errors with fixed error bits with low error bit dispersion and small distribution entropy.
[0054] With the first Taking one transmission cycle as an example, calculate the spatial distribution entropy of the error bits. :
[0055] ;
[0056] in, For the first Within the first cycle The probability of a bit error, if but (Regulation ).
[0057] Parameter meaning: The first The first cycle The probability of bit error; Parameter meaning: The first Number of error bits within a period; Parameter meaning: Total number of bits in a single period of data;
[0058] Continuous output The set of error bit spatial distributions in each period And calculate its mean. (Characterizing the overall degree of dispersion).
[0059] Error bit time recurrence probability calculation: Time recurrence probability is used to quantify the degree of error repetition at the same position within a continuous period. Metastable errors will not recur at the same position, and the time recurrence probability is low; fixed bit errors will recur at the same position, and the time recurrence probability is high.
[0060] Calculate continuous Error bit time recurrence probability within a transmission cycle
[0061] ;
[0062] Parameter meaning: The first Located in Total number of errors within a cycle;
[0063] Parameter meaning: The total number of transmission cycles within the sliding window (set to 5, matching the original buffer of 5 cycles).
[0064] Total number of error bits within a period;
[0065] Output error bit time recurrence probability , , The closer the threshold is to 1, the higher the degree of repetition of the error bit. Then, abandoning the original fixed threshold, a dynamic discrimination threshold is constructed based on the comprehensive time offset and the time offset sensitivity coefficient. (Distribution entropy threshold) and (Reprobability threshold), the threshold is dynamically adjusted as the time sequence offset changes, adapting to the dynamic characteristics of DDR transmission:
[0066] ;
[0067] For: Timing skew sensitivity coefficient, an empirical value, 1.0 for DDR5, which can be fine-tuned according to the transfer rate (0.8~1.2);
[0068] For: Total number of bits in a single period of data This is the theoretical maximum value of the distribution entropy;
[0069] For: the calculated composite timing offset;
[0070] The Sigmoid function enables smooth and dynamic adjustment of the threshold, allowing the threshold to adaptively optimize as the time series offset increases.
[0071] Output dynamic distribution entropy threshold Dynamic recurrence probability threshold .
[0072] Then construct the error type quantization discrimination function. The mean of the distribution entropy Time recurrence probability Combined with dynamic thresholds, through The range of values directly determines the error type, achieving quantitative judgment:
[0073] ;
[0074] For: weighting coefficients, take Because the time recurrence probability is a more significant characterization of fixed position errors; For: the mean entropy of the spatial distribution of error bits; For: the constructed dynamic distribution entropy threshold; For: the calculated time recurrence probability of the error bit; For: the constructed dynamic recurrence probability threshold;
[0075] Output the discriminant function value ,according to The error type is determined by the range of values, and the determination rule is as follows:
[0076] 1. If 1. If a metastable error is detected, a signal is sent to the original calibration and error correction process; 2. If If the error is determined to be a fixed bit error, a signal is sent to the original ECC process for processing.
[0077] The output is a clear error type determination result (metastable error / fixed bit error), and also outputs the quantization discrimination function value. Comprehensive timing offset The quantization result can be directly transferred to the subsequent timing calibration process, providing a quantization reference for sampling clock phase adjustment and data transmission delay calibration, realizing the quantization linkage of error judgment and calibration error correction, and solving the problem of the disconnect between the original qualitative judgment and subsequent quantization calibration.
[0078] This application also provides an embodiment of an electronic device. The electronic device is manifested in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: one or more processors or processing units, memory, and buses connecting different components (including memory and processing units).
[0079] A bus refers to one or more of several bus architectures, including memory buses or memory controllers, peripheral buses, graphics acceleration ports, processors, or local buses using any of the various bus architectures. Examples of these architectures include, but are not limited to, Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.
[0080] Electronic devices typically include a variety of computer-readable media. These media can be any available media that can be accessed by the electronic device, including volatile and non-volatile media, and removable and non-removable media.
[0081] The memory may include computer-readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. Electronic devices may further include other removable / non-removable, volatile / non-volatile computer device storage media. By way of example only, the storage system may be used to read and write non-removable, non-volatile magnetic media.
[0082] The electronic device can also communicate with one or more external devices (e.g., keyboard, pointing device, camera, etc.), may include a display, and may communicate with one or more devices that enable a user to interact with the electronic device, and / or with any device that enables the electronic device to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via an input / output (I / O) interface. Furthermore, the electronic device can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. The processor executes various functional applications and data processing by running programs stored in memory, such as implementing the DDR data transmission fault-tolerant method provided in the above embodiments of the present invention.
[0083] This application also discloses a DDR data transmission fault-tolerant system, including: a parameter configuration module for setting setup time threshold, hold time threshold, sampling window accuracy, calibration step size, and error correction response delay, and determining the criteria for distinguishing between metastable and fixed bit errors; a synchronous acquisition module for synchronously acquiring data and sampling clock signals at the DDR transmission rate, filtering noise, and transmitting the data to the detection process, while temporarily storing the data in a buffer; an error determination module for analyzing signal timing, determining metastable errors if timing is off and the error is instantaneous and non-fixed bit, and sending a signal to the calibration and error correction process; and sending fixed bit errors to the ECC process for processing; a calibration adjustment module for adjusting the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements, feeding back calibration parameters, and sending a completion signal to the error correction process; a data error correction module for calling the buffered original signal, resampling and correcting errors according to the calibration parameters, and transmitting the corrected data to the subsequent process; and a threshold fine-tuning module for feeding back the process to fine-tune the timing threshold, continuously driving the detection, calibration, and error correction processes.
[0084] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A DDR data transmission fault-tolerant method, characterized in that, Includes the following steps: Start the DDR transmission and fault tolerance process, set the setup time threshold, hold time threshold, sampling window accuracy, calibration step size, error correction response delay, and determine the criteria for distinguishing metastable and fixed bit errors; Data and sampling clock signals are synchronously acquired at the DDR transmission rate, and after filtering out noise, they are transmitted to the detection process and temporarily stored in the cache. Analyze the signal timing. If the timing is off and the error is instantaneous and non-fixed, it is determined to be a metastable error and a signal is sent to the calibration and error correction process. Fixed-bit errors are sent to the ECC process for processing. Adjust the sampling clock phase and data transmission delay according to the preset step size until the timing meets the threshold requirements, then feed back the calibration parameters and send a completion signal to the error correction process; The original cached signal is retrieved, and the error is corrected by resampling based on the calibration parameters. The corrected data is then transmitted to the subsequent process. The feedback process fine-tunes timing thresholds and continuously detects, calibrates, and corrects errors.
2. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The criteria for distinguishing between metastable and fixed bit errors include: metastable errors do not repeat the same position error within three consecutive transmission cycles; the number of non-fixed bit errors in a metastable error does not exceed 2 bits within a single transmission cycle; fixed bit errors are errors with fixed error bits; fixed bit errors will repeat the same position error within three consecutive transmission cycles; and the number of non-fixed bit errors in a fixed bit error exceeds 2 bits within a single transmission cycle.
3. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, If the analyzed signal timing is offset and the error is instantaneous and non-fixed, it is determined to be a metastable error and a signal is sent to the calibration and error correction process. This includes: the timing offset detection process analyzes the synchronously acquired signal in real time, calculates the actual setup time and actual hold time, and compares them with the corresponding thresholds to determine whether a timing offset exists; at the same time, it retrieves historical signal data from the data buffer, analyzes the distribution characteristics of the detected error bits, and if the error meets the characteristics of an instantaneous metastable error with non-fixed error bits, it is determined to be a metastable error; after determination, the metastable error signal is immediately sent to the timing calibration process and the precise error correction process.
4. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The fixed bit error is sent to the ECC process for processing, including: the timing offset detection process analyzes the synchronization signal in real time, calculates the actual setup time and the actual hold time and compares them with the corresponding thresholds. After determining that there is a timing offset, it retrieves the cached historical signal data, analyzes the error bit distribution characteristics, and if it meets the characteristics of a fixed bit error, it is determined to be a fixed bit error. Then, the fixed bit error signal is sent to the ECC process, which processes it according to the fault tolerance mechanism.
5. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The step of adjusting the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements includes: the timing calibration process starts the calibration operation after receiving the metastable error signal; based on the detected timing offset, the sampling clock phase is adjusted by a preset step size, and the data transmission delay is fine-tuned at the same time; during the adjustment process, the actual setup time and hold time are detected in real time and compared with the corresponding threshold, and the two are continuously adjusted until the timing meets the preset threshold requirements.
6. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The feedback calibration parameters and sending the completion signal to the error correction process include: after the timing calibration process completes the timing calibration operation, it immediately feeds back the calibration parameters to the timing offset detection process and the feedback process in real time, and synchronously sends the calibration completion signal to the precision error correction process, ensuring that the signal transmission does not exceed the preset error correction response delay.
7. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The process of calling the cached original signal, resampling and correcting the error based on the calibration parameters, and transmitting the corrected data to subsequent processes includes: after receiving the calibration completion signal, the precise error correction process calls the original signal in the cache corresponding to the period in which the metastable error occurs; resamples the erroneous data based on the calibration parameters; completes the precise correction of the metastable error through resampling and replaces the original erroneous data; after the error correction is completed, the corrected data is transmitted to subsequent processes, and an error correction completion signal is sent while ensuring that the preset error correction response delay is not exceeded.
8. The DDR data transmission fault-tolerant method according to claim 1, characterized in that, The feedback process fine-tunes the timing threshold and continuously detects, calibrates, and corrects errors, including: receiving calibration parameters, detection results, and error correction results; updating the timing threshold and optimizing metastable state detection accuracy accordingly; initiating a loop mechanism to continuously trigger signal acquisition, detection, calibration, and error correction; and avoiding the accumulation of metastable state errors and unnecessary passive retransmissions.
9. A system applying the DDR data transmission fault-tolerant method of claim 1, characterized in that, include: The parameter configuration module is used to set the setup time threshold, hold time threshold, sampling window precision, calibration step size, error correction response delay, and determine the criteria for distinguishing metastable and fixed position errors. The synchronous acquisition module is used to synchronously acquire data and sampling clock signals at the DDR transmission rate, filter out noise and transmit the data to the detection process, and temporarily store the data in the buffer. The error determination module is used to analyze the signal timing. If the timing is off and the error is instantaneous and non-fixed, it is determined to be a metastable error and a signal is sent to the calibration and error correction process. If it is a fixed-position error, it is sent to the ECC process for processing. The calibration and adjustment module is used to adjust the sampling clock phase and data transmission delay by a preset step size until the timing meets the threshold requirements, and then feeds back the calibration parameters and sends a completion signal to the error correction process. The data error correction module is used to call up the cached original signal, resample and correct the error according to the calibration parameters, and then transmit the corrected data to the subsequent process. The threshold fine-tuning module is used to provide feedback on the timing thresholds for fine-tuning the process, continuously driving the detection, calibration, and error correction processes.