High-precision I2C bus timing generation and data acquisition method and device

Abstract

The application provides a high-precision I2C bus timing generation and data collection method and device, relates to the fields of optical communication, automatic testing, precision instruments, embedded systems and the like, and comprises the following steps: a CPU processor calculates all timing information required for complete protocol interaction containing a write operation stage and a read operation stage according to a target I2C protocol standard and a test frequency, and encodes a continuous data stream to be stored in a system memory; a hardware timer generates a periodic trigger pulse according to the test frequency; in the write operation stage, a DMA controller responds to the trigger pulse and outputs to a GPIO output register; in the read operation stage, the DMA controller and an input sampling module respond to the trigger pulse, and store the sampled data into a receiving buffer area. By using the above method, high-precision full-link interaction of reading and writing is realized, the anti-interference capability reaches a physical limit, the "zero CPU jitter" and extreme computing power liberation in the whole reading and writing process are realized, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the fields of optical communication, automated testing, precision instruments, and embedded systems, specifically to a high-precision I2C bus timing generation and data acquisition method and apparatus. Background Technology

[0002] In fields such as optical communication, automated testing, precision instruments, and embedded systems, the widespread deployment of high-speed optical modules such as QSFP-DD (Quarter Small Form Factor Pluggable Dual Density) and OSFP has placed extremely stringent requirements on the timing parameters of the I2C bus, based on protocol standards such as CMIS (Common Management Interface Specification) and SFF-8636, which govern their internal management interfaces. To ensure the interoperability and reliability of optical modules in complex operating environments, R&D and production line testing require compliance verification and stress testing of the I2C bus timing with nanosecond-level precision.

[0003] Currently, there are two main methods for verifying I2C bus timing signals: Firstly, the traditional approach based on physical oscilloscopes involves sending commands from a host computer to manually detect and measure waveforms using a high-frequency oscilloscope and probes to verify timing parameters. While this approach offers high accuracy, it suffers from complex setup, high equipment costs, low testing efficiency, poor repeatability due to reliance on manual operation, and inability to perform prolonged stress tests.

[0004] Secondly, there is the pure software simulation approach: on a general-purpose operating system (such as Linux), the application directly controls the GPIO pins of the CPU processor, simulating I2C timing bit by bit using methods such as "bit-banging". However, this approach is limited by the scheduling latency of non-real-time operating systems, CPU processor load fluctuations, and the inherent jitter of software simulation. The generated I2C timing signals have low accuracy and large jitter, and cannot meet the stringent testing requirements of high-speed optical modules for nanosecond-level accuracy.

[0005] Therefore, there is an urgent need for a high-precision I2C bus timing generation and data acquisition method and device. Summary of the Invention

[0006] To overcome the existing technical problems, the present invention provides a high-precision I2C bus timing generation and data acquisition method and apparatus.

[0007] The present invention adopts the following technical solution.

[0008] A high-precision I2C bus timing generation and data acquisition method includes the following steps: S1. The CPU processor calculates all the timing information required for a complete protocol interaction, including a write operation phase and a read operation phase, based on the target I2C protocol standard and the test frequency, and encodes it into a continuous data stream stored in the system memory. Each data unit in the data stream has a preset bit width and includes the clock line level state, the data line target level, and the data line direction control indicator. During the write operation phase, the direction control indicator is output valid, and during the read operation phase, the direction control indicator is high-impedance released. S2. The hardware timer generates periodic trigger pulses according to the test frequency. During the write operation phase, the DMA controller responds to the trigger pulses to read data units from the system memory and forces the target level of the data line to be output to the GPIO output register according to the direction control flag. During the read operation phase, the DMA controller responds to the trigger pulses to configure the data line to a high impedance state. At the same time, the input sampling module responds to the same trigger pulses, reads the actual level state of the data line pin at the sampling moment when the clock line is at a high level, and stores the sampled data into the receive buffer. The S3 and GPIO pins output write timing information to the I2C bus according to the level state during the write operation phase, and receive the response data from the slave device to the receive buffer during the read operation phase, thus completing a complete I2C protocol interaction.

[0009] As a further improvement of the present invention, the trigger frequency of the hardware timer is an even multiple of the clock line frequency in the target I2C protocol standard, and the clock line frequency includes at least 100kHz, 400kHz and 1MHz.

[0010] As a further improvement of the present invention, the DMA controller is configured in single-transmission mode. When the data stream is completed and a complete protocol interaction is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and retrieving the slave's response data from the receive buffer, or re-executes S1.

[0011] As a further improvement of the present invention, the DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is completed, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

[0012] As a further improvement of the present invention, S11 is included after S1: starting the hardware timer, DMA controller and input sampling module, and the CPU processor enters sleep state.

[0013] This invention also proposes a high-precision I2C bus timing generation and data acquisition device, employing the high-precision I2C bus timing generation and data acquisition method described above, including: The CPU processor is used to calculate complete timing information, including write and read operation phases, according to the target I2C protocol standard and test frequency, and encode it into a continuous data stream stored in system memory. System memory is used to store data streams; A hardware timer is used to generate periodic trigger pulses based on the test frequency; The DMA controller, connected to the hardware timer and system memory, is used to output data in response to trigger pulses during write operations and to configure the data lines to a high-impedance state in response to trigger pulses during read operations. The input sampling module is connected to the hardware timer and GPIO input terminal. It is used to respond to the trigger pulse during the read operation phase and collect the actual level state of the data line pin. The receiving buffer, connected to the input sampling module, is used to store the sampled data; The GPIO register, connected to the DMA controller, is used to control the level state and high-impedance configuration of the clock line and data line pins.

[0014] As a further improvement of the present invention, the DMA controller is configured in single-transmission mode. When the data stream is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and obtaining the slave's response data from the receive buffer, or regenerating a new data stream.

[0015] As a further improvement of the present invention, the DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is completed, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

[0016] The beneficial effects of this invention are as follows: 1. Breaking the one-way limitation, achieving high-precision end-to-end interaction for integrated reading and writing: It overcomes the fatal bottleneck of traditional pure hardware timing generation schemes, which "can only send, not receive." By innovatively introducing direction control indicators for the data lines and a parallel input sampling module, the device leaps from a unidirectional signal generator to a complete I2C bus master device, completing the entire protocol loop of "issuing write commands → releasing the bus → accurately capturing slave response data" with nanosecond-level precision.

[0017] 2. Absolute precision of data sampling points and interference resistance reaching physical limits: Traditional software simulation, when reading data, is limited by CPU processor interrupt response and code execution delay, making it easy for sampling points to deviate from the "SCL high-level center" specified by the I2C protocol, leading to data reading errors at high frequencies. In this invention, the input sampling module and the DMA controller are controlled by the same hardware timer trigger pulse, enabling hardware-level latching of the SDA data line at the absolute center of the SCL clock line high level, completely eliminating sampling timing deviations and ensuring zero bit error rate when reading data at high speeds such as 1MHz.

[0018] 3. Zero CPU jitter and ultimate computing power liberation throughout the entire read / write process: Whether it's forcibly driving the SDA data line level during the write operation phase or releasing the SDA data line and capturing slave data during the read operation phase, the entire complex state switching and timing control is automatically completed by the hardware timer, DMA controller, and input sampling module. The CPU processor is in a "true sleep" state throughout the entire I2C interaction, not only with computing power utilization approaching zero, but also fundamentally eliminating any microsecond-level jitter caused by operating system scheduling.

[0019] 4. Extremely low-cost hardware reconfiguration, replacing expensive high-end programmable logic devices: In existing technologies, achieving jitter-free I2C bidirectional read / write simulation typically relies on expensive hardware solutions such as FPGAs. This invention cleverly utilizes readily available timers, dual DMA channels, and GPIO registers in ordinary MCUs. Through data flow pre-arrangement and time-division multiplexing mechanisms, it achieves nanosecond-level bidirectional transmit / receive performance comparable to FPGAs. While ensuring extreme accuracy, it reduces hardware costs by several orders of magnitude, making it highly valuable for mass production and commercialization. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the present invention. Detailed Implementation

[0022] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent. To better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product.

[0023] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "middle," and "inner," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, it should be noted that unless otherwise explicitly specified and limited, the terms "installed," "connected," and "joined" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention through specific circumstances.

[0024] It will be understood by those skilled in the art that certain well-known structures and their descriptions may be omitted in the accompanying drawings. The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Reference Figure 1 A high-precision I2C bus timing generation and data acquisition method includes the following steps: S1. The CPU processor calculates all the timing information required for a complete protocol interaction, including a write operation phase and a read operation phase, based on the target I2C protocol standard and the test frequency, and encodes it into a continuous data stream stored in the system memory. Each data unit in the data stream has a preset bit width and includes the clock line level state, the data line target level, and the data line direction control indicator. During the write operation phase, the direction control indicator is output valid, and during the read operation phase, the direction control indicator is high-impedance released. S2. The hardware timer generates periodic trigger pulses according to the test frequency. During the write operation phase, the DMA controller responds to the trigger pulses to read data units from the system memory and forces the target level of the data line to be output to the GPIO output register according to the direction control flag. During the read operation phase, the DMA controller responds to the trigger pulses to configure the data line to a high impedance state. At the same time, the input sampling module responds to the same trigger pulses, reads the actual level state of the data line pin at the sampling moment when the clock line is at a high level, and stores the sampled data into the receive buffer. The S3 and GPIO pins output write timing information to the I2C bus according to the level state during the write operation phase, and receive the response data from the slave device to the receive buffer during the read operation phase, thus completing a complete I2C protocol interaction.

[0026] The method has at least the following beneficial effects: 1. Breaking the one-way limitation, achieving high-precision end-to-end interaction for integrated reading and writing: It overcomes the fatal bottleneck of traditional pure hardware timing generation schemes, which "can only send, not receive." By innovatively introducing direction control indicators for the data lines and a parallel input sampling module, the device leaps from a unidirectional signal generator to a complete I2C bus master device, completing the entire protocol loop of "issuing write commands → releasing the bus → accurately capturing slave response data" with nanosecond-level precision.

[0027] 2. Absolute precision of data sampling points and interference resistance reaching physical limits: Traditional software simulation, when reading data, is limited by CPU processor interrupt response and code execution delay, making it easy for sampling points to deviate from the "SCL high-level center" specified by the I2C protocol, leading to data reading errors at high frequencies. In this invention, the input sampling module and the DMA controller are controlled by the same hardware timer trigger pulse, enabling hardware-level latching of the SDA data line at the absolute center of the SCL clock line high level, completely eliminating sampling timing deviations and ensuring zero bit error rate when reading data at high speeds such as 1MHz.

[0028] 3. Zero CPU jitter and ultimate computing power liberation throughout the entire read / write process: Whether it's forcibly driving the SDA data line level during the write operation phase or releasing the SDA data line and capturing slave data during the read operation phase, the entire complex state switching and timing control is automatically completed by the hardware timer, DMA controller, and input sampling module. The CPU processor is in a "true sleep" state throughout the entire I2C interaction, not only with computing power utilization approaching zero, but also fundamentally eliminating any microsecond-level jitter caused by operating system scheduling.

[0029] 4. Extremely low-cost hardware reconfiguration, replacing expensive high-end programmable logic devices: In existing technologies, achieving jitter-free I2C bidirectional read / write simulation typically relies on expensive hardware solutions such as FPGAs. This invention cleverly utilizes readily available timers, dual DMA channels, and GPIO registers in ordinary MCUs. Through data flow pre-arrangement and time-division multiplexing mechanisms, it achieves nanosecond-level bidirectional transmit / receive performance comparable to FPGAs. While ensuring extreme accuracy, it reduces hardware costs by several orders of magnitude, making it highly valuable for mass production and commercialization.

[0030] As a further improvement of this invention, the trigger frequency of the hardware timer is an even multiple of the clock line frequency in the target I2C protocol standard, and the clock line frequency includes at least 100kHz, 400kHz, and 1MHz. The test frequency corresponds to one of the clock line frequencies.

[0031] 100kHz, 400kHz, and 1MHz are the typical rates for standard mode, fast mode, and high-speed mode, respectively. Using these test frequencies ensures that this method can be directly used for timing generation of the management interfaces of most commercial I2C devices and optical modules (such as QSFP-DD and OSFP), without the need to redesign hardware for different rates, which greatly improves the versatility of the test device.

[0032] After completing one test, the CPU processor only needs to recalculate and generate a data stream at another or the same test frequency, and adjust the trigger period of the hardware timer to immediately start the next round of testing. The entire process is completed automatically without the need for manual instrument replacement or rewiring. It is especially suitable for production line aging test scenarios that require stress scanning at three rates: 100kHz, 400kHz, and 1MHz, significantly reducing the total test time under multi-rate conditions.

[0033] This invention sends trigger pulses directly to the DMA controller via a hardware timer. During the write operation phase, the DMA controller responds to the trigger pulse, reads the data unit from the system memory, and forces the target level of the data line to be output to the GPIO output register according to the direction control flag. During the read operation phase, the DMA controller responds to the trigger pulse, configures the data line to a high-impedance state, and the input sampling module responds to the same trigger pulse. At the sampling moment when the clock line is at a high level, it reads the actual level state of the data line pin and stores the sampled data in the receive buffer. The entire process does not depend on the real-time response capability of the CPU processor.

[0034] Of course, the specific clock line frequency and test frequency can be determined according to the actual situation; this is just a partial example. The listed 100kHz, 400kHz, and 1MHz are only typical values ​​that are at least included, and other frequencies (such as 10kHz, 2.5MHz, etc.) are not excluded.

[0035] This indicates that while covering the clock line frequencies of the three standards mentioned above, this method naturally has the ability to expand to a wider frequency range, and will not increase the processing burden of the CPU processor due to frequency changes—because at all frequencies, the CPU processor only participates in the initial data stream generation stage, and is always in a sleep or freed state during signal generation, so resource efficiency is unrelated to frequency.

[0036] As a further improvement of the present invention, the DMA controller is configured in single-transmission mode. When the data stream is completed and a complete protocol interaction is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and retrieving the slave's response data from the receive buffer, or re-executes S1.

[0037] This method enables the CPU processor to automatically encode and generate the next required data stream after completing the test, and automatically execute S2 and S3. This achieves rapid deployment and repeated execution of the test process, greatly improving R&D and testing efficiency and significantly reducing costs.

[0038] Specifically, in single-transfer mode, the DMA controller automatically stops after completely outputting all the timing data required for a single I2C protocol interaction and notifies the CPU. The CPU can then choose to immediately stop the hardware timer and retrieve the slave's response data from the receive buffer, based on the needs of the test process. This prevents the hardware timer from continuing to send invalid trigger pulses, which could cause GPIO pin malfunctions or bus conflicts.

[0039] As a further improvement of the present invention, the DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is completed, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

[0040] This method enables high-precision, repeatable stress testing over extended periods. In cyclic transfer mode, the DMA controller automatically resets and restarts after completing a full data stream output, without requiring the CPU to respond to any interrupts or reconfigure registers. Each data unit within each cycle is generated by the same hardware path and memory source, and the trigger pulse is stably provided by the same hardware timer. Therefore, even after running continuously for hours or days, the edge alignment error of the I2C timing signal output from the first cycle to the 1 millionth cycle can still be controlled within nanoseconds, fundamentally eliminating the periodic jitter or gaps that may be introduced by software-reloaded data streams.

[0041] Furthermore, in loop transmission mode, the CPU processor only intervenes during the initial startup and after the entire loop ends, with zero interruptions in between. This is particularly critical for scenarios that need to execute the same operation tens of thousands of times continuously at a rate of 400kHz or 1MHz, reducing CPU processor utilization from nearly 100% to almost zero while avoiding interrupt latency interference with timing.

[0042] Users can set the loop count threshold before testing according to their needs. Once the preset value is reached, the DMA controller's internal or linked counter hardware can automatically stop triggering requests or generate a completion interrupt, notifying the CPU processor to receive the slave's response data into the receive buffer to record the test results. This achieves a controllable and automated closed-loop stress test.

[0043] When testing multiple optical modules simultaneously, each channel can be configured with an independent DMA controller channel, hardware timer, and preset number of loops. Each channel operates in cyclic transfer mode, requiring no CPU coordination or synchronization, and can independently execute repetitive test tasks according to its preset number of loops. When one channel completes its loop count first, it generates an interrupt to notify the CPU, while the other channels continue running. This architecture allows the CPU to intervene only at the start and end of the test, significantly improving the throughput and real-time performance of the multi-channel automated testing system.

[0044] As a further improvement of the present invention, S11 is included after S1: starting the hardware timer, DMA controller and input sampling module, and the CPU processor enters sleep state.

[0045] When the CPU processor does not need to perform multiple test tasks or data analysis, it can enter a sleep state, significantly reducing power consumption and testing costs. Specifically, when the CPU processor enters sleep mode, it no longer actively accesses system memory or cache. During the entire process of I2C timing signals being independently generated and acquired by the DMA controller, input sampling module, and hardware timer, the CPU processor remains silent, thus avoiding dynamic power consumption caused by instruction execution, cache line filling, or bus sniffing. For scenarios requiring long-term I2C stress testing, this sleep mechanism can reduce the CPU processor's power consumption to milliwatts or even microwatts, significantly reducing the heat dissipation pressure and power supply requirements of the testing equipment.

[0046] Thanks to its low power consumption, which enables mobile testing, this invention can be deployed in battery-powered scenarios such as handheld I2C protocol analyzers, field maintenance tools, or wireless sensor network nodes. When generating waveforms for I2C buses for extended periods or simulating devices, it does not rapidly deplete the battery, significantly extending field operation time.

[0047] Furthermore, thanks to its low power consumption, more test channels can be stacked within a compact chassis, enabling the construction of a high-throughput parallel test system. When a CPU processor needs to test multiple slave devices simultaneously, each channel can be configured with an independent hardware timer, DMA controller, input sampling module, and corresponding GPIO data register. During the startup phase, the CPU processor sequentially encodes each data stream, stores it in different areas of system memory, and configures the DMA controller and hardware timer for each channel. Subsequently, the CPU processor uniformly starts the hardware timers, input sampling modules, and DMA controllers of all channels and immediately enters a sleep state.

[0048] Each channel's DMA controller and input sampling module independently receive trigger pulses from their corresponding hardware timers, allowing for the generation of I2C timing signals across multiple channels in complete parallel and without interference. During CPU sleep, no bit-level transmissions are involved, eliminating the need for channel switching via interrupts or polling, thus achieving true "one-to-many" parallel testing. Compared to the serial operation of software simulation schemes where the CPU needs to toggle GPIO pins bit by bit channel by channel, this method increases parallel throughput by a factor equal to the number of channels, and the increase in the number of channels does not lead to an increase in CPU load.

[0049] Furthermore, when multiple CPU processors are integrated within the system, each CPU processor can manage its own set of test channels according to the above mode. Assuming a single CPU processor can simultaneously drive M independent channels, and there are N CPU processors (or CPU cores) in the system, the total number of parallel test channels can reach N×M. After each CPU processor completes the initialization of its respective channel group and starts all hardware timers, input sampling modules, and DMA controllers, it can independently enter a sleep state (or not enter a sleep state if a single CPU processor has a sufficient number of independent channels). This enables N×M times higher throughput parallel I2C bus timing generation and data acquisition testing. This architecture is particularly suitable for large-scale production line aging tests, high-density optical module parallel verification, and multi-node sensor array synchronous excitation scenarios. Without adding an additional main control chip, it significantly improves the test throughput per unit time while maintaining extremely low overall power consumption and low heat dissipation requirements.

[0050] For tests with high hardware execution environment requirements, by putting the CPU processor into sleep mode, there are no other master devices in the system except for the DMA controller, input sampling module and hardware timer, thus creating a clean hardware execution environment for I2C timing generation, further reducing the sources of timing jitter uncertainty, and is especially suitable for nanosecond-level calibration tests with stringent jitter requirements.

[0051] This invention also proposes a high-precision I2C bus timing generation and data acquisition device, employing the high-precision I2C bus timing generation and data acquisition method described above, including: The CPU processor is used to calculate complete timing information, including write and read operation phases, according to the target I2C protocol standard and test frequency, and encode it into a continuous data stream stored in system memory. System memory is used to store data streams; A hardware timer is used to generate periodic trigger pulses based on the test frequency; The DMA controller, connected to the hardware timer and system memory, is used to output data in response to trigger pulses during write operations and to configure the data lines to a high-impedance state in response to trigger pulses during read operations. The input sampling module is connected to the hardware timer and GPIO input terminal. It is used to respond to the trigger pulse during the read operation phase and collect the actual level state of the data line pin. The receiving buffer, connected to the input sampling module, is used to store the sampled data; The GPIO register, connected to the DMA controller, is used to control the level state and high-impedance configuration of the clock line and data line pins.

[0052] This device breaks down the I2C timing generation task into independent hardware modules. This decoupled design ensures that the overall throughput of the device is no longer limited by the processing speed of a single module. Compared to the software approach of setting the SCL clock line and SDA data line separately using a read-modify-write sequence, the DMA controller, input sampling module, and hardware timer avoid the risk of half-state interruption or preemption by another task, fundamentally guaranteeing the strict synchronization of clock and data line level changes. When multiple I2C slave devices need to be tested simultaneously, the CPU initializes and starts the data stream for each unit separately. Subsequently, each unit operates completely independently, and the I2C timing signals between them will not interfere with each other due to bus arbitration.

[0053] As a further improvement of the present invention, the DMA controller is configured in single-transmission mode. When the data stream is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and obtaining the slave's response data from the receive buffer, or regenerating a new data stream.

[0054] As a further improvement of the present invention, the DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is completed, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

[0055] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high-precision I2C bus timing generation and data acquisition method, characterized in that, Includes the following steps: S1. The CPU processor calculates all the timing information required for a complete protocol interaction, including a write operation phase and a read operation phase, based on the target I2C protocol standard and the test frequency, and encodes it into a continuous data stream stored in the system memory. Each data unit in the data stream has a preset bit width and includes the clock line level state, the data line target level, and the data line direction control identifier. During the write operation phase, the direction control identifier is output valid, and during the read operation phase, the direction control identifier is high-impedance released. S2. The hardware timer generates periodic trigger pulses according to the test frequency; During the write operation phase, the DMA controller responds to the trigger pulse to read the data unit from the system memory and forces the target level of the data line to be output to the GPIO output register according to the direction control flag; during the read operation phase, the DMA controller responds to the trigger pulse to configure the data line to a high impedance state, and the input sampling module responds to the same trigger pulse to read the actual level state of the data line pin at the sampling moment when the clock line is at a high level, and stores the sampled data into the receive buffer. S3 and GPIO pins output write timing to the I2C bus according to the level state of the write operation phase, and receive the response data from the slave device to the receive buffer during the read operation phase, thus completing a complete I2C protocol interaction.

2. The high-precision I2C bus timing generation and data acquisition method according to claim 1, characterized in that, The trigger frequency of the hardware timer is an even multiple of the clock line frequency in the target I2C protocol standard, and the clock line frequency includes at least 100kHz, 400kHz and 1MHz.

3. The high-precision I2C bus timing generation and data acquisition method according to claim 1, characterized in that, The DMA controller is configured for single-transmission mode. When the data stream is transmitted and a complete protocol interaction is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and retrieving the slave's response data from the receive buffer, or re-executes S1.

4. The high-precision I2C bus timing generation and data acquisition method according to claim 1, characterized in that, The DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is transferred, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

5. The high-precision I2C bus timing generation and data acquisition method according to claim 1, characterized in that, Following S1, S11 is also included: starting the hardware timer, DMA controller, and input sampling module, and the CPU processor enters a sleep state.

6. A high-precision I2C bus timing generation and data acquisition device, characterized in that, The high-precision I2C bus timing generation and data acquisition method as described in any one of claims 1-5 includes: The CPU processor is used to calculate complete timing information, including write and read operation phases, according to the target I2C protocol standard and test frequency, and encode it into a continuous data stream stored in system memory. System memory, used to store the data stream; A hardware timer is used to generate periodic trigger pulses according to the test frequency; The DMA controller, connected to the hardware timer and system memory, is used to output data in response to trigger pulses during the write operation phase and to configure the data line to a high-impedance state in response to trigger pulses during the read operation phase. An input sampling module, connected to the hardware timer and GPIO input, is used to respond to the trigger pulse during the read operation phase and collect the actual level state of the data line pins. A receiving buffer, connected to the input sampling module, is used to store the sampled data; The GPIO register, connected to the DMA controller, is used to control the level state and high-impedance configuration of the clock line pin and data line pin.

7. The high-precision I2C bus timing generation and data acquisition device according to claim 6, characterized in that, The DMA controller is configured for single-transmission mode. When the data stream is completed, the DMA controller generates a transmission completion interrupt to the CPU processor. The CPU processor responds to the transmission completion interrupt by stopping the hardware timer and obtaining the slave's response data from the receive buffer, or regenerating a new data stream.

8. The high-precision I2C bus timing generation and data acquisition device according to claim 6, characterized in that, The DMA controller is configured in a cyclic transfer mode. For continuous write timing scenarios that only include the write operation phase, after the data stream is transferred, the DMA controller re-outputs the data stream according to the trigger pulse until the number of times the DMA controller outputs the data stream reaches the preset number of cycles.

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