A method and circuit for adjusting a termination resistance of a high-speed serial bus receiver

Abstract

The application belongs to terminal resistance adjustment technology, and particularly relates to a high-speed serial bus receiving terminal resistance adjustment method and an adjustment circuit, wherein the adjustment method comprises the following steps: setting a corresponding matching relationship between a receiving terminal resistance module and an equivalent resistance control signal of a receiving terminal resistance array module, so that the equivalent resistances of the two modules under the control of the control signal are in a determined relationship; applying the same size of current to the receiving terminal resistance array module and an external reference resistance respectively, so as to generate corresponding state voltage and terminal voltage; comparing the state voltage and the terminal voltage, and continuously regulating the equivalent resistance control signal of the receiving terminal resistance array module according to the comparison result until the equivalent resistance of the receiving terminal resistance array module reaches the resistance value of the external reference resistance; meanwhile, under the control of the control signal, the equivalent resistance of the receiving terminal resistance module is accurately matched with the equivalent resistance of the regulated receiving terminal resistance array module, so that the accurate regulation of the terminal resistance value is finally realized.

Description

Technical Field

[0001] This application belongs to the field of high-speed serial bus receiver terminal resistor adjustment technology, specifically relating to a high-speed serial bus receiver terminal resistor adjustment method and adjustment circuit. Technical Background

[0002] With the continuous upgrading of Universal Serial Bus (USB) versions, its data transmission rate has reached gigabit levels. Under increasingly higher data transmission rates, the non-ideal characteristics of the channel lead to more severe distortion of the input signal at the receiving end, and the requirements for signal integrity in high-frequency signal transmission are also increasing.

[0003] High-speed signals will be reflected when they encounter connection nodes, sudden load changes, or impedance discontinuities at connection terminals during transmission. The reflection is related to the amount of impedance change. When a signal travels from a region with instantaneous impedance Z1 to a region with instantaneous impedance Z2, its reflection coefficient is: Signal reflection can cause overshoot, ringing, and jitter in the original signal. The signal level may exceed the noise margin of the data receiver, leading to false triggering. Therefore, impedance matching circuits are needed to mitigate the impact of impedance abrupt changes on signal transmission. Terminating resistors are crucial units in circuits for impedance matching and improving signal stability. Using terminating resistors can improve signal quality and reliability, reduce waveform distortion, suppress signal amplitude variations, and reduce signal loss on transmission lines. Providing good impedance matching through terminating resistors ensures signal stability and consistency. However, currently, the adjustment of terminating resistors is not precise enough to meet the matching requirements of different environments. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a method and circuit for adjusting the terminating resistor of a high-speed serial bus receiver, which is used to adjust the resistance value of the terminating resistor of a high-speed serial bus receiver to improve the signal integrity of high-frequency signal transmission.

[0005] The technical solution of this invention to solve the above-mentioned technical problems is: a method for adjusting the terminating resistor of a high-speed serial bus receiver, which includes the following steps: (1) Set the corresponding matching relationship between the equivalent resistance control signals of the receiving end terminal resistor module and the receiving end resistor array module so that the equivalent resistance values ​​of the two modules under the control of the control signals are in a definite relationship. (2) Apply the same current to the receiver resistor array module and the external reference resistor respectively to generate the corresponding state voltage and terminal voltage; (3) Compare the above state voltage and terminal voltage, and continuously adjust the equivalent resistance control signal of the receiving end resistor array module according to the comparison result until the equivalent resistance of the receiving end resistor array module reaches the resistance value of the external reference resistor. (4) Under the control of the control signal, the equivalent resistance of the receiver terminal resistor module is precisely matched with the equivalent resistance value of the regulated receiver resistor array module.

[0006] Preferably, the equivalent resistance value of the receiving end terminal resistor module is controlled by a seven-bit control signal, and the equivalent resistance value of the receiving end resistor array module is controlled by a six-bit control signal. The six-bit control signal and the lower six bits of the seven-bit control signal share the same control logic.

[0007] Preferably, when the highest bit control signal of the receiving end terminating resistor module is connected and enabled, the remaining six bits of the receiving end terminating resistor module and the six bits of the receiving end resistor array module, under the action of shared control logic, maintain a definite multiple relationship between the equivalent resistance value of the receiving end resistor array module and the equivalent resistance value of the receiving end terminating resistor module.

[0008] This invention also provides a high-speed serial bus receiver termination resistor adjustment circuit, including a receiver termination resistor module, a receiver resistor array module, an external reference resistor, a reference current generation module, and a comparator module, wherein: The receiver terminating resistor module is used as a high-speed serial bus receiver terminating resistor. The receiver resistor array module is used to measure and adjust the equivalent resistance value of the receiver terminal resistor module. The reference current generation module is used to generate a reference current and apply it to an external reference resistor to generate a terminal voltage; it is also used to mirror the reference current to a mirror current and apply it to the receiving resistor array module to generate a status voltage. An external reference resistor is connected to generate a reference current in conjunction with the reference current generation module, and at the same time assists in measuring the equivalent resistance value of the receiver resistor array module. The comparator module is used to compare the state voltage and the terminal voltage, and continuously adjusts the equivalent resistance control signal of the resistor array module according to the comparison result.

[0009] Preferably, the comparator module is a single-ended time-domain comparator that uses the law of conservation of charge for comparison.

[0010] Preferably, the single-ended time-domain comparator completes a comparison in two time steps, wherein the terminal voltage is sampled and buffered in the first step, and the state voltage is sampled and compared with the buffered terminal voltage in the second step.

[0011] Preferably, the comparator module includes a five-transistor operational amplifier composed of NMOS transistors NM119~NM121 and PMOS transistors PM15 and PM16. The sources of PM15 and PM16 are both connected to the power supply vphreg. The gate and drain of PMOS transistor PM15 are connected, and also connected to the gate of PMOS transistor PM16 and the drain of NMOS transistor NM119. NM119 is the non-inverting input transistor of the five-transistor operational amplifier, and its gate is connected to the second terminal of resistor R9. The first terminal of the resistor R10 is connected to the second terminal of capacitor C1, and the first terminal of capacitor C1 is connected to the second terminal of resistor R10. A grounding capacitor C2 is connected at this connection point. The first terminal of resistor R10 is connected to the drain of NMOS transistors NM122 and NM123. The source of NM122 is connected to the first terminal (vfb) of an external reference resistor. The gate of NM122 is connected to the control signal r_h. The source of NM123 is connected to the input terminal (rin) of the receiver resistor array module. The gate of NM123 is connected to the control signal rx_h. NM122 and NM123 are used to control the comparator's comparison signal selection input. The gate of NM120 is the inverting input of a five-transistor operational amplifier, connected to the first terminal of resistor R9 and the source of NMOS transistor NM124. The second terminal of resistor R9 is connected to the grounding capacitor C3. The gate of NM124 is controlled by r_h. The control signal regulates the voltage, and its drain is connected to a voltage divider network formed by two resistors R11 and PMOS transistor PM17. A five-transistor operational amplifier, along with PM18 and NM125, constitutes a two-stage operational amplifier. The drains of PMOS transistor PM16 and NMOS transistor NM120 are connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gate of PM18 and the first terminal of capacitor C4. The second terminal of capacitor C4 is connected to the source of NMOS transistor NM127. The gate of NM127 is connected to the control signal r_h. The drain of NM127 is connected to the first terminal of resistor R12. The second terminal of resistor R12 is connected to the drains of PMOS transistor PM18 and NMOS transistors NM125~NM126. The circuit consists of the gates of PMOS transistor PM20 and NMOS transistor NM128. The source of PMOS transistor PM18 is connected to the power supply vphreg. The gate of NMOS transistor NM126 is connected to the control signal r_h, and its source is connected back to the gate of the non-inverting input transistor NM119. The output vom1 of the second-stage operational amplifier is inverted and output to the final output terminal comp_result of the comparator via an inverter structure composed of PM20 and NM128. At the same time, this output terminal is also connected to the drain of NMOS transistor NM129. The source of NM129 is grounded, and its gate is connected to the control signal r_h. The inverter is enabled by the gate signal r_h of PM19, and the source of PM19 is connected to the power supply vphreg.PMOS transistor PM21, resistor R13, and NM130 are used to generate the bias current ibias. The source of PM21 is connected to the power supply vphreg, the gate is connected to the control signal pwron_hn, and the drain is connected to the first terminal of resistor R13. The second terminal of resistor R13 is connected to the drain of NMOS transistor NM130. The gate and drain of NM130 are connected, and also connected to the gates of NMOS transistors NM121 and NM125. The sources of NMOS transistors NM130, NM121, and NM125 are all grounded.

[0012] As can be seen from the above technical solution, this invention, by reasonably setting the resistance values ​​of the receiving-end resistor array module and the receiving-end terminating resistor module, ensures that the equivalent resistance values ​​of the two modules maintain a definite relationship under the control of the equivalent resistance value control signal. Simultaneously, the generated reference current and its mirror current flow through the external reference resistor and the receiving-end resistor array module, respectively, generating corresponding terminal voltage and status voltage. These terminal voltage and status voltage are sampled and compared, and the equivalent resistance value of the receiving-end resistor array module is adjusted according to the comparison result until its equivalent resistance value approaches that of the external reference resistor, thereby adjusting the terminating resistance of the receiving-end terminating resistor module to the desired value. Therefore, this invention can precisely adjust the receiving-end terminating resistor value under different environments, offering high flexibility and controllability, meeting the terminating resistance matching requirements under various conditions, and ensuring signal integrity. Attached Figure Description

[0013] Figure 1 The diagram shown is a structural block diagram of the adjustment circuit of the present invention.

[0014] Figure 2 The diagram shown is a schematic of the receiver terminal resistor module of the present invention.

[0015] Figure 3 The diagram shown is a schematic of the receiver resistor array module of the present invention.

[0016] Figure 4 The diagram shown is a schematic representation of the reference current generation module of the present invention.

[0017] Figure 5 The diagram shown is a structural schematic of the comparator module of the present invention. Detailed Implementation

[0018] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] refer to Figures 1 to 5 This invention provides a method for adjusting the terminating resistor of a high-speed serial bus receiver, which includes the following steps: First, a matching relationship is established between the equivalent resistance control signals of the receiving end terminating resistor module and the receiving end resistor array module, ensuring a definite relationship between the equivalent resistance values ​​of the two modules under the control signal. Equal currents are applied to the receiving end resistor array module and the external reference resistor, generating corresponding state voltages and terminal voltages. These state voltages and terminal voltages are compared, and the equivalent resistance control signal of the receiving end resistor array module is continuously adjusted based on the comparison result until the equivalent resistance of the receiving end resistor array module reaches the resistance value of the external reference resistor. Simultaneously, under the control signal, the equivalent resistance of the receiving end terminating resistor module precisely matches the adjusted equivalent resistance value of the receiving end resistor array module, ultimately achieving precise adjustment of the terminating resistor value.

[0020] Specifically, by reasonably setting the correspondence between the control signals of the receiver terminating resistor module and the receiver resistor array module, the size of the terminating resistor can be determined simply by using an external reference resistor to determine the equivalent resistance of the receiver resistor array module. Given a certain control signal code value for the receiver resistor array module, the state voltage of the receiver resistor array module under this control code is compared with the voltage at the external reference resistor terminal. Based on the initial comparison result, the control signal code value of the receiver resistor array module is adjusted to change its equivalent resistance value, and the comparison is repeated. Whether the comparison result state flips determines whether the control signal of the receiver resistor array module is adjusted again, until the adjusted control signal causes the comparison result state to flip. The control signal code value that causes the comparison result state to flip is the control signal code value corresponding to the target resistance value. Under this control signal, the equivalent resistance value of the receiver resistor array module is close to the resistance value of the external reference resistor, and the equivalent resistance of the receiver terminating resistor module will also be precisely matched accordingly, ultimately achieving the control of the receiver terminating resistor.

[0021] During implementation, the equivalent resistance of the receiving end terminal resistor module is controlled by a seven-bit control signal, and the equivalent resistance of the receiving end resistor array module is controlled by a six-bit control signal. The six-bit control signal shares control logic with the lower six bits of the seven-bit control signal. When the highest bit control signal of the receiving end terminal resistor module is connected and enabled, the remaining six bits of the receiving end terminal resistor module and the six bits of the receiving end resistor array module, under the action of the shared control logic, maintain a definite multiple relationship between the equivalent resistance of the receiving end resistor array module and the equivalent resistance of the receiving end terminal resistor module, such as a four-fold relationship.

[0022] The present invention also provides a high-speed serial bus receiver termination resistor adjustment circuit designed according to the above method, such as... Figure 1As shown, it specifically includes a receiver terminating resistor module, a receiver resistor array module, an external reference resistor, a reference current generation module, and a comparator module. The equivalent resistance value of the receiver terminating resistor module is controlled by a seven-bit control signal, and the equivalent resistance value of the receiver resistor array module is controlled by a six-bit control signal. The six-bit control signal shares the same control logic as the lower six bits of the seven-bit control signal of the receiver terminating resistor module. The reference current generation module generates a reference current `ical_ext` to the external reference resistor and a mirrored current `ical` to the receiver resistor array module. The terminal resistor array module generates a state voltage vrin to the comparator module under the action of the mirror current and the six-bit control signal; the external reference resistor generates a terminal voltage vfb to the comparator module under the action of the reference current; the comparator module determines the magnitude of the equivalent resistance value of the receiving terminal resistor array module relative to the resistance value of the external reference resistor by comparing the aforementioned state voltage vrin and terminal voltage vfb, and adjusts the resistance control signal of the receiving terminal resistor array module according to the output state of the comparator module comparison until its equivalent resistance value is close to the external reference resistor, and at the same time, the receiving terminal resistor module will also be precisely matched accordingly.

[0023] like Figure 2 As shown, the receiving-end terminating resistor module provided in this embodiment is used as a high-speed serial bus receiving-end terminating resistor. All resistors in this module share a common terminal `rout`, the gates of all NMOS transistors are connected to a control signal in `cal_h<6:0>`, and the sources of all NMOS transistors are grounded to GND. The connection of each resistor in the receiving-end terminating resistor module is controlled by the gate control code of the NMOS switch. Each resistor and its corresponding NMOS switch are connected in series and then in parallel to form the entire receiving-end terminating resistor module. Under the control of the control signal, the more resistors connected to the receiving-end terminating resistor module, the smaller the equivalent resistance of the module.

[0024] like Figure 3 As shown, the receiver resistor array module provided in this embodiment is used to measure and adjust the equivalent resistance value of the current receiver termination resistor. Through flexible configuration and precise control of the receiver resistor array module's resistance value control signal, fine adjustment of the termination resistor value can be achieved to meet impedance matching requirements under different operating conditions. All resistors in this module share a common terminal rin, the gates of all NMOS transistors are connected to one of the control signals in rcal_h<5:0>, and the sources of all NMOS transistors are grounded to GND. The connection of each resistor in the receiver resistor array module is controlled by the gate control code of the NMOS switch. Each resistor and its corresponding NMOS switch are connected in series and then in parallel to form the entire receiver resistor array module. Under the control of the control signal, the more resistors connected to the receiver resistor array module, the smaller the equivalent resistance value of the module.

[0025] In this embodiment, it is worth noting that since the resistance control signals of the receiving end resistor array module and the receiving end terminating resistor module are controlled by a partially shared control logic, under certain conditions, the equivalent resistance values ​​of the two modules exhibit a definite multiple relationship. Specifically, when the following conditions are met: the highest bit of the seven-bit resistance control signal of the receiving end terminating resistor module is enabled, and the receiving end resistor array module is connected to a vphreg power supply, under the control of the shared control logic, the equivalent resistance values ​​of the receiving end resistor array module and the receiving end terminating resistor module exhibit a four-fold relationship.

[0026] like Figure 4 As shown, the reference current generation module provided in this application embodiment is used to generate a precise reference current. It consists of a resistor divider circuit, a folded cascode amplifier, an external reference resistor, and a cascode current mirror. The resistor divider circuit generates two different preset reference voltages as reference voltages for amplifier clamping, and the output of the two reference voltages is controlled by an NMOS switch. The folded cascode amplifier is used to clamp the preset reference voltage. The reference voltage output by the resistor divider module is input from the non-inverting input terminal vip of the amplifier. The amplifier output is connected to a common-gate PMOS transistor to form a two-stage operational amplifier. The common-gate PMOS transistor is fed back to the inverting input terminal vin of the amplifier through a switching circuit. At the same time, the inverting input terminal vin of the amplifier is also connected to a 200-ohm external reference resistor resref connected to ground and the vfb pin is led out to the comparator module. The generated reference current is the clamped reference voltage divided by the 200-ohm external reference resistor resref. The generated reference current is mirrored as ical by the cascode current mirror and applied to the receiver resistor array module to generate the comparison state voltage.

[0027] like Figure 5As shown, the comparator module provided in this embodiment is a single-ended time-domain comparator based on the principle of charge conservation. NMOS transistors NM119~NM121 and PMOS transistors PM15 and PM16 constitute a five-transistor operational amplifier. The sources of PM15 and PM16 are both connected to the power supply vphreg. The gate and drain of PMOS transistor PM15 are connected, and also connected to the gate of PMOS transistor PM16 and the drain of NMOS transistor NM119. NM119 is the non-inverting input transistor of the five-transistor operational amplifier, and its gate is connected to the second resistor R9. The first terminal of R9 is connected to the second terminal of capacitor C1, the first terminal of capacitor C1 is connected to the second terminal of resistor R10, and a pair of ground capacitors C2 are connected at this connection node. The first terminal of resistor R10 is connected to the drain of NMOS transistors NM122 and NM123. The source of NM122 is connected to the first terminal of the aforementioned external reference resistor, i.e., the VFB pin. The gate of NM122 is connected to the control signal r_h. The source of NM123 is connected to the input terminal rin of the aforementioned receiver resistor array module, and the gate of NM123 is connected to the control signal rx_h. NM122 and NM123 are used to control the comparator's comparison signal selection input; the gate of NM120 is the inverting input of a five-transistor op-amp, connected to the first terminal of resistor R9 and the source of NMOS transistor NM124. The second terminal of resistor R9 is connected to a grounded capacitor C3. The gate of NM124 is controlled by the r_h control signal, and its drain is connected to a voltage divider network formed by two resistors R11 and PMOS transistor PM17; the five-transistor op-amp, PM18, and NM125... This forms a two-stage operational amplifier. The drains of PMOS transistor PM16 and NMOS transistor NM120 are connected and then connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gate of PM18 and the first terminal of capacitor C4. The second terminal of capacitor C4 is connected to the source of NMOS transistor NM127. The gate of NM127 is connected to the control signal r_h. The drain of NM127 is connected to the first terminal of resistor R12. The second terminal of resistor R12 is connected to the drains of PMOS transistors PM18 and NMOS transistors NM125~NM126, as well as the gates of PMOS transistors PM20 and NMOS transistor NM128. The source of PMOS transistor PM18 is connected to the power supply vphreg. The gate of NMOS transistor NM126 is connected to the control signal r_h, and its source is connected back to the gate of the non-inverting input transistor 119. The output vom1 of the two-stage operational amplifier is connected via PM20 and NM128. The inverter structure is inverted and outputs to the comparator's final output terminal comp_result. This output terminal is also connected to the drain of the NMOS transistor NM129. The source of NM129 is grounded, and the gate is connected to the control signal r_h. The inverter is enabled by the gate signal r_h of PM19, and the source of PM19 is connected to the power supply vphreg.PMOS transistor PM21, resistor R13, and NM130 are used to generate the bias current ibias. The source of PM21 is connected to the power supply vphreg, the gate is connected to the control signal pwron_hn, and the drain is connected to the first terminal of resistor R13. The second terminal of resistor R13 is connected to the drain of NMOS transistor NM130. The gate and drain of NM130 are connected and simultaneously connected to the gates of NMOS transistors NM121 and NM125. The sources of NMOS transistors NM130, NM121, and NM125 are all grounded. Capacitor C4 and resistor R12 are used for Miller compensation of the second-stage operational amplifier. The generated bias current ibias powers the comparator module and the aforementioned reference current generation module. Under this connection, the comparator module performs single-ended time-domain comparison using the law of charge conservation. One comparison is completed in two time steps. In the first step, the voltage vfb at the external reference resistor is sampled and buffered. At this time, the charge Q1 stored in capacitor C1 and the charge Q2 stored in capacitor C3 are respectively:

[0028] In the second sampling, the state voltage Vrin of the receiver resistor array module is acquired. At this time, the charge Q1* stored in C1 and the charge Q2* stored in capacitor C3 are respectively:

[0029] Due to charge conservation, Q1 = Q1*, Q2 = Q2*, and the final output vom1 during the second comparison is:

[0030] Where Av is the op-amp gain. vom1 is inverted by an inverter to obtain the final output comp_result.

[0031] It should be noted that the control signals r_h and rx_h in the high-speed serial bus receiver terminal resistor adjustment circuit provided in this embodiment are a pair of inverted signals, that is, when r_h is high, rx_h is low, so that the comparator completes one comparison in two time steps.

Claims

1. A method for adjusting the terminating resistor of a high-speed serial bus receiver, characterized in that... Includes the following steps: (1) Set the corresponding matching relationship between the equivalent resistance control signals of the receiving end terminal resistor module and the receiving end resistor array module so that the equivalent resistance values ​​of the two modules under the control of the control signals are in a definite relationship. (2) Apply the same current to the receiver resistor array module and the external reference resistor respectively to generate the corresponding state voltage and terminal voltage; (3) Compare the above state voltage and terminal voltage, and continuously adjust the equivalent resistance control signal of the receiving end resistor array module according to the comparison result until the equivalent resistance of the receiving end resistor array module reaches the resistance value of the external reference resistor. (4) Under the control of the control signal, the equivalent resistance of the receiver terminal resistor module is precisely matched with the equivalent resistance value of the regulated receiver resistor array module.

2. The high-speed serial bus receiver termination resistor adjustment method according to claim 1, characterized in that: The equivalent resistance value of the receiving end terminal resistor module is controlled by a seven-bit control signal, and the equivalent resistance value of the receiving end resistor array module is controlled by a six-bit control signal. The six-bit control signal and the lower six bits of the seven-bit control signal share the control logic.

3. The high-speed serial bus receiver termination resistor adjustment method according to claim 2, characterized in that: When the highest bit control signal of the receiving end terminating resistor module is connected and enabled, the remaining six bits of the receiving end terminating resistor module and the six bits of the receiving end resistor array module, under the action of the shared control logic, maintain a definite multiple relationship between the equivalent resistance value of the receiving end resistor array module and the equivalent resistance value of the receiving end terminating resistor module.

4. An adjustment circuit designed according to the high-speed serial bus receiver termination resistor adjustment method according to claim 1, 2, or 3, comprising a receiver termination resistor module, a receiver resistor array module, an external reference resistor, a reference current generation module, and a comparator module, characterized in that: The receiver terminating resistor module is used as a high-speed serial bus receiver terminating resistor. The receiver resistor array module is used to measure and adjust the equivalent resistance value of the receiver terminal resistor module. The reference current generation module is used to generate a reference current and apply it to an external reference resistor to generate a terminal voltage. Simultaneously, it is used to mirror the reference current as the mirror current and apply it to the receiver resistor array module to generate a state voltage; An external reference resistor is connected to generate a reference current in conjunction with the reference current generation module, and at the same time assists in measuring the equivalent resistance value of the receiver resistor array module. The comparator module is used to compare the state voltage and the terminal voltage, and continuously adjusts the equivalent resistance control signal of the resistor array module according to the comparison result.

5. The adjustment circuit according to claim 4, characterized in that: The comparator module is a single-ended time-domain comparator that uses the law of conservation of charge for comparison.

6. The regulating circuit according to claim 5, characterized in that: The single-ended time-domain comparator completes a comparison in two time steps, wherein the terminal voltage is sampled and buffered in the first step, and the state voltage is sampled and compared with the buffered terminal voltage in the second step.

7. The regulating circuit according to claim 4, 5, or 6, characterized in that: The comparator module includes a five-transistor operational amplifier consisting of NMOS transistors NM119~NM121 and PMOS transistors PM15 and PM16. The sources of PM15 and PM16 are both connected to the power supply vphreg. The gate and drain of PMOS transistor PM15 are connected, and then connected to the gate of PMOS transistor PM16 and the drain of NMOS transistor NM119. NM119 is the non-inverting input transistor of the five-transistor operational amplifier. Its gate is connected to the second terminal of resistor R9. The first terminal of resistor R9 is connected to the second terminal of capacitor C1. The first terminal of capacitor C1 is connected to the second terminal of resistor R10, and a grounding capacitor C2 is connected at this connection point. The first terminal of resistor R10 is connected to NMOS transistor NM122. The drain of NM123 and the source of NM122 are connected to the first terminal (VFB) of the external reference resistor. The gate of NM122 is connected to the control signal r_h. The source of NM123 is connected to the input terminal (Rin) of the receiver resistor array module. The gate of NM123 is connected to the control signal rx_h. NM122 and NM123 are used to control the comparator's comparison signal selection input. The gate of NM120 is the inverting input transistor of a five-transistor operational amplifier, connected to the first terminal of resistor R9 and the source of NMOS transistor NM124. The second terminal of resistor R9 is connected to the ground capacitor C3. The gate of NM124 is controlled by r_h. The control signal regulates the voltage, and its drain is connected to a voltage divider network formed by two resistors R11 and PMOS transistor PM17. A five-transistor operational amplifier, along with PM18 and NM125, constitutes a two-stage operational amplifier. The drains of PMOS transistor PM16 and NMOS transistor NM120 are connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gate of PM18 and the first terminal of capacitor C4. The second terminal of capacitor C4 is connected to the source of NMOS transistor NM127. The gate of NM127 is connected to the control signal r_h. The drain of NM127 is connected to the first terminal of resistor R12. The second terminal of resistor R12 is connected to the drains of PMOS transistor PM18 and NMOS transistors NM125~NM126. The circuit consists of the gates of PMOS transistor PM20 and NMOS transistor NM128. The source of PMOS transistor PM18 is connected to the power supply vphreg. The gate of NMOS transistor NM126 is connected to the control signal r_h, and its source is connected back to the gate of the non-inverting input transistor NM119. The output vom1 of the second-stage operational amplifier is inverted and output to the final output terminal comp_result of the comparator via an inverter structure composed of PM20 and NM128. At the same time, this output terminal is also connected to the drain of NMOS transistor NM129. The source of NM129 is grounded, and its gate is connected to the control signal r_h. The inverter is enabled by the gate signal r_h of PM19, and the source of PM19 is connected to the power supply vphreg.PMOS transistor PM21, resistor R13, and NM130 are used to generate the bias current ibias. The source of PM21 is connected to the power supply vphreg, the gate is connected to the control signal pwron_hn, and the drain is connected to the first terminal of resistor R13. The second terminal of resistor R13 is connected to the drain of NMOS transistor NM130. The gate and drain of NM130 are connected, and also connected to the gates of NMOS transistors NM121 and NM125. The sources of NMOS transistors NM130, NM121, and NM125 are all grounded.

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