A low static power control circuit integrating a power stage and dynamic clock logic

Abstract

The application discloses a low static power consumption control circuit integrating a power stage and a dynamic clock logic, and solves the problems of high power consumption and lack of impedance matching of a dynamic clock architecture in the prior art. The application introduces a dynamic hysteresis gate control mechanism based on an input voltage state, significantly reduces the static power consumption of a controller, retains only a slow clock with extremely low frequency in an always-on state, and activates only a high-energy fast clock when the input voltage rises to an upper threshold voltage, thereby avoiding invalid flipping of the clock and the comparator, reducing the average static current of the MPPT controller to the level of nanoamperes, and significantly improving the end-to-end energy conversion efficiency under a weak heat source. The application builds a hysteresis voltage window, controls a dynamic clock, combines a four-switch Buck-Boost topology structure and zero-crossing detection, realizes nanoamperes-level static power consumption, and adaptively matches the input impedance without complex operation, thereby efficiently completing the maximum power point tracking of micro thermoelectric energy collection.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a low static power consumption control circuit that integrates power stage and dynamic clock logic. Background Technology

[0002] To reduce the quiescent power consumption of converters, existing research has proposed a dynamic clock timing control technique. This technique utilizes two independent clock signals: a lower-frequency "slow clock" to set the minimum duty cycle and detect the output voltage, and a higher-frequency "fast clock" to control the on-time of the power transistors. This architecture replaces the traditional high-gain error amplifier and continuous-time comparator with digital pulse control, thus significantly reducing quiescent current. Those skilled in the art have proposed a dual-mode buck converter combining dynamic clock and PWM (Pulse-width modulation), achieving nanoampere-level quiescent power consumption. Furthermore, they have proposed an adaptive dynamic clock technique, which adaptively adjusts the slow clock frequency and fast clock duty cycle to solve the problems of large ripple and slow transient response under heavy loads in traditional dynamic clocks, achieving efficient conversion over a wide load range. However, existing dynamic clock or adaptive dynamic clock control techniques are mainly designed for regulated output, and their control loop aims to maintain output voltage stability. Moreover, stabilizing the output voltage solely through dynamic clock cannot guarantee that the TEG (Thermo Electric Generator) operates at its maximum power point. Traditional dynamic clock architectures lack an input impedance adjustment mechanism, which makes impedance matching impossible in thermoelectric energy harvesting, resulting in low energy utilization.

[0003] Meanwhile, to address the energy extraction problem of TEG (Thermoelectric Generator), existing energy harvesting interface circuits widely employ MPPT (Maximum Power Point Tracking) technology. Common methods include perturbation observation and open-circuit voltage fractional method. For example, those skilled in the art have designed a reconfigurable DC-DC converter for TEG, employing a two-dimensional adaptive cooperative MPPT circuit to achieve input impedance matching by adjusting the conduction time and switching frequency. Traditional MPPT implementations typically rely on power-intensive analog comparators, complex digital computing units, or high-frequency sampling circuits to detect input voltage and current. However, this has limitations; traditional MPPT control circuits often consume microwatts (μW) or even higher power. For weak thermoelectric energy, the controller's own power consumption is too high, severely limiting the system's cold-start capability and resulting in low energy harvesting efficiency. Furthermore, existing MPPT technologies are usually based on PWM or PFM modulation, making direct integration into ultra-low-power dynamic clock architectures difficult. How to maintain the nanoampere-level quiescent current advantage of dynamic clocks while introducing the input impedance adjustment function required for MPPT remains a challenge that current technologies have not fully resolved.

[0004] Therefore, traditional maximum power point tracking (MPPT) techniques typically require high-frequency ADC sampling or continuously operating analog comparators to calculate power in real time. Their static power consumption is usually on the order of microwatts, severely wasting the meager energy generated by micro-thermoelectric generators (TEGs). Existing dynamic clocking or adaptive dynamic clocking techniques are primarily designed for output load voltage regulation and lack awareness of input source characteristics. When directly connected to a high-resistance TEG, the TEG's output voltage is easily pulled down to a region far from the maximum power point due to input impedance mismatch, resulting in most of the heat energy not being extracted. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a low static power control circuit integrating a power stage and dynamic clock logic. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a low static power control circuit integrating a power stage and dynamic clock logic, comprising: Input voltage monitoring circuit, dynamic clock signal generator, logic control unit, power stage circuit and zero-crossing detection circuit; The input voltage monitoring circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator; monitor the state of the input voltage of the thermoelectric generator within the dynamic hysteresis voltage window in real time, and output an enable control signal. The dynamic clock signal generator includes a slow clock generation circuit and a fast clock generation circuit. The slow clock generation circuit is normally open and is used to output a base clock to maintain the basic timing of the clock control circuit. Under the control of the enable control signal, the fast clock generation circuit is activated and generates a high-frequency pulse when the input voltage is higher than the upper threshold voltage of the dynamic hysteresis voltage window, and remains in the off state when the input voltage is lower than the lower threshold voltage of the dynamic hysteresis voltage window. The logic control unit is used to receive the base clock, high-frequency pulse, upper threshold voltage and lower threshold voltage of the dynamic hysteresis voltage window, and generate drive control signals. The power stage circuit is used to charge and discharge its own inductance during the activation of the fast clock generation circuit under the control of the drive control signal, and clamp the input voltage within the dynamic hysteresis voltage window by adjusting the input impedance to achieve maximum power point tracking. The zero-crossing detection circuit is used to monitor the inductor current during the inductor discharge phase and output a flip signal when the inductor current crosses zero. The logic control unit is also used to output a cutoff control signal when a flip signal is received, so as to control the power stage circuit to terminate the discharge of its own inductor.

[0006] In one embodiment of the present invention, a dynamic hysteresis voltage window is constructed based on the open-circuit voltage of a thermoelectric generator, including: The open-circuit voltage Voc of the thermoelectric generator is sampled and held, the center voltage of the maximum power point is set to Voc / 2, and the hysteresis voltage Vhys is preset. Voc / 2+Vhys is defined as the upper threshold voltage of the dynamic hysteresis voltage window, and Voc / 2-Vhys is defined as the lower threshold voltage of the dynamic hysteresis voltage window.

[0007] In one embodiment of the present invention, the slow clock generation circuit adopts a three-stage handshake structure relaxation oscillator, which consists of three identical delay units connected end to end to form a closed loop. Each delay unit follows a three-state handshake protocol of reset, timing and completion to eliminate short-circuit current. The first delay unit, stage1, includes: PMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M5, NMOS transistor M6, PMOS transistor M7, NMOS transistor M8 and capacitor Ca1; The source of the PMOS transistor M1 is connected to the power supply voltage, the gate is connected to the Vo2 signal output by the second delay unit stage2, and the drain is connected to the drain of NMOS transistor M2, the first terminal of capacitor Ca1, the drain of NMOS transistor M3 and the drain of PMOS transistor M5 respectively, and outputs the Va1 signal to the third delay unit stage3. The source of the NMOS transistor M2 outputs an Iosc signal, and its gate is connected to the Va2 signal output by the second delay unit stage2. The source of the NMOS transistor M3 is grounded, and its gate is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M6, the gate of the PMOS transistor M7, and the gate of the NMOS transistor M8, and outputs the Vb1 signal to the third delay unit stage3. The source of the PMOS transistor M5 is connected to the power supply voltage; The source of the NMOS transistor M6 is grounded, and its gate is connected to the Vb2 signal output by the second delay unit stage2. The source of the PMOS transistor M7 is connected to the power supply voltage, and its drain is connected to the drain of the NMOS transistor M8, outputting the Vo1 signal to the third delay unit stage3. The source of the NMOS transistor M8 is grounded; The second terminal of capacitor Ca1 is grounded.

[0008] In one embodiment of the present invention, the fast clock generation circuit includes: An inverter ring consisting of several inverters connected end to end, a bias circuit, a buffer stage, and an output module; The output of the bias circuit is connected to the inverter ring to provide a bias voltage to the inverter ring. The output of the inverter ring is connected to the buffer stage and is used to output an oscillation signal; The buffer stage is used to shape and amplify the oscillating signal to generate a square wave signal; The input terminal of the output module is connected to an enable control signal, and the output terminal is connected to the output terminal of the buffer stage, serving as the output terminal of the fast clock generation circuit. When the enable control signal is low, the output terminal of the fast clock generation circuit is pulled to ground potential; when the enable control signal is high, a square wave signal is output.

[0009] In one embodiment of the present invention, the input voltage monitoring circuit includes: Sample and hold circuit and multiplexed dynamic hysteresis comparator; The sample-and-hold circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator, and send the upper threshold voltage and lower threshold voltage of the dynamic hysteresis voltage window to the logic control unit and the multiplexed dynamic hysteresis comparator. The multiplexed dynamic hysteresis comparator is used to compare the input voltage of the thermoelectric generator. When the input voltage is higher than the upper threshold voltage, it outputs a high-level enable control signal, and when the input voltage is lower than the lower threshold voltage, it outputs a low-level enable control signal.

[0010] In one embodiment of the present invention, the dynamic hysteresis comparator is reused, including: First strong arm latch A, second strong arm latch B, and RS flip-flop composed of NOR gates; The enable signal of the first strong arm latch A is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the input voltage, and the negative input terminal is connected to the upper threshold voltage. The enable signal of the second strong arm latch B is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the lower threshold voltage, and the negative input terminal is connected to the input voltage. The R terminal of the RS flip-flop is connected to the output terminal of the second strong arm latch B, and the S terminal is connected to the output terminal of the first strong arm latch A. The output terminal serves as the output terminal of the multiplexed dynamic hysteresis comparator.

[0011] In one embodiment of the present invention, the zero-crossing detection circuit includes: Two voltage-to-current converters, two integrating capacitors, and one ZCD comparator; The first voltage-to-current converter converts the input voltage into a first charging current to charge the first integrating capacitor; The second voltage-to-current converter converts the output voltage of the power stage circuit into a second charging current to charge the second integrating capacitor; The ZCD comparator is used to compare the voltages on the two integrating capacitors. Utilizing the inductor volt-second balance principle, it outputs a flip signal when the voltages on the two integrating capacitors are equal, triggering the logic control unit to output a cutoff control signal.

[0012] In one embodiment of the present invention, the zero-crossing detection circuit adopts an intermittent working mode, which is in an enabled working state when the power stage circuit discharges its own inductor, and remains in a turned-off state when the inductor is charging.

[0013] In one embodiment of the present invention, the power stage circuit adopts a Buck-Boost topology with a single inductor and four switches: input-side switch NM00, input-side switch NM01, inductor L, output-side switch NM02, output-side switch PM01, and output resistor R. out and output capacitor C out ; The source of the input-side switch NM00 is connected to the drain of the input-side switch NM01 and the first end of the inductor L, respectively. The gate is connected to the drive control signal GateH, and the drain is connected to the input voltage as the input of the power stage circuit. The source of the input-side switching transistor NM01 is grounded, and the gate is connected to the drive control signal GateA. The second end of the inductor L is connected to the drain of the output-side switching transistor NM02 and the source of the output-side switching transistor PM01. The source of the output-side switching transistor NM02 is grounded, and the gate is connected to the drive control signal GateB. The gate of the output-side switching transistor PM01 is connected to the drive control signal GateLo, and the drain is connected to the output resistor R. out First terminal, output capacitor C out The first end is connected; The output resistance R out The second terminal is grounded; The output capacitor C out The second end is grounded.

[0014] In one embodiment of the present invention, the control logic of the logic control unit includes: When the high-frequency pulse is high, a corresponding drive control signal is generated to control the input-side switch NM00 and the output-side switch NM02 to turn on, while turning off the other switches, so that the thermoelectric generator charges the inductor L, resulting in a drop in the input voltage. When the high-frequency pulse is low, a corresponding drive control signal is generated to control the input-side switch NM01 and the output-side switch PM01 to turn on, while turning off the other switches, causing the inductor L to discharge to the output terminal, resulting in an increase in the input capacitance; through the continuous flipping of the high-frequency pulse, the input voltage fluctuates in a sawtooth pattern within the dynamic hysteresis voltage window. When the flip signal is high, a corresponding drive control signal is generated to turn on the input-side switch NM01 and the output-side switch NM02, while the other switches are turned off, so that the power stage circuit enters freewheeling mode.

[0015] The beneficial effects of this invention are: The solution provided in this invention significantly reduces the static power consumption of the controller by introducing a dynamic hysteresis gating mechanism based on the input voltage state, achieving cold start capability under low power conditions. The control circuit retains only the extremely low-frequency slow clock in a normally-on state to maintain the basic sample-and-hold circuit; while the high-power fast clock is only activated when the input voltage rises to the upper threshold voltage. This "on-demand" mechanism avoids ineffective clock and comparator switching, reducing the average static current of the MPPT controller to the nanoamp level. It supports TEG cold start under lower temperature differences, significantly improving end-to-end energy conversion efficiency under weak heat sources. Furthermore, compared to traditional dynamic clock control, this invention constructs a dynamic hysteresis voltage window, stabilizing the input voltage within the window through the coordinated operation of the fast and slow clocks. This control method eliminates the need for complex impedance calculations, dynamically clamping the input voltage near the maximum power point. Compared to traditional dynamic clocks, this invention can adaptively match the internal resistance changes of the TEG, ensuring that the TEG always outputs maximum power under different temperature environments. It significantly solves the problem of the trade-off between low power consumption control and high-efficiency energy extraction, achieves adaptive matching of input impedance, and greatly improves the energy extraction rate. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a low static power control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention. Figure 2 A flowchart of the MPPT (Maximum Power Point Tracking) of a low static power control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention. Figure 3 A timing logic waveform diagram of a low static power consumption control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention; Figure 4 The circuit structure diagram of a dynamic hysteresis comparator in a low static power control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention; Figure 5 The circuit structure diagram of the fast clock generation circuit in a low static power control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention; Figure 6 The circuit structure diagram of the slow clock generation circuit in a low static power control circuit integrating power stage and dynamic clock logic provided in an embodiment of the present invention; Figure 7 The diagram shows the circuit structure of a zero-crossing detection circuit in a low static power control circuit that integrates power stage and dynamic clock logic, as provided in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] This invention provides a low static power control circuit that integrates a power stage and dynamic clock logic, such as... Figure 1 As shown, it may include: Input voltage monitoring circuit, dynamic clock signal generator, logic control unit, power stage circuit and zero-crossing detection circuit; The input voltage monitoring circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator; it monitors the state of the input voltage of the thermoelectric generator within the dynamic hysteresis voltage window in real time and outputs an enable control signal. The dynamic clock signal generator includes a slow clock generation circuit and a fast clock generation circuit. The slow clock generation circuit is normally open and is used to output a base clock to maintain the basic timing of the clock control circuit. Under the control of the enable control signal, the fast clock generation circuit is activated and generates a high-frequency pulse when the input voltage is higher than the upper threshold voltage of the dynamic hysteresis voltage window, and remains in the off state when the input voltage is lower than the lower threshold voltage of the dynamic hysteresis voltage window. The logic control unit is used to receive the base clock, high-frequency pulses, and the upper and lower threshold voltages of the dynamic hysteresis voltage window, and generate drive control signals. The power stage circuit is used to charge and discharge its own inductor during the activation of the fast clock generation circuit under the control of the drive control signal. By adjusting the input impedance, the input voltage is clamped within the dynamic hysteresis voltage window to achieve maximum power point tracking. The zero-crossing detection circuit is used to monitor the inductor current during the inductor discharge phase and outputs a flip signal when the inductor current crosses zero. The logic control unit is also used to output a cutoff control signal when a flip signal is received, so as to control the power stage circuit to terminate the discharge of its own inductor.

[0019] For ease of understanding, Figure 1 The blue section represents the charging circuit, the red section represents the discharging circuit, and the green section represents the freewheeling circuit.

[0020] The MPPT (Maximum Power Point Tracking) flowchart of the low static power control circuit provided in this embodiment of the invention is as follows: Figure 2 As shown, the control circuit first samples and holds the open-circuit voltage Voc of the thermoelectric generator (TEG), and sets the center voltage of maximum power point tracking to 0. The open-circuit voltage Voc is the same as the voltage source in the signal source module. Based on this, two voltage thresholds are preset through a sample-and-hold circuit: an upper threshold voltage Voc / 2 + Vhys; and a lower threshold voltage Voc / 2 - Vhys. Vhys is the preset hysteresis voltage. These two thresholds constitute the allowable fluctuation range of the input voltage VIN. The output of the multiplexed dynamic hysteresis comparator is directly connected to the power supply or enable input pin of the fast clock generation circuit, forming a hardware gating path. The multiplexed dynamic hysteresis comparator monitors the input voltage of the thermoelectric generator in real time within the dynamic hysteresis voltage window, outputs an enable control signal, and clamps the input voltage within the dynamic hysteresis voltage window by adjusting the input impedance to achieve maximum power point tracking.

[0021] The timing logic waveform diagram of the low static power control circuit provided in this embodiment of the invention is as follows: Figure 3 As shown, when the input voltage Vin does not reach the upper threshold of the voltage window, the fast clock generation circuit does not work, outputs a low level, and the inductor of the power stage circuit discharges, causing Vin to rise. When the input Vin is higher than the upper threshold of the voltage window, the multiplexed dynamic hysteresis comparator triggers the fast clock generation circuit to start working, outputting a high-frequency pulse. When the high-frequency pulse is high, the inductor of the power stage circuit charges, as shown... Figure 3 The example shows that Ton_en is 1, causing Vin to decrease. Conversely, when the high-frequency pulse is low, the inductance of the power stage circuit itself discharges, such as... Figure 3 As shown, Toff_en is 1, causing Vin to rise. Due to differences in driving capability, the degree of Vin's decrease is greater than the degree of Vin's increase, thus resulting in an overall decreasing trend of Vin during the high-frequency pulse triggering period; when the inductor discharges to 0 current, as... Figure 3 As shown, FW_EN is 1, the power stage circuit enters freewheeling mode, maintaining the current at 0 until the next charging stage arrives.

[0022] The input voltage monitoring circuit may include: Sample and hold circuit and multiplexed dynamic hysteresis comparator; The sample-and-hold circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator, and send the upper threshold voltage and lower threshold voltage of the dynamic hysteresis voltage window to the logic control unit and the multiplexed dynamic hysteresis comparator. A dynamic hysteresis comparator is reused to compare the input voltage of the thermoelectric generator. When the input voltage is higher than the upper threshold voltage, a high-level enable control signal is output, and when the input voltage is lower than the lower threshold voltage, a low-level enable control signal is output.

[0023] Constructing a dynamic hysteresis voltage window based on the open-circuit voltage of a thermoelectric generator can include: The open-circuit voltage Voc of the thermoelectric generator is sampled and held, the center voltage of the maximum power point is set to Voc / 2, and the hysteresis voltage Vhys is preset. Voc / 2+Vhys is defined as the upper threshold voltage of the dynamic hysteresis voltage window, and Voc / 2-Vhys is defined as the lower threshold voltage of the dynamic hysteresis voltage window.

[0024] Understandably, when the input voltage exceeds the upper threshold voltage, a valid enable control signal is output to start the fast clock; when the input voltage drops below the lower threshold voltage, an invalid enable control signal is output to disable the fast clock.

[0025] Reuse dynamic hysteresis comparators, such as Figure 4 As shown, it may include: First strong arm latch A, second strong arm latch B, and RS flip-flop composed of NOR gates; The enable signal of the first strong arm latch A is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the input voltage, and the negative input terminal is connected to the upper threshold voltage. The enable signal of the second strong arm latch B is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the lower threshold voltage, and the negative input terminal is connected to the input voltage. The R terminal of the RS flip-flop is connected to the output of the second strong arm latch B, and the S terminal is connected to the output of the first strong arm latch A. The output terminal serves as the output of the multiplexed dynamic hysteresis comparator.

[0026] First strong arm latch A, such as Figure 4 As shown, it may include: The first MOSFET M11, the second MOSFET M12, the third MOSFET M13, the fourth MOSFET M14, the fifth MOSFET M15, the sixth MOSFET M16, the seventh MOSFET M17, the eighth MOSFET M18, the ninth MOSFET M19, the tenth MOSFET M20, and the eleventh MOSFET M21; The source of the first MOSFET is connected to the power supply voltage, the gate is connected to the gate of the second MOSFET and connected to the enable signal CMP_EN, and the drain is connected to the source of the seventh MOSFET and the drain of the ninth MOSFET respectively. The source of the second MOSFET is connected to the power supply voltage, and its drain is connected to the drain of the third MOSFET, the gate of the fourth MOSFET, and the MOSFET's gate protection, respectively. The source of the third MOSFET is connected to the power supply voltage, and its gate is connected to the drain of the fourth MOSFET, the drain of the fifth MOSFET, the gate of the seventh MOSFET, and the drain of the eighth MOSFET, respectively. The source of the fourth MOSFET is connected to the power supply voltage; The source of the fifth MOSFET is connected to the power supply voltage, and its gate is connected to the gate of the sixth MOSFET and connected to the enable signal CMP_EN. The source of the sixth MOSFET is connected to the power supply voltage, and its drain is connected to the source of the eighth MOSFET and the drain of the tenth MOSFET, respectively. The source of the ninth MOSFET is connected to the source of the tenth MOSFET and the drain of the eleventh MOSFET, respectively. The source of the eleventh MOSFET is grounded, and the gate is connected to the enable signal CMP_EN. The drains of the second MOSFET and the fifth MOSFET serve as the differential output terminals of the first strong arm latch A. The gates of the ninth and tenth MOSFETs serve as the differential input terminals of the first strong arm latch A.

[0027] Fast clock generation circuit, such as Figure 5 As shown, it may include: An inverter ring consisting of several inverters connected end to end, a bias circuit, a buffer stage, and an output module; The output of the bias circuit is connected to the inverter ring to provide a bias voltage for the inverter ring; The output of the inverter ring is connected to the buffer stage to output the oscillation signal; The buffer stage is used to shape and amplify the oscillating signal to generate a square wave signal; The input terminal of the output module is connected to the enable control signal, and the output terminal is connected to the output terminal of the buffer stage, serving as the output terminal of the fast clock generation circuit. When the enable control signal is low, the output terminal of the fast clock generation circuit is pulled to ground potential, and when the enable control signal is high, a square wave signal is output.

[0028] Bias circuit, such as Figure 5 As shown, it may include: Current source i0, NMOS transistor NM0, NMOS transistor NM1, NMOS transistor NM2, PMOS transistor PM1 and PMOS transistor PM2; One end of the current source i0 is connected to the power supply voltage, and the other end is connected to the drain of the NMOS transistor NM0. The gate of NMOS transistor NM0 is connected to its own drain, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2, respectively, and the source is grounded. The source of NMOS transistor NM1 is grounded, and its drain is connected to the drain of PMOS transistor PM1, the gate of PMOS transistor PM1, and the gate of PMOS transistor PM2, respectively. The source of NMOS transistor NM2 is grounded, and its drain is connected to the inverter ring accordingly. The source of PMOS transistor PM1 is connected to the power supply voltage; The source of PMOS transistor PM2 is connected to the power supply voltage, and the drain is connected to the inverter ring.

[0029] The enable control signal Fast_en serves as the input signal for the output module. The drain of the NMOS transistor NM4 in the output module, i.e., the output terminal of the output module, is connected to the output terminal of the buffer stage, acting as the output terminal of the fast clock generation circuit. When the enable control signal Fast_en is low, the output terminal of the fast clock generation circuit is pulled to ground potential VSSA, and the fast clock is not triggered. Conversely, the fast clock is triggered.

[0030] Slow clock generation circuit, such as Figure 6 As shown, the slow clock generation circuit adopts a three-stage handshake structure relaxation oscillator, which consists of three identical delay units connected end to end to form a closed loop. Each delay unit follows a three-state handshake protocol of reset, timing and completion to eliminate short-circuit current. The first delay unit, stage1, is as follows: Figure 6 As shown, it may include: PMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M5, NMOS transistor M6, PMOS transistor M7, NMOS transistor M8 and capacitor Ca1; The source of PMOS transistor M1 is connected to the power supply voltage, the gate is connected to the Vo2 signal output from the second delay unit stage2, and the drain is connected to the drain of NMOS transistor M2, the first terminal of capacitor Ca1, the drain of NMOS transistor M3 and the drain of PMOS transistor M5 respectively, and outputs the Va1 signal to the third delay unit stage3. The source of NMOS transistor M2 outputs the Iosc signal, and the gate is connected to the Va2 signal output by the second delay unit stage2. The source of NMOS transistor M3 is grounded, and its gate is connected to the drain of PMOS transistor M5, the drain of NMOS transistor M6, the gate of PMOS transistor M7, and the gate of NMOS transistor M8. The Vb1 signal is output to the third delay unit stage3. The source of PMOS transistor M5 is connected to the power supply voltage; The source of NMOS transistor M6 is grounded, and its gate is connected to the Vb2 signal output from the second delay unit stage2. The source of PMOS transistor M7 is connected to the power supply voltage, and its drain is connected to the drain of NMOS transistor M8, outputting the Vo1 signal to the third delay unit stage3. The source of NMOS transistor M8 is grounded; The second terminal of capacitor Ca1 is grounded.

[0031] The bias current of the three delay units is obtained by mirroring the reference current provided by the bandgap reference circuit through a current mirror.

[0032] This invention retains the slow and fast clocks in the dynamic clock architecture, but refactors their triggering mechanisms to meet MPPT requirements: the slow clock remains always on to maintain the circuit's basic static power consumption and periodic open-circuit voltage sampling updates. The fast clock uses an input voltage-triggered gating mechanism: only when the input voltage VIN is detected to rise and exceed the upper threshold voltage Voc_H, the dynamic hysteresis comparator outputs a valid signal, activating the fast clock generator; when VIN falls back below the lower threshold voltage Voc_L, the fast clock is disabled.

[0033] During the period when the fast clock is active, the system uses the high-frequency pulses of the fast clock to control the power switch: When the fast clock is high: the inductor charges. At this time, the input TEG stores energy in the inductor, causing the input current to increase and the input voltage VIN to drop rapidly. When the fast clock is low: the inductor discharges, transferring energy to the output. At this time, the TEG charges the input capacitor, causing the input voltage VIN to rise again.

[0034] Through the operation of the fast clock generation circuit described above, the continuous flipping of the fast clock forces the input voltage VIN to fluctuate in a sawtooth pattern between Voc_L and Voc_H. This mechanism dynamically clamps VIN near Voc / 2, thereby ensuring that the TEG always operates in the maximum power point region, achieving low power consumption and adaptive impedance matching.

[0035] Zero-crossing detection circuit, such as Figure 7 As shown, it may include: Two voltage-to-current converters, two integrating capacitors, and one ZCD comparator; The first voltage-to-current converter converts the input voltage into a first charging current IA to charge the first integrating capacitor; The second voltage-to-current converter converts the output voltage of the power stage circuit into a second charging current IB to charge the second integrating capacitor. The ZCD comparator is used to compare the voltages on two integrating capacitors. Utilizing the inductor volt-second balance principle, it outputs a flip signal when the voltages on the two integrating capacitors are equal, triggering the logic control unit to output a cutoff control signal.

[0036] The zero-crossing detection circuit can operate in an intermittent mode, being enabled during the discharge phase of the power stage circuit and turned off during the charging phase of the inductor.

[0037] To address the problem of traditional analog comparators shutting off too early or too late (generating reverse current) due to offset voltage, this invention abandons the traditional approach and employs a zero-crossing detection circuit based on the volt-second balance principle that is insensitive to offset. Design principle: This zero-crossing detection circuit utilizes the inductor's volt-second balance characteristic VIN×TON = VOUT×TOFF, converting it into an integral charge / voltage balance relationship. By comparing the accumulated voltage across the two capacitors, the zero-crossing point is accurately located, thereby avoiding the influence of the comparator input offset voltage.

[0038] The timing and logic of the zero-crossing detection circuit are as follows: During the inductor charging phase (TON), the switches controlled by signals Ton_en and Ton_en' are closed. Current IA charges the first integrating capacitor CA, while the second integrating capacitor CB remains reset (0V). At this time, VA rises linearly, simulating the accumulation process of the inductor current. During the inductor discharging phase (TOFF), the switches controlled by signals Toff_en and Toff_en' close the instant the inductor begins discharging. Current IB begins to rapidly charge the second integrating capacitor CB. The comparator begins monitoring at this time. When VB rises and catches up with VA (i.e., VB = VA), the comparator flips its output toggle signal. Turn-off action: The toggle signal triggers the logic circuit, ending the discharge cycle.

[0039] To address the large range of open-circuit voltage variation in the TEG (which may be higher or lower than the output voltage), the power stage circuit employs a single-inductor, four-switch Buck-Boost topology: input-side switch NM00, input-side switch NM01, inductor L, output-side switch NM02, output-side switch PM01, and output resistor R. out and output capacitor C out ; The source of the input-side switch NM00 is connected to the drain of the input-side switch NM01 and the first terminal of the inductor L, respectively. The gate is connected to the drive control signal GateH, and the drain is connected to the input voltage as the input of the power stage circuit. The source of the input-side switching transistor NM01 is grounded, and the gate is connected to the drive control signal GateA; The second terminal of inductor L is connected to the drain of output-side switching transistor NM02 and the source of output-side switching transistor PM01; The source of the output-side switching transistor NM02 is grounded, and the gate is connected to the drive control signal GateB; The gate of the output-side switching transistor PM01 is connected to the drive control signal GateLo, and the drain is connected to the output resistor R. out First terminal, output capacitor C out The first end is connected; Output resistance R out The second terminal is grounded; Output capacitor C out The second end is grounded.

[0040] The control logic of the logic control unit may include: When the high-frequency pulse is high, a corresponding drive control signal is generated to control the input-side switch NM00 and the output-side switch NM02 to turn on, while turning off the other switches, so that the thermoelectric generator charges the inductor L, resulting in a drop in the input voltage. When the high-frequency pulse is low, a corresponding drive control signal is generated to control the input-side switch NM01 and the output-side switch PM01 to turn on, while turning off the other switches, causing the inductor L to discharge to the output terminal, resulting in an increase in the input capacitance; through the continuous flipping of the high-frequency pulse, the input voltage fluctuates in a sawtooth pattern within the dynamic hysteresis voltage window. When the flip signal is high, a corresponding drive control signal is generated to turn on the input-side switch NM01 and the output-side switch NM02, while the other switches are turned off, so that the power stage circuit enters freewheeling mode.

[0041] The logic control unit can be implemented as follows: The output signal of the fast clock generation circuit is denoted as Ton_en, the output signal after passing through an inverter is denoted as Toff_en, and the output signal of the zero-crossing detection circuit is denoted as FW_EN. When Ton_en is 1 and Toff_en and FW_EN are 0, the input-side switch NM00 and the output-side switch NM02 are turned on, while the other switches are turned off, causing the thermoelectric generator to charge the inductor L, resulting in a drop in the input voltage. When Toff_en is 1 and Ton_en and FW_EN are 0, the input-side switch NM01 and the output-side switch PM01 are turned on, while the other switches are turned off, causing the inductor L to discharge to the output terminal and the input capacitor to charge, resulting in an increase in the input voltage. When FE_EN is 1 and Ton_en and Toff_en are 0, the input-side switch NM01 and the output-side switch NM02 are turned on, while the other switches are turned off, allowing the power stage circuit to enter freewheeling mode until the rising edge of the next fast clock arrives, at which point the power stage circuit is charged.

[0042] The control circuit provided in this embodiment of the invention significantly reduces the static power consumption of the controller by introducing a dynamic hysteresis gating mechanism based on the input voltage state, achieving cold start capability under low power conditions. The control circuit keeps only the extremely low-frequency slow clock in a normally-on state to maintain the basic sample-and-hold circuit; while the high-power fast clock is only activated when the input voltage rises to the upper threshold voltage. This "on-demand" mechanism avoids ineffective clock and comparator switching, reducing the average static current of the MPPT controller to the nanoamp level. It supports TEG cold start under lower temperature differences, significantly improving end-to-end energy conversion efficiency under weak heat sources. Furthermore, compared to traditional dynamic clock control, this control circuit constructs a dynamic hysteresis voltage window, stabilizing the input voltage within the window through the coordinated operation of the fast and slow clocks. This control method eliminates the need for complex impedance calculations, dynamically clamping the input voltage near the maximum power point. Compared to traditional dynamic clocks, this control circuit can adaptively match the internal resistance changes of the TEG, ensuring that the TEG always outputs maximum power under different temperature environments. This significantly solves the dilemma of the trade-off between low-power control and high-efficiency energy extraction, achieving adaptive matching of input impedance and greatly improving the energy extraction rate. Secondly, traditional MPPT often relies on digital signal processors or complex logic circuits to execute algorithms, resulting in large area, high cost, and limited tracking speed to environmental changes due to sampling rate and computation cycle. The control circuit provided in this embodiment of the invention uses a hysteresis comparator to directly control the enable terminal of the fast clock, eliminating the need for analog-to-digital converters and complex digital logic units, greatly saving chip area and cost. Simultaneously, due to the absence of complex algorithm delays, when sudden changes in external ambient temperature cause input voltage fluctuations, the circuit can respond instantaneously through the hysteresis window, quickly adjusting the inductor current to ensure the real-time performance and stability of MPPT tracking. Understandably, this invention achieves maximum power point tracking; in fact, the concept of this invention can also be used to implement voltage regulation technology.

[0043] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A low static power consumption control circuit integrating power stage and dynamic clock logic, characterized in that, include: Input voltage monitoring circuit, dynamic clock signal generator, logic control unit, power stage circuit and zero-crossing detection circuit; The input voltage monitoring circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator; The input voltage of the thermoelectric generator is monitored in real time within the dynamic hysteresis voltage window, and an enable control signal is output. The dynamic clock signal generator includes a slow clock generation circuit and a fast clock generation circuit; The slow clock generation circuit is normally open and is used to output a base clock to maintain the basic timing of the clock control circuit. Under the control of the enable control signal, the fast clock generation circuit is activated and generates a high-frequency pulse when the input voltage is higher than the upper threshold voltage of the dynamic hysteresis voltage window, and remains in the off state when the input voltage is lower than the lower threshold voltage of the dynamic hysteresis voltage window. The logic control unit is used to receive the base clock, high-frequency pulse, upper threshold voltage and lower threshold voltage of the dynamic hysteresis voltage window, and generate drive control signals. The power stage circuit is used to charge and discharge its own inductance during the activation of the fast clock generation circuit under the control of the drive control signal, and clamp the input voltage within the dynamic hysteresis voltage window by adjusting the input impedance to achieve maximum power point tracking. The zero-crossing detection circuit is used to monitor the inductor current during the inductor discharge phase and output a flip signal when the inductor current crosses zero. The logic control unit is also used to output a cutoff control signal when a flip signal is received, so as to control the power stage circuit to terminate the discharge of its own inductor.

2. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The construction of a dynamic hysteresis voltage window based on the open-circuit voltage of a thermoelectric generator includes: The open-circuit voltage Voc of the thermoelectric generator is sampled and held, the center voltage of the maximum power point is set to Voc / 2, and the hysteresis voltage Vhys is preset. Voc / 2+Vhys is defined as the upper threshold voltage of the dynamic hysteresis voltage window, and Voc / 2-Vhys is defined as the lower threshold voltage of the dynamic hysteresis voltage window.

3. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The slow clock generation circuit adopts a three-stage handshake structure relaxation oscillator, which consists of three identical delay units connected end to end to form a closed loop. Each delay unit follows a three-state handshake protocol of reset, timing and completion to eliminate short-circuit current. The first delay unit, stage1, includes: PMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M5, NMOS transistor M6, PMOS transistor M7, NMOS transistor M8 and capacitor Ca1; The source of the PMOS transistor M1 is connected to the power supply voltage, the gate is connected to the Vo2 signal output by the second delay unit stage2, and the drain is connected to the drain of NMOS transistor M2, the first terminal of capacitor Ca1, the drain of NMOS transistor M3 and the drain of PMOS transistor M5 respectively, and outputs the Va1 signal to the third delay unit stage3. The source of the NMOS transistor M2 outputs an Iosc signal, and its gate is connected to the Va2 signal output by the second delay unit stage2. The source of the NMOS transistor M3 is grounded, and its gate is connected to the drain of the PMOS transistor M5, the drain of the NMOS transistor M6, the gate of the PMOS transistor M7, and the gate of the NMOS transistor M8, and outputs the Vb1 signal to the third delay unit stage3. The source of the PMOS transistor M5 is connected to the power supply voltage; The source of the NMOS transistor M6 is grounded, and its gate is connected to the Vb2 signal output by the second delay unit stage2. The source of the PMOS transistor M7 is connected to the power supply voltage, and its drain is connected to the drain of the NMOS transistor M8, outputting the Vo1 signal to the third delay unit stage3. The source of the NMOS transistor M8 is grounded; The second terminal of capacitor Ca1 is grounded.

4. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The fast clock generation circuit includes: An inverter ring consisting of several inverters connected end to end, a bias circuit, a buffer stage, and an output module; The output of the bias circuit is connected to the inverter ring to provide a bias voltage to the inverter ring. The output of the inverter ring is connected to the buffer stage and is used to output an oscillation signal; The buffer stage is used to shape and amplify the oscillating signal to generate a square wave signal; The input terminal of the output module is connected to an enable control signal, and the output terminal is connected to the output terminal of the buffer stage, serving as the output terminal of the fast clock generation circuit. When the enable control signal is low, the output terminal of the fast clock generation circuit is pulled to ground potential; when the enable control signal is high, a square wave signal is output.

5. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The input voltage monitoring circuit includes: Sample and hold circuit and multiplexed dynamic hysteresis comparator; The sample-and-hold circuit is used to construct a dynamic hysteresis voltage window based on the open-circuit voltage of the thermoelectric generator, and send the upper threshold voltage and lower threshold voltage of the dynamic hysteresis voltage window to the logic control unit and the multiplexed dynamic hysteresis comparator. The multiplexed dynamic hysteresis comparator is used to compare the input voltage of the thermoelectric generator. When the input voltage is higher than the upper threshold voltage, it outputs a high-level enable control signal, and when the input voltage is lower than the lower threshold voltage, it outputs a low-level enable control signal.

6. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 5, characterized in that, The multiplexed dynamic hysteresis comparator includes: First strong arm latch A, second strong arm latch B, and RS flip-flop composed of NOR gates; The enable signal of the first strong arm latch A is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the input voltage, and the negative input terminal is connected to the upper threshold voltage. The enable signal of the second strong arm latch B is obtained by passing the outputs of the slow clock generation circuit and the fast clock generation circuit through an XOR gate. The positive input terminal is connected to the lower threshold voltage, and the negative input terminal is connected to the input voltage. The R terminal of the RS flip-flop is connected to the output terminal of the second strong arm latch B, and the S terminal is connected to the output terminal of the first strong arm latch A. The output terminal serves as the output terminal of the multiplexed dynamic hysteresis comparator.

7. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The zero-crossing detection circuit includes: Two voltage-to-current converters, two integrating capacitors, and one ZCD comparator; The first voltage-to-current converter converts the input voltage into a first charging current to charge the first integrating capacitor; The second voltage-to-current converter converts the output voltage of the power stage circuit into a second charging current to charge the second integrating capacitor; The ZCD comparator is used to compare the voltages on the two integrating capacitors. Utilizing the inductor volt-second balance principle, it outputs a flip signal when the voltages on the two integrating capacitors are equal, triggering the logic control unit to output a cutoff control signal.

8. The low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The zero-crossing detection circuit adopts an intermittent working mode, which is enabled when the power stage circuit discharges its own inductor and remains off when the inductor is charging.

9. A low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 1, characterized in that, The power stage circuit adopts a Buck-Boost topology with a single inductor and four switches: input-side switch NM00, input-side switch NM01, inductor L, output-side switch NM02, output-side switch PM01, and output resistor R. out and output capacitor C out ; The source of the input-side switch NM00 is connected to the drain of the input-side switch NM01 and the first end of the inductor L, respectively. The gate is connected to the drive control signal GateH, and the drain is connected to the input voltage as the input of the power stage circuit. The source of the input-side switching transistor NM01 is grounded, and the gate is connected to the drive control signal GateA. The second end of the inductor L is connected to the drain of the output-side switching transistor NM02 and the source of the output-side switching transistor PM01. The source of the output-side switching transistor NM02 is grounded, and the gate is connected to the drive control signal GateB. The gate of the output-side switching transistor PM01 is connected to the drive control signal GateLo, and the drain is connected to the output resistor R. out First terminal, output capacitor C out The first end is connected; The output resistance R out The second terminal is grounded; The output capacitor C out The second terminal is grounded.

10. A low static power consumption control circuit integrating power stage and dynamic clock logic according to claim 9, characterized in that, The control logic of the logic control unit includes: When the high-frequency pulse is high, a corresponding drive control signal is generated to control the input-side switch NM00 and the output-side switch NM02 to turn on, while turning off the other switches, so that the thermoelectric generator charges the inductor L, resulting in a drop in the input voltage. When the high-frequency pulse is low, a corresponding drive control signal is generated to control the input-side switch NM01 and the output-side switch PM01 to turn on, while turning off the other switches, causing the inductor L to discharge to the output terminal, resulting in an increase in the input capacitance; through the continuous flipping of the high-frequency pulse, the input voltage fluctuates in a sawtooth pattern within the dynamic hysteresis voltage window. When the flip signal is high, a corresponding drive control signal is generated to turn on the input-side switch NM01 and the output-side switch NM02, while the other switches are turned off, so that the power stage circuit enters freewheeling mode.

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