Oscillator

Abstract

To provide an oscillator that can maintain its oscillation frequency regardless of temperature. [Solution] Reference current sources 1 and 2 generate currents with opposite temperature characteristics and add them together to form a reference current I REF It outputs the following. Ring oscillator 3 outputs the reference current I REF It outputs an output signal OUT with an oscillation frequency corresponding to the specified value. The reference current source 1 has a diode D1, n-type transistors M1, M2 and M90 in cascaded configuration. The gate of n-type transistor M2 is at node N B The n-type transistor M1 is connected to the ground. The reference current source 2 has a cascaded n-type transistor M3 and diode D2, a cascaded n-type transistor M4, a p-type transistor M5 and resistor R1, and a p-type transistor M6 that forms a current mirror with the p-type transistor M5. The gates of the n-type transistors M3 and M4 are connected to the anode of diode D2. The n-type transistor M2 is connected to node N A It is connected to this.

Description

Technical Field

[0001] The present disclosure relates to an oscillator, for example, an oscillator used under conditions where the surrounding environment changes.

Background Art

[0002] Oscillators are widely used to supply an operating clock to a circuit. Such an oscillator is required to output a signal with a constant oscillation frequency without being affected by the use environment.

[0003] Patent Document 1 proposes an oscillator that can prevent a decrease in the oscillation frequency when the temperature rises. In the oscillator of Patent Document 1, when the power supply voltage is 1.8 V, the oscillation frequency is 2.8 MHz at -40°C and 3.6 MHz at 150°C. Also, in the oscillator of Patent Document 1, when the power supply voltage is 2.5 V, the oscillation frequency is 2.1 MHz at -40°C and 2.7 MHz at 150°C.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the oscillator according to Patent Document 1 is used to generate a clock supplied to a flip-flop constituting a digital circuit, there is a problem that the variation in the oscillation frequency is too large. In a flip-flop, it is required to suitably ensure the setup time and the hold time. The setup time is the minimum time for which the data input of the flip-flop should be stabilized before the rising edge of the clock. The hold time is the minimum time for which the data input of the flip-flop should be stabilized after the rising edge of the clock.

[0006] If the oscillation frequency of the oscillator that generates the clock fluctuates with temperature, the rising and falling edges of the clock will vary. This reduces the available setup and hold times, making it impossible to secure sufficient setup and hold times. Therefore, an oscillator that can suppress fluctuations in oscillation frequency more effectively with respect to temperature changes is required.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] According to one embodiment, the oscillator comprises a first current source that generates a first current having a positive temperature characteristic corresponding to the power supply voltage output from the power supply, a second current source that generates a second current having a negative temperature characteristic corresponding to the power supply voltage and outputs a reference current obtained by adding the first current and the second current, and a ring oscillator composed of a plurality of inverters in which a first conductivity type transistor and a second conductivity type transistor are complementaryly connected, which outputs an output signal of an oscillation frequency corresponding to the reference current, wherein the first current source comprises a first diode and a first transistor of the first conductivity type, which are sequentially cascaded between the power supply and ground, and a second transistor of the first conductivity type and a second resistor, which are sequentially cascaded between the second current source and ground, and the control terminal of the second transistor is connected to the first diode and The control terminal of the first transistor is connected to the ground, and the second current source comprises a third transistor of first conductivity type and a second diode, which are cascaded in order between the power supply and the ground, a fourth transistor of second conductivity type, a fifth transistor of second conductivity type and a first resistor, which are cascaded in order between the power supply and the ground, and a sixth transistor of second conductivity type, one end of which is connected between the power supply and the ring oscillator and which forms a current mirror with the fifth transistor, wherein the control terminals of the third and fourth transistors are connected to the anode of the second diode, and the second transistor is connected between the node between the fourth transistor and the fifth transistor and the second resistor. [Effects of the Invention]

[0009] According to one embodiment, an oscillator that can maintain its oscillation frequency regardless of temperature can be provided. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a graph showing the relationship between the drain-source current and the gate-source voltage of a MOS transistor. [Figure 2] Figure 2 is a circuit diagram showing a typical ring oscillator configuration. [Figure 3] Figure 3 is a schematic graph showing the relationship between the temperature characteristics of a MOS transistor and the temperature characteristics of the oscillation frequency of a ring oscillator. [Figure 4] Figure 4 is a circuit diagram showing the configuration of the oscillator according to Embodiment 1. [Figure 5] Figure 5 shows the current flow in the oscillator according to Embodiment 1. [Figure 6] Figure 6 shows the simulation results of the current in the oscillator according to Embodiment 1. [Figure 7] Figure 7 shows the simulation results of the oscillation frequency in the oscillator according to Embodiment 1. [Figure 8] Figure 8 is a circuit diagram showing the configuration of the oscillator according to Embodiment 2. [Figure 9] Figure 9 is a table showing the relationship between the on / off state of the switch and the value of the reference current. [Figure 10] Figure 10 is a circuit diagram showing the configuration of the oscillator according to Embodiment 3. [Figure 11] Figure 11 shows the eye pattern of the oscillator output signal when noise is superimposed on the power supply voltage. [Figure 12] Figure 12 is a circuit diagram showing the configuration of the oscillator according to Embodiment 4. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings. In each drawing, the same elements are denoted by the same reference numerals, and redundant explanations are omitted where necessary.

[0012] As a prerequisite for understanding the oscillator described in the following embodiment, the relationship between the MOS (Metal Oxide Semiconductor) transistors that constitute the oscillator and the oscillation frequency will be explained.

[0013] The drain-source current I of a MOS transistor ds and the gate-source voltage V gs The relationship between them is generally expressed by the following formula using the threshold voltage V t and the gain factor β of the MOS transistor.

Equation

Equation

[0014] Based on the above formula, the relationship between the drain-source current I ds and the gate-source voltage V gs will be explained. Figure 1 is a graph showing the relationship between the drain-source current I ds of a MOS transistor and the gate-source voltage V gs . Since both the gain factor β and the threshold voltage V t of the MOS transistor have negative temperature characteristics, the relationship between the drain-source current I ds and the gate-source voltage V gs changes with temperature. Specifically, as the temperature increases, β in Equation [1] decreases, so the rate of change of the drain-source current I ds becomes smaller. Therefore, in Figure 1, as the temperature increases, the slope of the curve showing the drain-source current I ds becomes smaller. Also, as the temperature increases, V t in Equation [1] becomes smaller, so the curve showing the drain-source current I ds shifts to the left. Therefore, as shown in Figure 1, the relationship between the drain-source current I ds and the gate-source voltage V gs can be divided into two regions. Region 1 is the case where the drain-source current I dsThis is the region where the drain-source current I increases when the temperature is lower than when the temperature is higher. ds This is the region where the value becomes larger.

[0015] Next, a general ring oscillator will be described. Figure 2 is a circuit diagram showing the configuration of a general ring oscillator 10. The ring oscillator 10 is constructed by connecting INVm from INV1, which consists of p-type transistors MP and n-type transistors MN in cascaded order, to the power supply VCC, in parallel between INVm and ground. Hereinafter, m is an integer of 2 or more. In the following, the p-type transistor MP will also be referred to as the 10th transistor, and the n-type transistor MN as the 11th transistor. Also, in the following, the power supply voltage output by the power supply VCC will be referred to as the power supply voltage VCC.

[0016] The input of CMOS inverter INV1 and the output of CMOS inverter INVm are connected to the output terminal OUT. The outputs of CMOS inverters INV1 through INVm-1 are connected to the inputs of CMOS inverters INV2 through INVm, respectively. In other words, if k is an integer between 1 and m-1, the output of CMOS inverter INVk is connected to the input of the adjacent CMOS inverter INVk+1.

[0017] Oscillation frequency f of ring oscillator 10 OSC This refers to the rise and fall time of the output voltage per inverter stage. d Therefore, it can be expressed by the following formula.

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[0018] Generally, the drain-source current I of a MOS transistor ds The larger the value, the greater the delay time t per inverter stage. d It is known that this becomes smaller. Therefore, the delay time t depends on the temperature characteristics of the MOS transistor.d The oscillation frequency f is determined by OSC Temperature characteristics also appear.

[0019] Figure 3 shows the temperature characteristics of the MOS transistor and the oscillation frequency f of the ring oscillator 10. OSC This graph schematically shows the relationship with temperature characteristics. When the transistors constituting the ring oscillator 10 are operated in region 1 of Figure 1, the drain-source current I increases as the ambient temperature rises. ds As it becomes larger, from equation [3], the oscillation frequency f OSC The frequency increases. In this case, the oscillation frequency f OSC This will result in a positive temperature characteristic.

[0020] On the other hand, when the transistors constituting the ring oscillator 10 are operated in region 2 of Figure 1, the drain-source current I increases as the ambient temperature rises. ds As it becomes smaller, from equation [3], the oscillation frequency f OSC The frequency becomes lower. In this case, the oscillation frequency f OSC This will result in a negative temperature characteristic.

[0021] In light of the recent demand for lower power consumption, the power consumption P of ring oscillators has also been reduced. OSC A reduction in the power supply voltage VCC supplied to the ring oscillator and the ring oscillator's current consumption I is required. OSC Reducing the power consumption P of the ring oscillator is considered effective. OSC The power consumption is expressed by the following formula:

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[0022] Based on the above, the power consumption P of the ring oscillator 10 is OSC To reduce this, lowering the power supply voltage VCC is effective.

[0023] In the following, when the term "transistor" is used, it refers to a MOS transistor. The term "transistor" will also be abbreviated as "Tr". In a MOS transistor, one of the source and drain terminals is referred to as the first end, the other as the second end, and the gate is also referred to as the control terminal.

[0024] The oscillator described in Patent Document 1 above prevents a decrease in oscillation frequency in situations where the oscillation frequency decreases with increasing temperature, as shown in region 2 in Figure 1. However, because the amount of fluctuation in oscillation frequency with increasing temperature is large, it is difficult to use it for clock generation in digital circuits, as described above.

[0025] Embodiment 1 The oscillator 100 is a circuit that oscillates by receiving a power supply voltage from a power supply voltage. Hereinafter, the power supply voltage output by power supply VCC will also be referred to as power supply voltage VCC. Figure 4 is a circuit diagram showing the configuration of the oscillator 100 according to Embodiment 1. The oscillator 100 according to Embodiment 1 has a reference current source 1, a reference current source 2, and a ring oscillator 3. Reference current sources 1 and 2 will also be referred to as the first and second current sources, respectively.

[0026] In the oscillator 100, the current I1 from the reference current source 1 having a positive temperature characteristic and the current I2 from the reference current source 2 having a negative temperature characteristic are added together to form the current I REF This is supplied to the ring oscillator 3. As a result, the oscillator 100 generates current due to temperature changes. REF By canceling out these fluctuations, the temperature fluctuations in the oscillation frequency of ring oscillator 3 are suppressed.

[0027] The reference current source 1 is configured as a current source having a positive temperature characteristic. The reference current source 1 includes a diode D1 and n-type transistors M1, M2, and M90. In Embodiment 1, the n-type transistors M1, M2, and M90 are depletion-type MOS transistors.

[0028] Diode D1 and n-type transistor M1 are cascaded between the power supply VCC and ground GND in this order. The anode of diode D1 is connected to the power supply VCC. The cathode of diode D1 is connected to the drain of n-type transistor M1. The source and gate of n-type transistor M1 are connected to ground GND.

[0029] n-type transistors M2 and M90 are cascaded in this order between the reference current source 2 and ground GND. The drain of n-type transistor M2 is connected to the node between the drain of p-type transistor M5 and the drain of n-type transistor M4 of the reference current source 2, as will be described later. The source of n-type transistor M2 is connected to the drain of n-type transistor M90. The gate of n-type transistor M2 is connected to node N between the cathode of diode D1 and the source of n-type transistor M1. B The source and gate of the n-type transistor M90 are connected to ground (GND).

[0030] The n-type transistor M90 is provided as a resistor in the reference current source 2 and may be replaced with a general-purpose resistor. Hereafter, the n-type transistor M90 will also be referred to as the second resistor.

[0031] As described above, since the reference current source 1 is constructed using a depletion-type MOS transistor, it functions as a normally-on type current source.

[0032] Hereinafter, n-type transistors M1 and M2 will also be referred to as the first and second transistors, respectively. N-type transistor M90 will also be referred to as the twelfth transistor. Diode D1 will also be referred to as the first diode.

[0033] The reference current source 2 is configured as a current source having a negative temperature characteristic. The reference current source 2 includes a diode D2, a resistor R1, n-type transistors M3 and M4, and p-type transistors M5 and M6. In Embodiment 1, the n-type transistor M3 is a depletion-type MOS transistor. The n-type transistor M4, and the p-type transistors M5 and M6 are enhancement-type MOS transistors.

[0034] The n-type transistor M3 and diode D2 are cascaded between the power supply VCC and ground GND in this order. The drain of n-type transistor M3 is connected to the power supply VCC. The source of n-type transistor M3 is connected to the gate of n-type transistor M3 and the anode of diode D2. The cathode of diode D2 is connected to ground GND.

[0035] The p-type transistor M5, the n-type transistor M4, and the resistor R1 are cascaded in this order between the power supply VCC and the ground GND. The source of the p-type transistor M5 is connected to the power supply VCC. The drain of the p-type transistor M5 is connected to the gate of the p-type transistor M5, the drain of the n-type transistor M4, and the drain of the n-type transistor M2. The resistor R1 is connected between the source of the n-type transistor M4 and the ground GND. The gate of the n-type transistor M4 is connected to node N between the source of the n-type transistor M3 and the anode of diode D2. A It connects to the network.

[0036] The p-type transistors M5 and M6 form a current mirror circuit. The source of p-type transistor M6 is connected to the power supply VCC. The drain of p-type transistor M6 is connected to ring oscillator 3. The gate of p-type transistor M6 is connected to the gate of p-type transistor M5.

[0037] As described above, since the reference current source 2 is constructed using a depletion-type MOS transistor, it functions as a normally-on type current source.

[0038] Hereafter, n-type transistors M3 and M4 will also be referred to as the third and fourth transistors, respectively. p-type transistors M5 and M6 will also be referred to as the fifth and sixth transistors, respectively. Diode D2 will also be referred to as the second diode. Resistor R1 will also be referred to as the first resistor.

[0039] Ring oscillator 3 has the same configuration as ring oscillator 10 in Figure 2. The current output from the drain of the p-type transistor M6 of the reference current source 2 is the reference current I of ring oscillator 3. REF It is supplied as such. The other configurations of ring oscillator 3 are the same as those of ring oscillator 10 in Figure 2, so redundant explanations are omitted.

[0040] Next, the operation of the oscillator 100 will be described. First, the temperature characteristics of the current flowing through the reference current source 2 will be examined. Figure 5 is a diagram showing the current flow in the oscillator 100 according to Embodiment 1. The forward voltage of diode D2 is V F Let [D2] be at temperature T. The forward voltage of diode D2 is V. F If the temperature characteristic of [D2] is negative, the following equation holds true.

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[0041] Therefore, node N between the source of n-type transistor M3 and the anode of diode D2 A Voltage V AThe temperature characteristic is negative, as shown by the following equation.

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[0042] Here, assuming that the temperature characteristic of resistor R1 is approximately 0, the temperature characteristic of the current I2 flowing through the n-type transistor M4 and resistor R1 will also be negative, as shown by the following equation. Note that a temperature characteristic of resistor R1 being approximately 0 means that the temperature characteristic of resistor R1 is 0 or a value that approximates 0. To give resistor R1 a temperature characteristic of 0 or a value that approximates 0, for example, resistor R1 may be constructed as a polysilicon resistor.

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[0043] Next, we will examine the temperature characteristics of the current flowing through the reference current source 1. The forward voltage of diode D1 is V F Let [D1] be the forward voltage of diode D1. F If the temperature characteristic of [D1] is negative, the following equation holds true.

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[0044] Therefore, node N between the cathode of diode D1 and the drain of n-type transistor M1 B Voltage V B The temperature characteristic is negative, as shown by the following equation.

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[0045] Drain-source voltage V of n-type transistor M90 DS If the temperature characteristic of [M90] is positive, the following equation holds true.

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[0046] In this case, the temperature characteristics of the current I1 flowing through n-type transistors M2 and M90 are also positive, as shown by the following equation.

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[0047] Therefore, the current flowing through the p-type transistor M5 of the reference current source 2 is the sum of current I1 and current I2. Thus, the reference current I flowing through the p-type transistor M5 and the p-type transistor M6 that constitutes the current mirror circuit is REF This is the sum of current I1 and current I2.

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[0048] As shown in equation

[15] , the reference current I REF The currents I1 and I2 contained in the oscillator have opposing temperature characteristics. Therefore, it can be seen that the temperature-dependent fluctuations of current I1 and current I2 cancel each other out. As a result, in oscillator 100, the reference current I REF Temperature fluctuations can be suppressed.

[0049] Figure 6 shows the simulation results of the current in the oscillator 100 according to Embodiment 1. As shown in Figure 6, currents I1 and I2 exhibit opposing temperature characteristics. On the other hand, the reference current I, which is the sum of currents I1 and I2, REF This shows that the temperature characteristics of current I1 and the temperature characteristics of current I2 cancel each other out, resulting in a mild positive temperature characteristic. Generally, when the power supply voltage VCC in which the transistor included in oscillator 100 operates in region 2 of Figure 1 is 1.9V or higher, the reference current I REF The fluctuations can be effectively suppressed.

[0050] Figure 7 shows the simulation results of the oscillation frequency in the oscillator 100 according to Embodiment 1. As shown in Figure 7, compared to the case where current I1 or I2 is supplied to the ring oscillator 3, current I REF It can be seen that supplying this reduces the fluctuation range of the oscillation frequency.

[0051] As described above, with this configuration, by summing the currents generated by two reference voltage sources having opposite temperature characteristics and supplying them to the ring oscillator, temperature fluctuations in the current supplied to the ring oscillator can be suppressed. As a result, temperature fluctuations in the oscillator's oscillation frequency can be suppressed.

[0052] Embodiment 2 In Embodiment 1, an oscillator capable of reducing temperature fluctuations in oscillation frequency was described. However, due to process variations and other factors, individual differences may occur in the oscillation frequency of the oscillator. Therefore, in this embodiment, the reference current I REFを This section describes an oscillator in which the oscillation frequency of ring oscillator 3 can be adjusted by trimming.

[0053] Figure 8 is a circuit diagram showing the configuration of the oscillator according to Embodiment 2. The oscillator 200 has a configuration in which the reference current source 2 of the oscillator 100 is replaced with a reference current source 4. The reference current source 4 has a configuration in which the p-type transistor M6 of the reference current source 2 is replaced with p-type transistors M61 to M64. In addition, the reference current source 4 has switches SW1 to SW4 added compared to the reference current source 2.

[0054] The sources of p-type transistors M61 to M64 are connected to the power supply VCC. Switches SW1 to SW4 are inserted between the drains of p-type transistors M61 to M64 and ring oscillator 3, respectively. The gates of p-type transistors M61 to M64 are connected to the gate of p-type transistor M5.

[0055] In this configuration, p-type transistors M61 and M64 are transistors of different sizes. For example, p-type transistor M61 is the same size as p-type transistor M5. p-type transistor M62 is twice the size of p-type transistor M5. p-type transistor M63 is four times the size of p-type transistor M5. p-type transistor M64 is eight times the size of p-type transistor M5.

[0056] Therefore, in oscillator 200, the reference current I is controlled by switching the on / off of switches SW1 to SW4. REF The value can be adjusted. Figure 9 shows the on / off state of switches SW1 to SW4 and the reference current I REF This is a table showing the relationship with the value of . Figure 9 shows an example where the sum of the currents I1 and I2 flowing through the p-type transistor M5 is 1 μA. As shown in Figure 9, by appropriately selecting the switch that turns ON from SW1 to SW4, the reference current I REF The value can be adjusted in 15 steps.

[0057] Switches SW1 to SW4 may be controlled by providing switch signals from a control unit (not shown) to turn them on or off.

[0058] As a result, the oscillator 200 receives a reference current I REF By trimming the signal, variations in the oscillation frequency of ring oscillator 3 caused by process variations can be suppressed.

[0059] Embodiment 3 In the oscillator according to the above embodiment, if noise is superimposed on the power supply voltage VCC, the noise propagates to the ring oscillator 3. As a result, there is a risk that jitter will be introduced into the output signal OUT, which is used as the clock signal.

[0060] For example, let's consider the case where the oscillator according to the above embodiment is mounted on an IC (Integrated Circuit) installed in an automobile. Regarding noise immunity for ICs used in automobiles, there is, for example, the IEC standard which is attracting attention in the automotive industry. In the IEC standard, IEC 62132-4 (DPI method: Direct Power Injection method) is standardized as an EMC (Electromagnetic Compatibility) (immunity) test. In the DPI method, noise of ±600mV (equivalent to 50Ω) is superimposed on the power supply terminal of a local pin (a pin that is not connected to anything outside the ECU (Electronic Control Unit) but is connected to components including other ICs within the ECU), usually in the range of 150KHz to 1GHz. It is required that the IC does not malfunction even under this noise superimposition.

[0061] When noise is superimposed on the power supply voltage, it can be superimposed on the output signal of the oscillator mounted on the IC, thus there is a need for an oscillator with excellent noise immunity. Therefore, this embodiment describes an oscillator that can suppress the effects of noise superimposed on the power supply voltage VCC.

[0062] Figure 10 is a circuit diagram showing the configuration of the oscillator 300 according to Embodiment 3. The oscillator 300 has a configuration in which the reference current source 2 of the oscillator 100 according to Embodiment 1 is replaced with a reference current source 5. In addition, the oscillator 300 has an additional capacitance C2 compared to the oscillator 100.

[0063] Reference current source 5 has a configuration in which capacitance C1 is added to reference current source 2. Capacitor C1 is connected to the power supply voltage VCC and the node between the gate of p-type transistor M5 and the gate of p-type transistor M6. The path through which noise superimposed on the power supply voltage is guided via capacitance C1 is also referred to as the first bypass path. Capacitor C1 is also referred to as the first capacitance.

[0064] Capacitor C2 is connected between the drain of p-type transistor M6 and ground (GND). The path through which noise superimposed on the power supply voltage is guided via capacitor C2 is also called the second bypass path. Hereafter, capacitor C2 will also be referred to as the second capacitor.

[0065] Next, noise reduction using capacitors C1 and C2 will be explained. In the reference current source 5, the influence of noise on the p-type transistor M5 can be reduced by providing capacitor C1. In this case, capacitor C1 should be designed so that its impedance is smaller than the impedance of the p-type transistor M5.

[0066] Here, let gm[M5] be the transconductance of the p-type transistor M5. Let f be the frequency of the noise applied to the power supply VCC. In this case, the following equation must hold for the impedance of capacitor C1 to be smaller than the impedance of p-type transistor M5.

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[0067] Furthermore, by providing a capacitance C2 in the oscillator 300, the influence of noise on the p-type transistor M6 on the ring oscillator 3 can be reduced. In this case, the capacitance C2 should be designed such that the impedance of the capacitance C2 to the noise is smaller than the impedance of the p-type transistor M6, as shown in the following equation. Here, when noise of frequency f is applied to the p-type transistor M6, the fluctuation of the drain-source voltage of the p-type transistor M6 is ΔV. DS Let [M6] be the variable. Also, let ΔI be the variation in the drain-source current of the p-type transistor M6. DS Let's call it [M6].

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[0068] As explained above, by designing capacitances C1 and C2 to satisfy equations

[17] and

[19] , the influence of noise on the power supply VCC on the ring oscillator 3 can be effectively reduced.

[0069] Figure 11 shows the eye pattern of the oscillator's output signal when noise is superimposed on the power supply voltage VCC. In Figure 11, ±600mV of noise is superimposed on the power supply VCC. Under these conditions, the eye patterns of oscillator 100 and oscillator 300 were compared. In the eye pattern of oscillator 100, the output signal OUT is spread out, and the eye is considerably narrowed. In contrast, in the eye pattern of oscillator 300, the spread of the output signal OUT is significantly suppressed, and the eye is clearly visible. Thus, in oscillator 300, by providing a noise bypass path, the degradation of the output signal quality due to noise can be effectively suppressed.

[0070] As described above, the oscillator 300 can suppress the influence of noise on the ring oscillator 3 by providing a bypass path for power supply noise propagating to the ring oscillator 3.

[0071] Embodiment 4 In the above-described embodiment, an oscillator in which n-type transistors M1 to M3 and M90 are depletion-type MOS transistors was explained. However, it is also possible to replace some of the n-type transistors M1 to M3 and M90 with enhancement-type MOS transistors.

[0072] Figure 12 is a circuit diagram showing the configuration of the oscillator 400 according to Embodiment 4. The oscillator 400 has a configuration in which the reference current sources 1 and 2 of the oscillator 100 are replaced with reference current sources 11 and 12, respectively. In addition, the oscillator 400 has a bias circuit 21 added compared to the oscillator 100.

[0073] Reference current source 11 has a configuration in which the depletion-type n-type transistor M1 of reference current source 1 is replaced with an enhancement-type n-type transistor M11. Reference current source 12 has a configuration in which the depletion-type n-type transistor M3 of reference current source 2 is replaced with a resistor R2.

[0074] The bias circuit 21 includes enhancement-type n-type transistors M21 and M22, a p-type transistor M23, and a current source CS. The n-type transistors M21 and M22 and the p-type transistor M23 are enhancement-type MOS transistors. Hereinafter, the n-type transistors M21 and M22 and the p-type transistor M23 will also be referred to as the 7th to 9th transistors, respectively.

[0075] The current source CS and the n-type transistor M21 are cascaded between the power supply VCC and ground GND in this order. The current source CS is connected between the power supply VCC and the drain of the n-type transistor M21. The source of the n-type transistor M21 is connected to ground GND. The gate of the n-type transistor M21 is connected to the drain of the n-type transistor M21, the gate of the n-type transistor M22, and the gate of the n-type transistor M11.

[0076] The p-type transistor M23 and the n-type transistor M22 are cascaded between the power supply VCC and the ground GND in this order. The source of the p-type transistor M23 is connected to the power supply VCC. The drain of the p-type transistor M23 is connected to the gate of the p-type transistor M23, the gate of the n-type transistor M13, and the drain of the n-type transistor M22. The source of the n-type transistor M22 is connected to the ground GND. The gate of the n-type transistor M22 is connected to the gate of the n-type transistor M21 and the gate of the n-type transistor M11, as described above.

[0077] Therefore, n-type transistors M11, M21, and M22 constitute a current mirror circuit. N-type transistors M13 and M23 also constitute a current mirror circuit. As a result, a bias voltage generated by the bias circuit 21 is applied to the gates of n-type transistors M11 and M13.

[0078] With this configuration, the oscillator 400 can operate in the same way as the oscillator 100 according to Embodiment 1. Therefore, it can be seen that even if some of the depletion-type transistors included in the oscillator are replaced with enhancement-type transistors, an oscillator capable of similar operation can be obtained.

[0079] Other embodiments Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made that will be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0080] In the above-described embodiment, n-type transistors M90 were provided in the reference current source 1 and the reference current source 11. However, the n-type transistors M90 may be replaced with resistors. In this case, it is preferable to configure the resistors as polysilicon resistors in order to suppress temperature characteristics.

[0081] Each drawing is merely illustrative to illustrate one or more embodiments. Each drawing may be associated with one or more other embodiments rather than with only one specific embodiment. As those skilled in the art will understand, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings, for example, to create embodiments not explicitly shown or described. Not all features or steps shown in any one drawing to illustrate an exemplary embodiment are necessarily required, and some features or steps may be omitted. The order of steps shown in any of the drawings may be changed as appropriate. [Explanation of Symbols]

[0082] 1, 2, 4, 5, 11, 12 Reference current source 3 Ring Oscillator 10 Ring Oscillators 21 Bias Circuit 100, 200, 300, 400 oscillators C1, C2 capacity CS current source D1, D2 diodes GND (Ground) INV to INVm Inverter M1 to M4, M11, M13, M21, M22, MN n-type transistors M5, M6, M23, M61 to M64, MP p-type transistors OUT output signal R1, R2 resistance SW1 to SW4 Switch VCC power supply

Claims

1. A first current source that generates a first current having a positive temperature characteristic corresponding to the power supply voltage output from the power supply, A second current source that generates a second current having a negative temperature characteristic corresponding to the power supply voltage and outputs a reference current obtained by adding the first current and the second current, The device comprises a ring oscillator composed of a plurality of inverters, each of which a first-conductivity transistor and a second-conductivity transistor are complementaryly connected, which outputs an output signal of an oscillation frequency corresponding to the aforementioned reference current. The first current source is, A first diode and a first transistor of a first conductivity type are sequentially connected between the power supply and ground. The system comprises a second transistor of the first conductivity type and a second resistor, which are sequentially connected in cascading order between the second current source and the ground, The control terminal of the second transistor is connected to the node between the first diode and the first transistor. The control terminal of the first transistor is connected to the ground. The second current source is, A third transistor and a second diode of the first conductivity type are sequentially connected between the power supply and the ground. A fourth transistor of the second conductivity type, a fifth transistor of the second conductivity type, and a first resistor are sequentially connected between the power supply and the ground. One end of the sixth transistor of the second conductivity type is connected between the power supply and the ring oscillator, and the fifth transistor and the sixth transistor of the second conductivity type constitute a current mirror. The control terminals of the third and fourth transistors are connected to the anode of the second diode. The second transistor is connected between the node between the fourth transistor and the fifth transistor and the second resistor. Oscillator.

2. The first to third transistors are depletion-type MOS (Metal Oxide Semiconductor) transistors, The fourth to sixth transistors are enhancement-type MOS transistors. The oscillator according to claim 1.

3. The system further includes a bias circuit that supplies a bias voltage to the first current source, The aforementioned bias circuit is A current source and a seventh transistor of the first conductivity type are sequentially connected between the power supply and ground. The system comprises an eighth transistor of the second conductivity type and a ninth transistor of the first conductivity type, which are sequentially connected in cascading order between the power supply and ground. The first, seventh, and eighth transistors constitute a current mirror. The third and ninth transistors described above constitute a current mirror. The first and third to ninth transistors are enhancement-type MOS (Metal Oxide Semiconductor) transistors. The second transistor is a depletion-type MOS transistor. The oscillator according to claim 1.

4. The MOS transistor has a negative temperature characteristic in that the drain-source current is greater than a predetermined value when the gate-source voltage is greater than a predetermined value. The power supply voltage is set to a value such that the gate-source voltages of the first to sixth transistors and the transistors of the ring oscillator are greater than the predetermined value. The oscillator according to claim 2.

5. The sixth transistor includes a plurality of transistors of different sizes connected in parallel. The system comprises a plurality of switches, each inserted between the plurality of transistors and the ring oscillator, The value of the reference current can be switched by switching each of the aforementioned multiple switches. The oscillator according to claim 1.

6. The second current source includes a first bypass path connecting the power supply and the control terminals of the fifth and sixth transistors. The first bypass path is configured to have a lower impedance than the fifth transistor with respect to noise superimposed on the power supply voltage supplied to the fifth transistor. The oscillator according to claim 1.

7. The second current source further comprises the power supply and a first capacitor connected between the node between the control terminals of the fifth and sixth transistors, The oscillator according to claim 6.

8. A second bypass path is provided that connects the second current source and the ground without going through the ring oscillator. The second bypass path is configured to have a lower impedance than the ring oscillator with respect to noise superimposed on the reference current supplied to the ring oscillator. The oscillator according to claim 1.

9. The system further comprises a second capacitance connected between the node between the second current source and the ring oscillator and the ground, The oscillator according to claim 1.

10. The first resistor is configured such that the temperature characteristic of its resistance value is 0 or approximately 0. The oscillator according to claim 1.

11. The first resistor is constructed as a polysilicon resistor. The oscillator according to claim 10.

12. Each of the plurality of inverters of the ring oscillator has a tenth transistor of a first conductivity type to which the reference current is supplied at one end, and an eleventh transistor of a second conductivity type to which one end is connected to the tenth transistor and the other end is connected to the ground, the gates of the tenth and eleventh transistors are connected to each other as inputs to the inverter, and the node between the tenth transistor and the eleventh transistor is an output. The input of the first stage inverter is connected to the output of the last stage inverter, and in the inverters from the second stage to the one before the last stage, the output of the preceding stage inverter is connected to the input of the subsequent stage inverter. The oscillator according to claim 1.

13. The second resistor is a twelfth transistor of the first conductivity type, connected between the second transistor and the ground, with its control terminal connected to the ground. The oscillator according to claim 1.

14. The first conductivity type is n-type, and the second conductivity type is p-type. The oscillator according to claim 1.

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