Memory operation method and apparatus having validity check function

Abstract

The present invention relates to a memory operation method and apparatus having an effectiveness check function, in which a part of a code and an intermediate checksum are stored together in a first nonvolatile memory, and the remaining part of the code and a final checksum of the entire code stored separately in the first nonvolatile memory and the second nonvolatile memory are stored together in a second nonvolatile memory.

Description

Technical Field

[0001] This invention relates to a memory operation method and apparatus applicable to embedded systems. Background Technology

[0002] An embedded system is a computer system implemented by embedding software (or program code) into hardware to perform specific functions. In embedded systems, checksums can be used when writing or reading code from memory to verify the integrity of the software code.

[0003] A typical example of a cyclic checksum is as follows. First, when the 4 bytes of data are 0x25, 0x62, 0x3F, and 0x52, add all these bytes together to get 0x118. Next, discard the carry nibble to get 0x18. In the third step, obtain the two's complement of 0x18, thus obtaining 0xE8 as the checksum byte. To test the checksum byte, add the original byte to the checksum byte to get 0x25 + 0x62 + 0x3F + 0x52 + 0xE8 = 0x200. Discard the carry nibble again to get 0x00. 0x00 indicates that the byte data has no errors.

[0004] In embedded systems, a checksum is calculated before the code is stored in non-volatile memory, and the calculated checksum is stored at the last address in memory. When the embedded system's MCU (Microcontroller Unit) begins reading code, the checksum calculation is repeated every time power is supplied to the embedded system equal to the size of the program code stored in memory. Assuming a memory with N addresses, N additions and discarding carry nibbles are required to complete the checksum calculation, which translates to a computation time of N clock cycles. In MCUs with lower clock frequencies, the checksum calculation takes a significant amount of time before the software (or application code) begins execution, thus delaying the code validity check. Embedded systems typically store a checksum corresponding to the code in non-volatile memory. Summary of the Invention

[0005] The problem that the invention aims to solve

[0006] This invention provides a memory operation method and apparatus that can improve the speed of validity checks of code stored in non-volatile memory in embedded systems.

[0007] Technical solutions to the problem

[0008] A memory operation method according to an embodiment of the present invention includes the steps of: storing a portion of code and an intermediate checksum together in a first non-volatile memory; storing the remaining portion of code and a final checksum for the entire code stored separately in the first non-volatile memory and the second non-volatile memory together in a second non-volatile memory; and calculating and accumulating a first checksum in real time during the process of reading the intermediate checksum stored in the first non-volatile memory and reading the portion of code stored in the first non-volatile memory, and using the intermediate checksum to calculate and accumulate a second checksum in real time during the process of reading the remaining portion of code stored in the second non-volatile memory.

[0009] Multiple codes stored separately in the first non-volatile memory and the second non-volatile memory can be read simultaneously in parallel processing, while the first checksum and the second checksum are calculated and accumulated in real time.

[0010] The second checksum can be accumulated from the first checksum.

[0011] The memory operation method may further include: a step of confirming the integrity of a portion of the code stored in the first non-volatile memory by comparing the intermediate checksum with the first checksum; and a step of confirming the integrity of the entire code stored in the first non-volatile memory and the second non-volatile memory by comparing the final checksum with the second checksum.

[0012] While comparing the intermediate checksum with the first checksum, the final checksum can also be compared with the second checksum.

[0013] The memory operation method may further include: writing the intermediate checksum after sequentially writing a portion of the code into the first non-volatile memory; and writing the final checksum after sequentially writing the remaining portion of the code into the second non-volatile memory. Before the final checksum is written into the second non-volatile memory, the first intermediate checksum may be written into the first non-volatile memory as the intermediate checksum.

[0014] A memory operation device according to an embodiment of the present invention includes: a first non-volatile memory; The Nth (N is a positive integer greater than or equal to 2) non-volatile memory; and the central processing unit, memory control unit, communication interface, and volatile memory are connected to the first non-volatile memory and the Nth non-volatile memory via a bus. The memory control unit is configured to, when N is 2, store a portion of the code together with an intermediate checksum for that portion of the code in the first non-volatile memory, and store the remaining portion of the code together with a final checksum for the entire code stored in the first and second non-volatile memories in the second non-volatile memory. During the process of reading the intermediate checksum from the first non-volatile memory and reading the portion of the code stored in the first non-volatile memory, the memory control unit calculates and accumulates a first checksum in real time; during the process of reading the remaining portion of the code stored in the second non-volatile memory, it calculates and accumulates a second checksum in real time.

[0015] Invention Effects

[0016] According to embodiments of the invention, in embedded systems, intermediate checksums generated and stored internally during steps stored in multiple non-volatile memories enable parallel processing of validity checks that compare with real-time calculated checksums across multiple non-volatile memories. This improves the overall code validity check speed stored in multiple non-volatile memories. Consequently, the present invention improves the overall application software startup speed of embedded systems by increasing the initial integrity check speed of low-speed MCUs.

[0017] The effects of this invention are not limited to those mentioned above, and those skilled in the art can clearly understand other effects not mentioned from the description of the claims. Attached Figure Description

[0018] Figure 1 and Figure 2 This is a diagram illustrating the configuration of a memory operation apparatus according to an embodiment of the present invention.

[0019] Figure 3 This is a flowchart illustrating a method for writing to a non-volatile memory according to an embodiment of the present invention.

[0020] Figure 4 This diagram illustrates in detail an example of a method for writing non-volatile memory when it is divided into two parts.

[0021] Figure 5 This is a flowchart illustrating a method for reading a non-volatile memory according to an embodiment of the present invention.

[0022] Figure 6 This diagram illustrates in detail an example of a method for reading non-volatile memory when it is divided into two parts. Detailed Implementation

[0023] The advantages and features of the present invention, as well as the methods of implementing them, will become clear with reference to the accompanying drawings and the detailed embodiments described below. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to complete the disclosure of the invention and to fully inform those skilled in the art to which this invention pertains. The invention is defined only by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to illustrate embodiments of the present invention are illustrative, and therefore the present invention is not limited to the content shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same constituent elements. Furthermore, in describing the present invention, detailed descriptions of relevant prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention.

[0025] When terms such as “possessing,” “including,” “having,” and “consisting of” are used in this specification, additional parts may be added unless “only” is used. When a constituent element is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0026] When interpreting constituent elements, even without other explicit statements, it is interpreted as including a range of error.

[0027] When describing the positional and interconnected relationships between two constituent elements such as “~above”, “~upper part”, “~lower part”, “~beside”, “~connect or couple”, “~crossing, intersecting”, unless “immediately” or “directly” is mentioned, one or more other constituent elements may be set between these constituent elements.

[0028] When describing temporal relationships such as "after," "followed by," "next," or "before," the timeline may not be continuous unless "immediately" or "directly" is used.

[0029] To distinguish the constituent elements, terms such as "first" and "second" can be used, but the function or structure of these constituent elements is not limited by the ordinal number or the name of the constituent element added before it.

[0030] The embodiments described below can be combined or integrated with each other, either partially or entirely, and can be linked and driven in various ways. The embodiments can be implemented independently or in a related manner.

[0031] Hereinafter, "code" includes the operating system (OS), applications, and data that can be stored in memory. Data here includes configuration data and user data for internal and external peripheral devices connected to the embedded system.

[0032] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 and Figure 2 This is a diagram illustrating a memory operation device according to an embodiment of the present invention. The memory operation device 100 may be an MCU (Microcontroller Unit) of an embedded system.

[0034] Reference Figure 1 and Figure 2 The memory operation device 100 includes a central processing unit (hereinafter referred to as "") 110, a non-volatile memory 120, a memory control unit 130, a communication interface 140, a volatile memory 150, and a bus 160 that connects the plurality of constituent elements 110 to 150 of the memory operation device 100 to provide signal transmission paths.

[0035] CPU 110 processes the execution of application programs and commands written in code stored in non-volatile memory 120, and performs calculations. Communication interface 140 supports standard interfaces for data communication between external peripheral devices and memory operation device 100, such as UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), I2C, USB (Universal Serial Bus), and other serial communication interfaces. Volatile memory 150 may include memory for temporary data storage, such as SRAM (Static Random Access Memory).

[0036] The memory operation device 100 includes a first pin 101 and a second pin 102 for inputting / outputting code or data. The first pin 102 may be a JTAG (Joint Test Action Group) pin. The first pin 102 provides code to the CPU 110 during debugging, flash programming, board testing, inter-chip testing, and other processes. The second pin 102 may be a communication interface pin for connecting to peripheral devices. Through the plurality of pins 101 and 102, code to be stored in the non-volatile memory 120, the final checksum of the entire code, or data read from the non-volatile memory 120 can be received and transmitted to external peripheral devices. As an example of a checksum, CRC (Cyclic Redundancy Check) can be used, but it is not limited to this.

[0037] The non-volatile memory 120 can be flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), etc., but is not limited to these. The non-volatile memory 120 divides the stored code into segments and stores intermediate and final checksums for the segmented code. The non-volatile memory 120 can be divided into N (N being a positive integer greater than 2) or more memory segments for write and read operations, either by software or hardware. In software, a single non-volatile memory segment containing code to be read and written can be divided into N memory segments. When N is 2, the code of the first data group corresponding to half of the total code is read and written to the first memory region of the non-volatile memory, and the code of the second data group corresponding to the remaining half can be read and written to the second memory region of the non-volatile memory. The intermediate checksum is a value that verifies whether the code stored in each memory region is corrupted when confirming the integrity of the code stored in the N non-volatile memories. It allows for parallel processing of the validity check used to verify the integrity of the code during the reading of the code stored in the non-volatile memory, thereby minimizing the validity check time. The hardware approach divides and reads and writes code into N physically separated non-volatile memories, and can store intermediate checksums into the smallest (N-1) of these memories.

[0038] The first data group code and an intermediate checksum generated for the first data group code, such as a first checksum CS1, are stored together in the first non-volatile memory 121. The second data group code and an accumulated intermediate checksum for the first and second data groups code, such as a second checksum, are stored together in the second non-volatile memory 122. The third data group code and a final checksum FCS for the entire code stored separately in the first to the Nth non-volatile memories 121, 122, and 123 are stored together in the Nth non-volatile memory 123.

[0039] The memory control unit 130 can control the writing and reading of code in the non-volatile memory 120, and calculate and generate intermediate checksums CS1, CS2 and the final checksum FCS. The memory control unit 130 can... Figures 3 to 5 The memory operation method shown performs memory read / write operations and checksum calculations. The final checksum (FCS) is a checksum of the entire code stored in the non-volatile memory 120. When the non-volatile memory 120 is flash memory, it may include N Flash Prigram IPs (Intellectual Property) responsible for dividing the non-volatile memories 121, 122, and 123 into N units, and N checksum calculators 131-133. The N non-volatile memories can be interpreted as the N memory cells included in the flash memory.

[0040] The memory operation device 100 also includes Figure 2 The memory selector 111 and comparators 112-115 are shown. The memory selector 111 and comparators 112-115 may be physical components controlled by the CPU 110 or the memory control unit 130, or be part of a program executed by the CPU 110 or the memory control unit 130.

[0041] The memory selector 111 divides the input raw code into memory regions of each non-volatile memory 121, 122, and 123 and transmits them sequentially to the non-volatile memories 121, 122, and 123. When the raw code is divided into the first data group to the Nth data group, after the first data group is stored in the first non-volatile memory 121, the second data group is stored in the second non-volatile memory 122, and then the Nth data group can be stored in the Nth non-volatile memory 123.

[0042] When storing the original code in the first to Nth non-volatile memories 121, 122, and 123, intermediate checksums are calculated for each memory. For example, when the code storing the first data group is written to the first non-volatile memory 121, the first checksum calculator 131 calculates the first checksum of the code of the first data group in real time. When the code storing the second data group is written to the second non-volatile memory 122, the second checksum calculator 132 calculates the second checksum in real time using the accumulated value for the code of adding the first data group stored in the first non-volatile memory and the second data group stored in the second non-volatile memory 122. When the code storing the Nth data group is written to the third non-volatile memory 123, the Nth checksum calculator 133 calculates the final checksum in real time using the accumulated value for the original complete code stored separately in the first to Nth non-volatile memories 121, 122, and 123.

[0043] The first comparator to the Nth comparator 112, 113, 114 compare the intermediate checksums calculated in real time according to the memory regions of each non-volatile memory 121 to 123 with the intermediate checksums read from the corresponding memory 121 to 123 stored in the checksums of the non-volatile memory 121 to 123 in parallel, and can output their comparison results at the same time.

[0044] The first comparator 112 compares the real-time calculated value of the first checksum input from the first checksum calculator 131 with the first checksum CS1 read from the first non-volatile memory 121. When the first checksum CS1 read from the first non-volatile memory 121 is the same as the real-time calculated value of the first checksum, the first comparator 112 outputs a first logical value indicating that the code stored in the first non-volatile memory 121 is valid data; otherwise, it outputs a second logical value. The first logical value can be "1" (or "high"), and the second logical value can be "0" (or "low"), but is not limited to these.

[0045] The second checksum calculator 132 uses the first checksum CS1 value and the stored value in the second non-volatile memory 122 to calculate the second checksum. The second comparator 113 compares the second checksum input from the second checksum calculator 132 with the second checksum CS2 read from the second non-volatile memory 122. The second checksum output from the second checksum calculator 132 is an intermediate checksum calculated by accumulating the sum of the first and second data groups stored separately in the first and second non-volatile memories 121 and 122. When the second checksum CS2 read from the second non-volatile memory 122 is the same as the real-time calculated value of the second checksum input from the second checksum calculator 132, the second comparator 113 outputs a first logical value indicating that the code stored in the second non-volatile memory 122 is valid data; otherwise, it outputs a second logical value.

[0046] The Nth comparator 114 compares the final checksum input from the Nth checksum calculator 133 with the final checksum FCS read from the Nth non-volatile memory 123. When the final checksum FCS read from the Nth non-volatile memory 123 is the same as the real-time calculated value of the final checksum input from the Nth checksum calculator 133, the Nth comparator 114 outputs a first logical value indicating that the code stored in the Nth non-volatile memory 123 is valid data; otherwise, it outputs a second logical value.

[0047] The output signals of the first comparators to the Nth comparators 112, 113, and 114 can be simultaneously input to the final comparator 115. When the output signals of the first to the Nth comparators 112, 113, and 114 are all first logic values, the final comparator 115 outputs a first logic value indicating that the entire code stored in the first to the Nth non-volatile memories 121, 122, and 123 is valid and without defects. Conversely, when one or more of the output signals of the first to the Nth comparators 112, 113, and 114 are second logic values, the final comparator 115 outputs a second logic value indicating that the code read from the first to the Nth non-volatile memories 121, 122, and 123 is defective. The output signal of the final comparator 115 can be transmitted to components requesting data read from the plurality of non-volatile memories 121, 122, and 123.

[0048] Figure 3 This is a flowchart illustrating a method for writing to a non-volatile memory according to an embodiment of the present invention.

[0049] Reference Figure 3 The original overall code and the final checksum (W1) of the original overall code are input into the memory operation device 100.

[0050] The memory operation device 100 can divide the non-volatile memory into a plurality of memories (W2) that divide and store the original code.

[0051] The memory operation device 100 divides and stores the original code into segments based on distinct memory regions within the non-volatile memory. Each memory region can be a non-volatile memory. The memory operation device 100 accumulates the addresses of the non-volatile memory segments containing the written code and calculates intermediate checksums. This process of storing the segmented code in one non-volatile memory and then storing the intermediate checksum of that segmented code is repeated until all the original code (W3~W8) is stored in N non-volatile memory segments. Therefore, before storing the entire original code in the non-volatile memory, more than one intermediate checksum can be calculated and stored in the corresponding non-volatile memory segment.

[0052] All original code is stored in N non-volatile memories, and the final checksum calculated in real time is compared with the final checksum of the input. When the final checksum calculated in real time is the same as the final checksum of the input, the memory operation device 100 confirms the code stored in the plurality of non-volatile memories as defect-free integrity data (W10). If the final checksum comparison results (W9 and W10) determine that the code stored in the plurality of non-volatile memories is defective, then W3 to W10 are repeated, and the original code is stored again in the plurality of non-volatile memories and the validity of the stored code is checked.

[0053] Figure 4 This diagram illustrates in detail an example of a method for writing non-volatile memory when it is divided into two parts. This method of writing non-volatile memory can be, but is not limited to, writing code into the memory during the production of the embedded system to store initial code or during code updates during the use of the embedded system after the product has left the factory. Figure 4 The "Write clock" is the clock used when writing code to the non-volatile memory. "External communication read" indicates the process of serially inputting code from an external source via pins 101 and 102. When the non-volatile memory is divided into two parts, "Write 1" is the process of writing code to the first non-volatile memory, and "Write 2" is the process of writing code to the second non-volatile memory. Figure 4 In this context, "C1~C(N)" represents the original code that is segmented and stored in the first and second non-volatile memories. In this embodiment, it is assumed that during the write clock "0", the checksums of the plurality of non-volatile memories are initialized to CS=0.

[0054] Reference Figure 4The raw code received from the outside is written to the first non-volatile memory 121 starting from the first write clock 1. In each write clock, the checksum is accumulated when code is written to the first non-volatile memory.

[0055] For example, when C1 is input to the first write clock 1 via pins 101 and 102, the first checksum CS1 accumulates to CS1 = CS + C1. When C2 is input to the second write clock 2, C1 is written to the first non-volatile memory, and the first checksum CS1 is accumulated and becomes CS1 = CS1 + C2. Then, when C3 is input to the third write clock 3, C2 is written to the first non-volatile memory, and the first checksum CS1 is accumulated and becomes CS1 = CS1 + C3. When C(N / 2) is input to the N / 2nd write clock (N / 2) and C(N / 2) - 1 is written to the first non-volatile memory, the first checksum CS1 is accumulated and becomes CS1 = CS1 + C(N / 2). Simultaneously, while writing clock ((N / 2)+1) inputs C(N / 2)+1 and writing C(N / 2) to the first non-volatile memory, the accumulated value of the first checksum CS1, CS1 = CS1 + C(N / 2)+1, is stored in the first non-volatile memory. The first checksum CS1 is an intermediate checksum used for validity checks of the code stored in the first non-volatile memory. In this way, after storing half of the original code in the first non-volatile memory, the remaining half of the code is sequentially stored in the second non-volatile memory.

[0056] While inputting C(N / 2)+2 to the (N / 2)+2nd write clock ((N / 2)+2) and writing C(N / 2)+1 to the second non-volatile memory, the second checksum CS2 begins to accumulate and becomes CS2=CS1+C(N / 2)+2. Then, while inputting C(N / 2)+3 to the (N / 2)+3th write clock (omitted in the diagram) and writing C(N / 2)+2 to the second non-volatile memory, the second checksum CS2 accumulates and becomes CS2=CS2+C(N / 2)+3. While inputting C(N-1) to the (N-1)th write clock (N-1) and writing C(N-2) to the second non-volatile memory, the second checksum CS2 accumulates and becomes CS2=CS2+C(N-1). While inputting C(N) to the Nth write clock (N) and writing C(N-1) to the second non-volatile memory, the second checksum CS2 is accumulated and becomes CS2=CS2+C(N).

[0057] If no code is input at the (N+1)th write clock, while writing C(N) to the second non-volatile memory, a comparator compares the final checksum FCS, which is input to the memory operation device 100 along with the original code, with the second checksum CS2, which is calculated in real time. The final checksum FCS received along with the original code can be temporarily stored in the volatile memory 150 and then compared with the second checksum CS2 at the (N+1)th write clock. When the accumulated second checksum CS2 is the same as the input final checksum FCS, the integrity of the code stored separately in the first and second non-volatile memories is confirmed. At this time, a first logic value can be output from the comparator, and the checksum calculation ends. When the second checksum CS2 is inconsistent with the final checksum FCS, a second logic value can be output from the comparator. At the (N+2)th write clock, the final checksum FCS can be stored in the second non-volatile memory.

[0058] Figure 5 This is a flowchart illustrating a method for reading a non-volatile memory according to an embodiment of the present invention.

[0059] Reference Figure 5 The memory operation device 100 can perform parallel processing while reading N non-volatile memories and writing an application program with code stored in N non-volatile memories.

[0060] First, the memory operation device 100 reads intermediate checksums (R1) pre-stored in a plurality of non-volatile memories. Then, the memory operation device 100 simultaneously reads codes stored in N non-volatile memories, accumulates the code values ​​in real time, and calculates the checksum (R2).

[0061] Next, the memory operation device 100 simultaneously verifies the integrity of the code stored in the plurality of non-volatile memories by comparing the checksums calculated in real time by each of the N non-volatile memories with the pre-stored checksums, thereby performing a validity check of the overall code (R3). If the integrity of the code stored in the plurality of non-volatile memories as a whole is verified, the application program written using the code can be executed (R4).

[0062] Figure 6 This diagram illustrates in detail an example of a method for reading non-volatile memory when it is divided into two parts. Figure 4 The "read clock" is the clock used when reading code from non-volatile memory. When the non-volatile memory is divided into two parts, "Read1" is the process of reading code stored in the first non-volatile memory, and "Read2" is the process of reading code stored in the second non-volatile memory. Figure 4 In this code, "C1~C(N)" represents the code stored in the first non-volatile memory and the second non-volatile memory. "Checksum Calculation 1" is the intermediate checksum calculation process performed in real time as the code stored in the first non-volatile memory is read sequentially. "Calculation 2" is the intermediate checksum calculation process performed in real time as the code stored in the second non-volatile memory is read sequentially. The first and second non-volatile memories are accessed in parallel, the code stored in these multiple non-volatile memories is read simultaneously, and the intermediate checksums of each of the multiple non-volatile memories are calculated simultaneously in real time.

[0063] Reference Figure 6 The memory operation device 100 first reads intermediate checksums stored in a plurality of non-volatile memories at the first read clock 1, such as the first checksum CS1 stored in the first non-volatile memory. At the same time, whenever code is read, the first checksum CS1, which is calculated in real time, is initialized to CS=0, and the second checksum CS2 is initialized to the first checksum CS1 read from the first non-volatile memory (CS2=CS1).

[0064] During the second read clock 2, while reading C1 from the first non-volatile memory, the real-time calculated first checksum CS is accumulated and becomes CS = CS + C1. During the second read clock 2, while reading C(N / 2) + 1 from the second non-volatile memory, the real-time calculated second checksum CS2 is accumulated and becomes CS2 = CS2 + C(N / 2) + 1. During the third read clock 3, while reading C2 from the first non-volatile memory, the real-time calculated first checksum CS is accumulated and becomes CS = CS + C2. During the third read clock 3, while reading C(N / 2) + 2 from the second non-volatile memory, the real-time calculated second checksum CS2 is accumulated and becomes CS2 = CS2 + C(N / 2) + 2.

[0065] At the N / 2nd read clock (N / 2), while reading C(N / 2)-1 from the first non-volatile memory, the real-time calculated first checksum CS is accumulated and becomes CS=CS+C(N / 2)-1. At the N / 2nd read clock (N / 2), while reading C(N-1) from the second non-volatile memory, the real-time calculated second checksum CS2 is accumulated and becomes CS2=CS2+C(N-1). At the (N-2)+1nd read clock ((N-2)+1), while reading C(N / 2) from the first non-volatile memory, the real-time calculated first checksum CS is accumulated and becomes CS=CS+C(N / 2). At the (N-2)+1st read clock ((N-2)+1), while reading C(N) from the second non-volatile memory, the real-time calculated second checksum CS2 is accumulated and becomes CS2=CS2+C(N / 2).

[0066] At the N / 2+2nd read clock ((N / 2)+2), the first checksum CS, calculated in real time during the read process, is compared by a comparator with the first checksum CS1 stored in the first non-volatile memory. When the first checksum CS calculated in real time is the same as the first checksum stored in the first non-volatile memory, the integrity of the code stored in the first non-volatile memory is confirmed. At the N / 2+2nd read clock ((N / 2)+2), the second checksum CS2, calculated in real time during the read process, is compared by a comparator with the final checksum FCS stored in the second non-volatile memory. The final checksum FCS is the final checksum of the entire original code. When the second checksum CS2 calculated in real time is the same as the final checksum FCS stored in the second non-volatile memory, the read of the first and second non-volatile memories can be terminated at the N / 2+3rd read clock ((N / 2)+3) after confirming the integrity of the overall code stored in the first and second non-volatile memories. At the N / 2+3rd clock read ((N / 2)+3), the comparator outputs a first logic value confirming the integrity of the overall code stored in the first and second non-volatile memories. When the second checksum CS2 is different from the final checksum FCS, the comparator outputs a second logic value.

[0067] The memory operation device described in this embodiment can be applied to embedded systems such as home appliances, automobiles, medical devices, communication systems, aerospace systems, smart homes, and IoT devices.

[0068] The description of the problem to be solved, the technical solution to the problem, and the technical effects described above does not limit the essential features in the claims. Therefore, the scope of the claims is not limited by the matters described in the description.

[0069] The embodiments of the present invention have been described in more detail above with reference to the accompanying drawings. However, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in this invention are not intended to limit the technical spirit of the present invention, but are for illustrative purposes, and these embodiments do not limit the scope of the technical spirit of the present invention. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

[0070] Other ways of carrying out the invention

[0071] A memory operation method according to an embodiment of the present invention includes the steps of: storing a portion of code and an intermediate checksum together in a first non-volatile memory; storing the remaining portion of code together in a second non-volatile memory and storing a final checksum for the entire code separately stored in the first non-volatile memory and the second non-volatile memory in the second non-volatile memory; and calculating and accumulating a first checksum in real time during the process of reading the intermediate checksum stored in the first non-volatile memory and reading the portion of code stored in the first non-volatile memory, and using the intermediate checksum to calculate and accumulate a second checksum in real time during the process of reading the remaining portion of code stored in the second non-volatile memory.

[0072] Industrial application potential

[0073] An embedded system is a computer system implemented by embedding software (or program code) into hardware to perform specific functions. In embedded systems, checksums can be used when writing or reading code from memory to verify the integrity of the software code.

[0074] The memory operation device described in this embodiment can be applied to embedded systems such as home appliances, automobiles, medical devices, communication systems, aerospace systems, smart homes, and IoT devices.

Claims

1. A memory operation method, wherein, include: The step of storing a portion of the code together with the intermediate checksum in the first non-volatile memory; The steps include storing the remainder of the code together in the second non-volatile memory, and storing the final checksum of the code as a whole, which is separately stored in the first non-volatile memory and the second non-volatile memory, in the second non-volatile memory. as well as The steps include: calculating and accumulating a first checksum in real time during the process of reading the intermediate checksum stored in the first non-volatile memory and reading a portion of the code stored in the first non-volatile memory; and using the intermediate checksum to calculate and accumulate a second checksum in real time during the process of reading the remaining portion of the code stored in the second non-volatile memory.

2. The memory operation method according to claim 1, wherein, Multiple codes stored separately in the first non-volatile memory and the second non-volatile memory are read simultaneously in parallel processing, while the first checksum and the second checksum are calculated and accumulated in parallel in real time.

3. The memory operation method according to claim 2, wherein, The second checksum is accumulated from the first checksum.

4. The memory operation method according to claim 3, wherein, Also includes: The step of verifying the integrity of a portion of the code stored in the first non-volatile memory by comparing the intermediate checksum with the first checksum; as well as The step of verifying the integrity of the code stored in the first non-volatile memory and the second non-volatile memory by comparing the final checksum with the second checksum.

5. The memory operation method according to claim 4, wherein, While comparing the intermediate checksum with the first checksum, the final checksum is also compared with the second checksum.

6. The memory operation method according to claim 1, wherein, Also includes: The step of writing the intermediate checksum after sequentially writing a portion of the code into the first non-volatile memory; as well as The step of writing the final checksum after the remaining portion of the code is sequentially written to the second non-volatile memory; Before the final checksum is written to the second non-volatile memory, the first intermediate checksum is written to the first non-volatile memory as the intermediate checksum.

7. A memory operation device, wherein, include: First non-volatile memory; The Nth non-volatile memory, where N is a positive integer greater than 2; as well as The central processing unit, memory control unit, communication interface, and volatile memory are connected to the first non-volatile memory and the Nth non-volatile memory via a bus. The memory control unit is configured such that, When N is 2, a portion of the code is stored together with an intermediate checksum for that portion of the code in the first non-volatile memory, and the remainder of the code is stored together with the final checksum for the entire code stored in the first and second non-volatile memories in the second non-volatile memory. During the process of reading the intermediate checksum from the first non-volatile memory and reading a portion of the code stored in the first non-volatile memory, a first checksum is calculated and accumulated in real time, and during the process of reading the remaining portion of the code stored in the second non-volatile memory, a second checksum is calculated and accumulated in real time.

8. The memory operation apparatus according to claim 7, wherein, The memory control unit reads multiple codes stored separately in the first non-volatile memory and the second non-volatile memory simultaneously in parallel processing, and calculates and accumulates the first checksum and the second checksum in real time.

9. The memory operation apparatus according to claim 7, wherein, The second checksum is accumulated from the first checksum.

10. The memory operation apparatus according to claim 9, wherein, The memory control unit is configured such that, The integrity of the portion of code stored in the first non-volatile memory is confirmed by comparing the intermediate checksum with the first checksum. as well as The integrity of the code stored in the first non-volatile memory and the second non-volatile memory is confirmed by comparing the final checksum with the second checksum.

11. The memory operation apparatus according to claim 10, wherein, The memory control unit compares the intermediate checksum with the first checksum, and at the same time compares the final checksum with the second checksum.

12. The memory operation apparatus according to claim 7, wherein, The memory control unit is configured such that, After storing a portion of the code sequentially in the first non-volatile memory, the intermediate checksum is stored; After the remaining portion of the code is stored sequentially in the second non-volatile memory, the final checksum is stored.

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