A clock system based on feeder terminal and calibration method
By using a hardware timer and a counter difference correction based on GPS or 8025t second pulse output, the problems of crystal oscillator aging and interrupt priority in the feeder terminal clock system are solved, achieving high-precision microsecond counting and overflow protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- QINGDAO DINGJUN ELECTRIC CO LTD
- Filing Date
- 2025-06-11
- Publication Date
- 2026-06-19
AI Technical Summary
The clock system of the feeder terminal is inaccurate due to crystal oscillator aging and interrupt priority.
Employing a hardware timer and GPS or 8025t second pulse output function, the crystal oscillator frequency is dynamically corrected through counter difference. Combined with dual counting units and calibration units, the clock system achieves precision calibration and overflow protection.
The accuracy of the clock system has been improved, the impact of crystal oscillator frequency offset and interrupt priority has been reduced, and more accurate microsecond counting and overflow protection have been achieved.
Smart Images
Figure CN122239892A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of clock systems for feeder terminals, and specifically relates to a clock system and calibration method based on a feeder terminal. Background Technology
[0002] The feeder terminal is a device installed on 10kV distribution network overhead lines. It has three remote functions (remote signaling, remote measurement, and remote control), power management, conventional protection, low current grounding protection, and security encryption. It integrates high-precision electronic sensing, multi-level fault protection algorithms, and IoT communication modules. It can monitor 10kV line current and voltage parameters in real time, achieve millisecond-level accurate identification and isolation of faults such as overcurrent, short circuit, and grounding, and quickly restore power supply to non-faulty sections, thereby effectively improving the reliability of line power supply.
[0003] The feeder terminal requires a clock system to maintain program operation and time recording functionality. In the current feeder terminal clock system, interrupt interval parameters are set for either the internal hardware timer or the software timer in the operating system. Interrupts are generated periodically by the timer, and the system clock's millisecond or microsecond variables are accumulated within the timer's interrupt function, thus maintaining the feeder terminal's clock system.
[0004] The accuracy of the current feeder terminal's clock system depends on the frequency offset of the internal or external crystal oscillator. However, these oscillators age over time and with temperature changes, causing frequency shifts. Furthermore, the system clock relies on timer interrupts, which are not the highest priority and can be interrupted by other interrupts, leading to inaccurate system clock performance. Summary of the Invention
[0005] To address the problems existing in the prior art, this invention provides a clock system and calibration method based on a feeder terminal, which solves the problem of frequency offset and interruption affecting accuracy caused by crystal oscillator aging from the perspective of clock system implementation.
[0006] The technical solution adopted by this invention to solve its technical problem is as follows: a calibration method for a clock system based on a feeder terminal, comprising:
[0007] Enable the hardware timer of the main control chip, configure the up counter, set the overflow comparison value of the counter to the power of 2 and enable the overflow interrupt, where n is the number of bits of the counter;
[0008] Crystal oscillator frequency correction: Enable the second pulse output function of GPS or 8025t, connect the second pulse output pin of GPS or 8025t to the highest priority interrupt pin of the main control chip, enable the interrupt function of this pin, record the value of the counter register of the hardware timer each time, and dynamically correct the crystal oscillator frequency by calculating the convergence value of the counter difference D between adjacent second pulse interrupts.
[0009] Counting assignment: Obtain the value of the hardware timer's counter register with a period of T seconds, divide this register value by D, add the integer part to the system clock's second count value, take the remainder of this value with respect to D, and reassign the remainder part to the hardware timer's counter register, executing a period of T less than 2 to the power of n clock frequencies.
[0010] Preferably, in the counting assignment, the value of the counter register at the time of the current interrupt is compared with the value of the counter register of the hardware timer at the time of the previous interrupt. If the difference D converges to the value N in M consecutive interrupts, then D is considered to be the oscillation frequency of the internal or external crystal oscillator per second. The value of M ranges from 1 to 60, and the value of N depends on the accuracy or clock frequency of different GPS or 8025t.
[0011] Preferably, in the counting assignment, the D value is updated every T seconds, and the latest D value is used for each rounding and remainder calculation.
[0012] Preferably, it further includes: synchronous counting, whereby the main control program re-acquires the register value of the counter when using the system clock, divides this register value by D, adds the integer part to the second count value of the system clock, takes the remainder of this value with respect to D, and assigns the remainder part to the microsecond count variable.
[0013] Preferably, n is 32 and T is less than 2^32 clock frequencies.
[0014] Preferably, the counter register value of the hardware timer increments by 1 every 1Hz. Therefore, the counter needs to overflow after every 2^32 clock cycles, generating a timer overflow interrupt, and the timer counter will restart counting from 0.
[0015] Preferably, an alarm function for abnormal overflow of the clock system is added to the timer overflow interrupt to monitor and alert to abnormalities in the clock system.
[0016] A clock system based on a feeder terminal includes:
[0017] Hardware timer;
[0018] The system clock has a built-in second counting unit for counting seconds and a microsecond counting unit for counting microseconds. The microsecond counting unit realizes the microsecond timing of the clock system by periodically reading the counter value of the hardware timer.
[0019] The calibration unit includes a GPS module or an 8025t chip, which connects the second pulse output pin of the GPS or 8025t chip to the highest priority interrupt pin of the main control chip. The GPS module or 8025t chip has a built-in execution program that implements the crystal oscillator frequency correction and count assignment described in this application.
[0020] The system clock is connected to the hardware timer signal, and the system clock and hardware timer are respectively connected to the calibration unit signal.
[0021] Preferably, the GPS module or 8025t chip also has a built-in execution program that implements the synchronous counting described in this application.
[0022] Preferably, the hardware timer is configured as a 32-bit up counter with an input frequency of 1MHz, the overflow comparison value is set to 2^32 and the overflow interrupt is enabled; the second counting unit and the microsecond counting unit use 32-bit unsigned number variables for counting.
[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0024] 1. Compared to the previous method of using timer interrupts, the microsecond timing of the clock system is achieved by periodically reading the counter value of the hardware timer. This eliminates the need for interrupt counting, reduces the problem of system clock inaccuracy caused by timer interrupt priority, improves the accuracy of the clock system, and makes the counting more accurate.
[0025] 2. Compared to the previous solution, this clock system uses the second pulse output function of the GPS module or the 8025t chip to periodically measure the frequency deviation of the internal or external crystal oscillator of the chip, thereby realizing the periodic calibration function of the clock system accuracy. This reduces the problem of the crystal oscillator frequency deviation increasing over time or due to temperature aging, resulting in more accurate counting.
[0026] 3. During the counting assignment, the hardware timer's counter register is periodically converted into a second count to prevent the counter register from overflowing upwards, thus achieving overflow protection.
[0027] In summary, the present invention sets up a system clock with dual counting units and a calibration unit based on the clock system of the feeder terminal to realize a calibration method for microsecond counting that takes into account the overflow prevention design. This method has calibration function and overflow prevention counting design, removes the impact of interrupt priority on the accuracy of the clock system, and can achieve more accurate microsecond counting. Attached Figure Description
[0028] Figure 1 This is a block diagram of a clock system based on a feeder terminal. Detailed Implementation
[0029] To facilitate understanding of the present invention, it will be described in more detail below with reference to the accompanying drawings and specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention.
[0030] Example 1: Combination Figure 1 Understanding a clock system calibration method based on a feeder terminal, comprising:
[0031] The system clock is configured to use two 32-bit unsigned variables: one for counting seconds and one for counting microseconds. Each system restart initializes the second and microsecond values by reading the 8025t clock signal.
[0032] During system initialization, the hardware timer function of the main control chip is enabled, the input frequency of the hardware timer is set to 1MHz, the hardware timer is set to up-counting mode, the hardware timer counter is 32-bit, the hardware timer is enabled, the overflow comparator value of the timer is configured to 2^32, and the overflow interrupt of the hardware timer is enabled. At this time, the value of the hardware timer counter register starts to count up by 1 every 1Hz. It takes 2^32 clock frequencies (i.e., 2^32 / 1000000 seconds, approximately equal to 4295 seconds) for the counter to overflow and generate a timer overflow interrupt. The timer counter then restarts counting up from 0.
[0033] To enable the second pulse output function of the GPS or 8025t, connect the GPS or 8025t second pulse output pin to the highest priority interrupt pin of the main control chip, enabling the interrupt function of this pin. In the interrupt function of this pin, record the value of the hardware timer counter register each time, and compare the current counter register value with the value of the hardware timer counter register in the previous interrupt function. If the difference D converges to the value N in M consecutive interrupts, then D is considered to be the oscillation frequency of the chip's internal or external crystal oscillator per second. This value is updated once every T seconds. The value of M ranges from 1 to 60, depending on the different GPS or 8025t modules, and the time from power-on to precise synchronization is approximately between 1 and 60 seconds. The value of N depends on the accuracy or clock frequency of different GPS or 8025t modules, and generally needs to be set according to the relevant specifications or experience. For example, when using the second pulse output function of the L76K module, M is generally set to 10 and N to 200.
[0034] In the main control program's tasks, if an operating system is involved, considering the inter-thread access to the system clock, the operations within this step need to be protected within a critical code section of the operating system. Perform the following operations at a period of T seconds (the execution period must be less than 2^32 clock cycles to prevent microsecond overflow of the system clock, which could lead to system clock anomalies):
[0035] a. Obtain the value of the hardware timer's counter register, divide this value by D, add the integer part to the system clock's second count value, take the remainder of this value divided by D, and reassign the remainder to the hardware timer's counter register to make the hardware counter continue counting.
[0036] b. The D value updated every T seconds is used every time step a is performed.
[0037] The purpose of this operation is to periodically convert the hardware timer's counter register into a second count to prevent the counter register from overflowing and causing system clock abnormalities.
[0038] When the main control program uses the system clock, it retrieves the register value of the counter, divides this register value by D, adds the integer part to the second count value of the system clock, takes the remainder of this value with respect to D, and assigns the remainder to the microsecond count variable. At this time, the second and microsecond clocks of the system clock are synchronized and available for application use.
[0039] Add a flag alarm function for abnormal overflow of the clock system to the timer overflow interrupt, so as to monitor and prompt abnormalities of the clock system.
[0040] In this solution, the system clock's microsecond count automatically increments on the hardware timer counter, eliminating the need for interrupts and reducing inaccuracies caused by timer interrupt priority. Compared to previous methods relying on timer interrupts, this system clock count is more accurate. The crystal oscillator frequency is periodically measured using the second pulse output function of an external GPS or 8025T chip, mitigating the problem of increasing frequency deviation due to crystal aging over time or temperature. Compared to previous solutions, this approach includes a calibration function, and since the system clock accuracy depends on the external crystal oscillator, it achieves more precise microsecond counting. The clock system count also features overflow protection.
[0041] A clock system based on a feeder terminal includes:
[0042] The hardware timer is configured as a 32-bit up counter with an input frequency of 1MHz, and the overflow comparison value is set to 2^32 with overflow interrupt enabled.
[0043] The system clock has a built-in second counting unit for counting seconds and a microsecond counting unit for counting microseconds. The microsecond counting unit realizes the microsecond timing of the clock system by periodically reading the counter value of the hardware timer. The second count and the microsecond count are represented by 32-bit unsigned number variables respectively.
[0044] The calibration unit includes a GPS module or an 8025t chip, which connects the GPS or 8025t second pulse output pin to the highest priority interrupt pin of the main control chip. The GPS module or 8025t chip has a built-in execution program that implements the crystal oscillator frequency correction, count assignment and / or synchronous counting described in this application.
[0045] The system clock is connected to the hardware timer signal, and both the system clock and the hardware timer are connected to the calibration unit signal. Figure 1 It is understood that the GPS module or 8025t chip is connected to the counter signals of the second counting unit, the microsecond counting unit, and the hardware timer, respectively. The connection between the GPS module and the hardware timer counter is bidirectional. The microsecond counting unit is connected to the counter signal of the hardware timer.
[0046] A high-precision clock system is built based on dual 32-bit variables. A hardware timer provides a microsecond-level counting reference, and an external GPS / 8025T second pulse triggers the highest-priority interrupt. The crystal oscillator frequency is dynamically calibrated by continuously comparing the counter difference D between adjacent interrupts. A critical section operation is periodically performed: the quotient of the current count value divided by D is added to the second count, and the remainder is assigned to the hardware counter to prevent overflow. The system updates the second / microsecond variables using real-time calculation of the current count value and implements an anomaly alarm through an overflow interrupt monitoring mechanism, forming a closed-loop calibration system.
[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A calibration method for a clock system based on a feeder terminal, characterized in that, include: Enable the hardware timer of the main control chip, configure the up counter, set the overflow comparison value of the counter to the power of 2 and enable the overflow interrupt, where n is the number of bits of the counter; Crystal oscillator frequency correction: Enable the second pulse output function of GPS or 8025t, connect the second pulse output pin of GPS or 8025t to the highest priority interrupt pin of the main control chip, enable the interrupt function of this pin, record the value of the counter register of the hardware timer each time, and dynamically correct the crystal oscillator frequency by calculating the convergence value of the counter difference D between adjacent second pulse interrupts. Counting assignment: Obtain the value of the hardware timer's counter register with a period of T seconds, divide this register value by D, add the integer part to the system clock's second count value, take the remainder of this value with respect to D, and reassign the remainder part to the hardware timer's counter register, executing a period of T less than 2 to the power of n clock frequencies.
2. The calibration method for a clock system based on a feeder terminal according to claim 1, characterized in that, In the counting assignment, the value of the counter register at the time of the current interrupt is compared with the value of the hardware timer counter register at the time of the previous interrupt. If the difference D converges to the value N in M consecutive interrupts, then D is considered to be the oscillation frequency of the internal or external crystal oscillator per second. The value of M ranges from 1 to 60, and the value of N depends on the accuracy or clock frequency of different GPS or 8025t.
3. The calibration method for a clock system based on a feeder terminal according to claim 2, characterized in that, In the counting assignment, the D value is updated every T seconds, and the latest D value is used for each rounding and modulo operation.
4. The calibration method for a clock system based on a feeder terminal according to claim 1, characterized in that, Also includes: Synchronous counting: When the main control program uses the system clock, it re-acquires the register value of the counter, divides this register value by D, adds the integer part to the second count value of the system clock, takes the remainder of this value with respect to D, and assigns the remainder to the microsecond count variable.
5. The calibration method for a clock system based on a feeder terminal according to any one of claims 1-4, characterized in that, n is 32, and T is less than 2^32 clock frequencies.
6. The calibration method for a clock system based on a feeder terminal according to claim 5, characterized in that, The hardware timer's counter register value increments by 1 every 1Hz. Therefore, the counter overflows after 2^32 clock cycles, generating a timer overflow interrupt, and the timer's counter restarts counting from 0.
7. The calibration method for a clock system based on a feeder terminal according to claim 1, characterized in that, Add a flag alarm function for abnormal overflow of the clock system to the timer overflow interrupt, so as to monitor and prompt abnormalities of the clock system.
8. A clock system based on a feeder terminal, characterized in that, include: Hardware timer; The system clock has a built-in second counting unit for counting seconds and a microsecond counting unit for counting microseconds. The microsecond counting unit realizes the microsecond timing of the clock system by periodically reading the counter value of the hardware timer. The calibration unit includes a GPS module or an 8025t chip, which connects the GPS or 8025t second pulse output pin to the highest priority interrupt pin of the main control chip. The GPS module or 8025t chip has a built-in execution program for crystal oscillator frequency correction and counting assignment as described in claim 1. The system clock is connected to the hardware timer signal, and the system clock and hardware timer are respectively connected to the calibration unit signal.
9. The clock system based on a feeder terminal according to claim 8, characterized in that, The GPS module or 8025t chip also has a built-in execution program that implements the synchronous counting as described in claim 4.
10. The clock system based on a feeder terminal according to claim 9, characterized in that, The hardware timer is configured as a 32-bit up counter with an input frequency of 1MHz, and the overflow comparison value is set to 2^32 with overflow interrupt enabled; the second and microsecond counting units use 32-bit unsigned number variables for counting.