An integrated ReLU in-memory computing circuit and computing method
By integrating the in-memory computation circuit of ReLU, the ReLU activation function is processed directly in the array, the result is judged in real time and set to zero when it is negative, which solves the problem of data transfer required for the ReLU activation function in the prior art, and improves the computational efficiency and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2026-05-22
- Publication Date
- 2026-06-19
Smart Images
Figure CN122240058A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and in particular to in-memory computing circuits and methods for integrating ReLU. Background Technology
[0002] With the rapid development of artificial intelligence (AI), machine learning, and edge computing, the demand for large-scale data processing has increased significantly. Various neural network algorithms are increasingly being deployed on edge devices to perform complex tasks such as bioinformatics, speech recognition, and image classification. This places higher demands on the computing power of edge devices. However, most existing data processing platforms are still based on the traditional von Neumann architecture, whose separation of memory and computing units leads to two major problems: the "power wall" problem—frequent data transfers between the processor and memory consume a large amount of energy, forming a significant power bottleneck; and the "memory wall" problem—the improvement in memory performance cannot keep up with the growth in processor performance, resulting in limited system performance.
[0003] Performing neural network tasks requires frequent and extensive data movement, which significantly reduces computational efficiency and increases power consumption, especially for power-constrained edge devices. In-memory computing (CIM) technology offers an effective solution to these problems. Compared to the von Neumann architecture, CIM architecture minimizes data movement between memory and computing units, thereby significantly improving system performance and energy efficiency. Recent research on CIM based on SRAM, eDRAM, and novel non-volatile memories (NVMs) such as RRAM, MRAM, and FeFET has demonstrated the enormous potential of this technology.
[0004] Currently, most research on integrating activation functions in CIM focuses on Analog In-Memory Computation (ACIM). For example, ACIM architectures integrating ReLU activation modules can effectively improve energy efficiency, but their functionality is often fixed and limited by the accuracy and power consumption of analog-to-digital converters (ADCs), resulting in low readout accuracy. Furthermore, their ability to extend to other activation functions (such as Sigmoid or Tanh) is limited, making it difficult to meet the needs of complex neural networks. In addition, Digital In-Memory Computation (DCIM) architectures in neural network applications are mainly used to perform multiply-accumulate (MAC) operations between inputs and weights. However, when the accumulated result is applied to an activation function (such as ReLU), the data still needs to be moved off-array for computation, which significantly limits the system's energy efficiency and computational density. Summary of the Invention
[0005] Purpose of the invention: The purpose of this invention is to provide an in-memory computing circuit and method with integrated ReLU, which can directly process the accumulation result within the array, avoid data movement, and improve computing efficiency and energy efficiency.
[0006] Technical solution: The present invention provides an in-memory computing circuit with integrated ReLU, which is applied to a neural network structure. The in-memory computing circuit includes an accumulator circuit and a ReLU circuit.
[0007] The accumulator circuit is used to extend the sign bit of the multiplication-accumulation result to obtain a signed accumulated output signal;
[0008] The ReLU circuit executes both conventional calculation mode and ReLU mode under the control of the function control signal and the sign bit signal; the sign bit signal is the highest bit signal of the accumulated output signal.
[0009] The function control signal is used to control the opening and closing of the ReLU mode. When the ReLU mode is disabled, the ReLU circuit performs the normal calculation mode and directly outputs the accumulated output signal.
[0010] When ReLU mode is enabled and the sign bit signal is 1, the ReLU circuit outputs a full zero signal;
[0011] When ReLU mode is enabled and the sign bit signal is 0, the ReLU circuit directly outputs the accumulated output signal.
[0012] Furthermore, the ReLU circuit includes: a sign bit signal connected to an inverter and input together with a function control signal to an OR gate to obtain a function selection signal; the function selection signal and the accumulated output signal are input together to a NAND gate, and then passed through a register to obtain an inverted output.
[0013] Furthermore, the accumulator circuit includes a first accumulator and a second accumulator;
[0014] The first accumulator latches the accumulation result through the first register and performs the first sign bit extension, and performs shift accumulation through the second register;
[0015] The second accumulator latches the output signal of the first accumulator through the third register and performs a second sign bit extension. It then performs shift accumulation through the fourth register to obtain the accumulated output signal with the sign bit.
[0016] Furthermore, in the first accumulator, a data selector is connected after the first register. The data selector controls the first register to select either the Q port or the QN port for output based on the SIGN signal.
[0017] Furthermore, when ReLU mode is enabled and the sign bit signal is 1, the first to third registers are in a signal hold state.
[0018] Furthermore, it also includes timing control circuitry;
[0019] The timing control circuit generates a first timing control signal and a second timing control signal based on the reset signal, the function control signal and the sign bit signal, and generates a first to a fourth clock signal based on the first timing control signal, the second timing control signal and the master clock signal.
[0020] The first to fourth clock signals are used to control the states of the first to fourth registers, respectively.
[0021] Furthermore, the function control signal is connected to an inverter and then input to the first AND gate together with the sign bit signal; the first reset signal is connected to an inverter and then input to the second AND gate together with the output of the first AND gate to obtain the first timing control signal.
[0022] The second reset signal is connected to the register and the inverter, and then input together with the output of the first AND gate to the third AND gate to obtain the second timing control signal;
[0023] The second timing control signal is delayed by one clock cycle compared to the first timing control signal.
[0024] Furthermore, the master clock signal is connected to an inverter and then input together with the first timing control signal to a NOR gate to obtain the first clock signal;
[0025] The second clock signal is the same as the first clock signal;
[0026] The start signal is connected to the inverter and then input together with the second timing control signal to the NOR gate to obtain the third clock signal;
[0027] The fourth clock signal is the same as the master clock signal;
[0028] The start signal is used to set the data bit width.
[0029] Furthermore, the accumulator circuit also includes an adder tree, which is used to perform addition operations on the results of the previous multiplier to obtain a multiply-accumulate result.
[0030] The present invention provides an in-memory calculation method for ReLU, wherein the result of the operation of the preceding multiplier is input into the in-memory calculation circuit of the integrated ReLU to obtain the ReLU calculation result.
[0031] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) The existing DCIM architecture requires the data to be moved outside the array for calculation when the accumulation result is applied to the activation function ReLU, which limits the energy efficiency and computing density. The present invention directly completes the processing of the accumulation result in the array, avoids data movement, further explores the potential of in-memory computing technology, shortens the calculation time, and improves the calculation efficiency and computing energy efficiency. (2) The present invention uses the sign bit signal to judge the positive and negative of the intermediate accumulation result in real time. When the result is negative, the final output bus is forced to be pulled low to 0. At the same time, the timing control circuit closes the clock input of the two accumulators through the CTRL_LAT0 and CTRL_LAT1 signals to terminate the accumulation process in advance under the condition of meeting the accuracy constraints, avoiding redundant MAC operations. (3) The present invention can realize flexible switching between the conventional calculation mode and the ReLU mode without adding a large amount of additional hardware. Attached Figure Description
[0032] Figure 1 This is a circuit diagram of an accumulator according to an embodiment of the present invention.
[0033] Figure 2 This is a timing control circuit diagram according to an embodiment of the present invention.
[0034] Figure 3 This is a ReLU circuit diagram according to an embodiment of the present invention.
[0035] Figure 4 This is a timing diagram of 4-bit serial computation in ReLU mode according to an embodiment of the present invention. Detailed Implementation
[0036] The integrated ReLU in-memory computation circuit of this invention is based on a digital in-memory computation (DCIM) architecture and is applied in neural networks to process the MAC operation results of multiplier and adder trees to complete ReLU nonlinear computation. The technical solution of this invention will be further described below with reference to the accompanying drawings.
[0037] The in-memory calculation circuit with integrated ReLU described in this invention includes an accumulator circuit, a timing control circuit, and a ReLU circuit.
[0038] like Figure 1 As shown, the accumulator circuit includes an adder tree and a first accumulator (such as...). Figure 1 (Part A circled in red in the image) and the second accumulator (such as...) Figure 2The blue box circles section B. The result of the previous multiplication is added through an adder tree to obtain the multiply-accumulated result. The multiply-accumulated result undergoes a first sign-bit extension using the first accumulator, and then a second sign-bit extension using the second accumulator, resulting in a signed accumulated output signal. The bit width of the previous multiplication result and the output bit width of the multiplier circuit can be adjusted according to actual conditions. In this embodiment, the multiplication result is 128 bits, and the output of the accumulator circuit is 23 bits. The following section combines... Figure 1 Please provide a detailed explanation.
[0039] Specifically, COUT_0~COUT_127 are the results of the previous multiplication calculation. COUT_0~COUT_127 are added by the adder tree to obtain an 8-bit multiplication accumulation result PSUM<7:0>. PSUM<7:0> is extended by the first accumulator to obtain the output signal SUM<15:0>. Then, the second accumulator is used to extend the sign bit for the second time to obtain the accumulated output signal SOUT<22:0> with the sign bit.
[0040] PSUM<7:0> is input to the first register of the first accumulator. The output of the first register is selected by the data selector. Since the result of multiplication in the neural network may be negative, this invention performs addition and subtraction operations through the data selector. When the data selector control signal (SIGN signal) is 0, the Q signal is selected for output, and when the SIGN signal is 1, the QN signal is selected for output, thus realizing the sign bit judgment function. The output of the data selector is extended with a sign bit, and the second register is used to perform shift accumulation to obtain the first sign bit extension result SUM<15:0>.
[0041] The input SUM<15:0> is fed into the third register of the second accumulator, then sign-bit extension is performed. The fourth register is used for shift accumulation to obtain the first sign-bit extended result SOUT<22:0>. The second, third, and fourth registers are all selected for Q-port output. The most significant bit SOUT of the second accumulator output signal is... <22> As the sign bit of the calculation result, when the sign bit signal SOUT... <22> When the value is logic "0", it indicates that the accumulator output SOUT<22:0> is a non-negative number (positive or zero). When the sign bit signal SOUT... <22> When the value is logic "1", it indicates that the accumulator output SOUT<22:0> is negative.
[0042] like Figure 2As shown, the timing control circuit determines the timing based on the input function control signal PREC and the most significant bit SOUT. <22> The first reset signal RESET0, the second reset signal RESET1, the start signal START0, and the master clock signal CK are used to generate the first to fourth clock signals CK1~CK4 and the first to fourth inverted clock signals CK1N-CK4N. The function control signal PREC is used to enable or disable ReLU operation. The CK1-CK4 and CK1N-CK4N signals are used to control the state of the first to fourth registers in the accumulator circuit. The START0 signal is used to set the bit width of the calculation data (such as 4bit×4bit or 8bit×8bit). In this embodiment, when the CK period is m and the data bit width is n, its period and duty cycle can be calculated according to formulas (1) and (2).
[0043] (1)
[0044] (2)
[0045] Specifically, the dynamic output sensing circuit in the timing control circuit ( Figure 2 The left-side circuitry includes: the function control signal PREC connected to the inverter and the sign bit signal SOUT. <22> The first reset signal, after being connected to an inverter, is input together with the output of the first AND gate to the second AND gate, resulting in the first timing control signal CTRL_LAT0. The second reset signal, RESET1, is connected to the sixth register and an inverter, then input together with the output of the first AND gate to the third AND gate, resulting in the second timing control signal CTRL_LAT1. The sixth register selects the Q port output.
[0046] Specifically, the gated clock network in the timing control circuit ( Figure 2 The circuit on the right side includes: a master clock signal CK connected to an inverter and input to a NOR gate along with the first timing control signal CTRL_LAT0 to obtain the first clock signal CK1; a second clock signal CK2 is the same as the first clock signal CK1, and the master clock signal CK is connected to an inverter and input to a NOR gate along with the first timing control signal CTRL_LAT0 to obtain the second clock signal CK2; a start signal START0 connected to an inverter and input to a NOR gate along with the second timing control signal CTRL_LAT1 to obtain the third clock signal CK3; and a fourth clock signal CK4 is the same as the master clock signal, and the master clock signal CK is connected to two inverters to obtain the fourth clock signal CK4. CK1~CK4 are connected to inverters respectively to obtain CK1N~CK4N.
[0047] The timing control logic is explained below:
[0048] (1) When the PREC signal is “1”, the ReLU function is disabled. At this time, the CTRL_LAT0 and CTRL_LAT1 signals are always “0”. The CK1-CK4 and CKN1-CKN4 signals are determined by the clock signal CK and the start signal START0.
[0049] (2) When the PREC signal is “0”, the ReLU function is enabled. In this mode, the reset signals RESET0 and RESET1 need to be set to reset the CTRL_LAT0 and CTRL_LAT1 signals to “0” when performing the next multi-bit calculation. Their respective periods and duty cycles can be set according to the actual calculation requirements. In this embodiment, when the CK period is m and the data bit width is n:
[0050] (3)
[0051] (4)
[0052] (5)
[0053] (6)
[0054] When the sign bit signal SOUT of the second accumulator outputs... <22> When the detection value is "0", the current calculation result is determined to be non-negative, CTRL_LAT0 and CTRL_LAT1 are "0", the clock signals CK1-CK4 are output normally, and the accumulator performs the accumulation function normally.
[0055] When the sign bit signal SOUT of the second accumulator outputs... <22> When the detection result is "1", the current calculation result is determined to be negative. According to the definition of the ReLU function, this negative value will eventually be set to zero, so subsequent low-order calculations do not contribute to the final result. The timing control circuit pulls signals CTRL_LAT0 and CTRL_LAT1 high to logic "1". The CTRL_LAT1 signal is delayed by one clock cycle through the sixth register to ensure that the calculation result of the first accumulator can be completely transmitted to the second accumulator. This state directly drives the gated clock network, forcing clock signals CK1, CK2, and CK3 to enter the constant low level state "0", which is equivalent to turning off the clock input of the first and second accumulators. As a result, the first to third registers inside the accumulator circuit are in a signal hold state due to the loss of trigger edge. The first and second accumulators will pause their work until the start of the next calculation cycle, thus effectively blocking the output of negative numbers at the underlying physical structure level.
[0056] like Figure 3As shown, the ReLU circuit includes an inverter, an OR gate, a NAND gate, and a fifth register. The fifth register outputs a signal through its QN port, providing the inverted output. The number of NAND gates is determined by the output bit width of the multiplier circuit; in this embodiment, it includes 23 NAND gates. The sign bit signal is SOUT. <22> After connecting the inverter, the function control signal PREC is input together to the OR gate to obtain the function selection signal. The function selection signal and the accumulator circuit output signal SOUT<22:0> are input together to the NAND gate, and then through the fifth register to obtain the inverted output CIMOUT<22:0>. CIMOUT<22:0> is the final output bus of the in-memory calculation circuit.
[0057] Specifically, the operating logic of the ReLU circuit consists of the function control signal PREC and the sign bit signal SOUT. <22> Joint control can be divided into the following three states:
[0058] 1) ReLU Function Disabled: When the PREC signal is logic "1", the ReLU function is disabled. At this time, the ReLU circuit acts as a pass-through path, directly outputting the original output value SOUT<22:0> of the second accumulator as the final result CIMOUT<22:0> without any correction processing.
[0059] 2) ReLU function enabled and result non-negative: when PREC is logic "0" and SOUT... <22> When the logic value is "0", it indicates that the accumulated result is a non-negative number (positive or zero). In this state, the ReLU circuit logic still allows the original accumulated value to pass through without modification and be used as the final output.
[0060] 3) ReLU function is enabled and the result is negative: when PREC is logic "0" and SOUT is negative. <22> When the value is logic "1", the accumulated result is determined to be negative. At this time, the OR gate output becomes logic "0". This signal is passed to the subsequent 23 NAND gates, which, due to their logical characteristics, will all output logic "1". This all-"1" signal is input to the fifth register, and through its QN inverted output port, it finally drives all of CIMOUT<22:0> to logic "0", thus realizing the setting of negative values to "0".
[0061] Table 1 shows... Figures 1-3 A table of names and graphic symbols for Chinese circuit components.
[0062] Table 1. Reference Table of Circuit Component Names and Graphic Symbols
[0063]
[0064] The timing control and reset process of this invention will be verified through a simulation example below. Figure 4The timing diagram of the in-memory computing circuit of the present invention performing 4-bit serial computing in ReLU function enabled mode is shown.
[0065] When the sign bit SOUT of the second accumulator output... <22> When the detection value is "1", the current calculation result is determined to be negative. The control circuit pulls signals CTRL_LAT0 and CTRL_LAT1 high to logic "1". The CTRL_LAT1 signal needs to be delayed by one clock cycle to ensure that the calculation result of the first accumulator can be completely transmitted to the second accumulator. This state directly drives the gated clock network, forcing clock signals CK1, CK2, and CK3 to enter a constant low level state "0". This causes the internal registers of the accumulator to be in a signal hold state due to the loss of the trigger edge, thus effectively blocking the output of negative numbers at the underlying physical structure.
[0066] In the design of the reset logic, this invention employs differentiated time constants to ensure tight connection of the computational pipeline. The first reset signal, RESET0, resets the CTRL_LAT0 signal to "0" after 16 standard clock cycles. This span precisely corresponds to the basic processing time of a 4-bit multiplication-addition operation, aiming to release clock control to prepare for the next set of data computation tasks. Simultaneously, the second reset signal, RESET1, adopts a delayed strategy, resetting CTRL_LAT1 after 16+4=20 clock cycles. The additional 4 cycles are used to compensate for the hardware delay required for the second accumulator to perform the final shift-accumulation operation. This differentiated reset timing design ensures that when the early termination mechanism is triggered, different circuit modules can exit their current state in an orderly manner according to their data processing stage, avoiding timing conflicts and guaranteeing the integrity of intermediate results, thus enabling the entire "calculation, determination, termination" process to be reliably executed cyclically.
Claims
1. An in-memory computing circuit with integrated ReLU, characterized in that, Applied to neural network structures, the in-memory computing circuit includes an accumulator circuit and a ReLU circuit; The accumulator circuit is used to extend the sign bit of the multiplication-accumulation result to obtain a signed accumulated output signal; The ReLU circuit executes both conventional calculation mode and ReLU mode under the control of the function control signal and the sign bit signal; the sign bit signal is the highest bit signal of the accumulated output signal. The function control signal is used to control the opening and closing of the ReLU mode. When the ReLU mode is disabled, the ReLU circuit performs the normal calculation mode and directly outputs the accumulated output signal. When ReLU mode is enabled and the sign bit signal is 1, the ReLU circuit outputs a full zero signal; When ReLU mode is enabled and the sign bit signal is 0, the ReLU circuit directly outputs the accumulated output signal.
2. The in-memory computing circuit with integrated ReLU according to claim 1, characterized in that, The ReLU circuit includes: a sign bit signal connected to an inverter and input together with a function control signal to an OR gate to obtain a function selection signal; the function selection signal and the accumulated output signal are input together to a NAND gate, and then passed through a register to obtain an inverted output.
3. The in-memory computing circuit with integrated ReLU according to claim 1, characterized in that, The accumulator circuit includes a first accumulator and a second accumulator; The first accumulator latches the accumulation result through the first register and performs the first sign bit extension, and performs shift accumulation through the second register; The second accumulator latches the output signal of the first accumulator through the third register and performs a second sign bit extension. It then performs shift accumulation through the fourth register to obtain the accumulated output signal with the sign bit.
4. The in-memory computing circuit with integrated ReLU according to claim 3, characterized in that, In the first accumulator, a data selector is connected after the first register. The data selector controls the first register to select either the Q port or the QN port for output based on the SIGN signal.
5. The in-memory computing circuit with integrated ReLU according to claim 3, characterized in that, When ReLU mode is enabled and the sign bit signal is 1, the first to third registers are in a signal hold state.
6. The in-memory computing circuit with integrated ReLU according to claim 3, characterized in that, It also includes timing control circuitry; The timing control circuit generates a first timing control signal and a second timing control signal based on the reset signal, the function control signal and the sign bit signal, and generates a first to a fourth clock signal based on the first timing control signal, the second timing control signal and the master clock signal. The first to fourth clock signals are used to control the states of the first to fourth registers, respectively.
7. The in-memory computing circuit with integrated ReLU according to claim 6, characterized in that, The function control signal is connected to the inverter and then input together with the sign bit signal to the first AND gate. The first reset signal is connected to the inverter and then input together with the output of the first AND gate to the second AND gate to obtain the first timing control signal. The second reset signal is connected to the register and the inverter, and then input together with the output of the first AND gate to the third AND gate to obtain the second timing control signal; The second timing control signal is delayed by one clock cycle compared to the first timing control signal.
8. The in-memory computing circuit with integrated ReLU according to claim 6, characterized in that, The master clock signal is connected to an inverter and then input together with the first timing control signal to a NOR gate to obtain the first clock signal; The second clock signal is the same as the first clock signal; The start signal is connected to the inverter and then input together with the second timing control signal to the NOR gate to obtain the third clock signal; The fourth clock signal is the same as the master clock signal; The start signal is used to set the data bit width.
9. The in-memory computing circuit with integrated ReLU according to claim 1, characterized in that, The accumulator circuit also includes an adder tree, which is used to perform addition operations on the results of the previous multiplier to obtain a multiply-accumulate result.
10. A method for in-memory computation of ReLU, characterized in that, The result of the previous multiplier is input into the in-memory calculation circuit of the integrated ReLU as described in any one of claims 1-9 to obtain the ReLU calculation result.