A power-on reset and bandgap reference composite circuit and method with temperature compensation
Patent Information
- Application Number
- CN202610339024.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-19
Smart Images
Figure CN122239913A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design technology, specifically to a temperature-compensated power-on reset and bandgap reference composite circuit and method. Background Technology
[0002] As is well known, electronic devices such as mobile phones, personal computers, digital cameras, and personal entertainment devices all integrate semiconductor integrated circuit chips (ICs). These chips are designed to operate at different power, voltage, and temperature levels. Many electronic devices employ bandgap reference circuits, which provide an accurate and reliable voltage reference and remain stable over a wide temperature range. During the startup and shutdown processes of electronic devices, due to the unpredictability of the power supply voltage during startup and shutdown, IC chips may enter uncertain operating states. Therefore, most IC chips require the power supply to reach the desired operating voltage before starting up to perform normal functions. Simultaneously, since most power supplies cannot immediately provide the required voltage level to the IC circuit, the power supply gradually increases the voltage level over a period of time according to the integrated circuit's load. Therefore, to ensure normal circuit operation, using a POR circuit to participate in chip startup, initializing the chip's internal digital circuits and storage elements to known values when the power supply is turned on until the power supply voltage reaches the effective operating range, is a widely accepted technical solution. When the power supply voltage exceeds the expected trigger voltage or threshold voltage level, the POR circuit detects the power-on state and outputs a reset signal. This reset signal is used to reset the chip to a known operating state. The POR circuit can also detect abnormal power supply states, including undervoltage states where the voltage level drops below the threshold.
[0003] Conventional power-on reset circuits lack temperature compensation. Their output node changes linearly with the increase of MOSFET operating temperature, and the power-on threshold voltage varies significantly with temperature. Furthermore, they cannot accurately detect power-off, and the power-off threshold voltage also changes with temperature. This results in an unstable reset state, and the reset circuit becomes unreliable when there are changes in process, temperature, or voltage rise and fall rates. Summary of the Invention
[0004] To help solve the above-mentioned technical problems, this application provides a power-on reset and bandgap reference composite circuit and method with temperature compensation.
[0005] In a first aspect, this application provides a composite circuit with temperature-compensated power-on reset and bandgap reference, employing the following technical solution: A temperature-compensated power-on reset and bandgap reference composite circuit includes a startup circuit module, a bandgap core circuit module, a signal generation circuit module, and a comparison module. The output of the startup circuit module is connected to the startup node of the bandgap core circuit module; The PTAT current output terminal of the bandgap core circuit module is connected to the input terminal of the signal generation circuit module to provide a PTAT current proportional to the absolute temperature. The feedback node of the bandgap core circuit module is connected to the control terminal of the startup circuit module. The signal generation circuit module includes a first branch and a second branch, and the output nodes of the first branch and the second branch are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparison module; The comparison module includes a comparator and a first NMOS transistor. The non-inverting input and the inverting input of the comparator receive a first reference voltage and a second reference voltage, respectively. The output of the comparator is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the generation node of the first reference voltage, which is used to turn on when the comparator output flips and pull the first reference voltage down by a bandgap voltage value to form a temperature-independent hysteresis in the output signal of the power-on reset circuit.
[0006] The startup circuit module includes a self-biasing circuit, a second NMOS transistor, and a shutdown control unit; The self-biased circuit is composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, and a first resistor and a second resistor connected together, and its output terminal is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the startup node of the bandgap core circuit module, and its source is grounded; The shutdown control unit includes a fourth PMOS transistor and a fourth NMOS transistor. The gate of the fourth PMOS transistor is connected to the feedback node of the bandgap core circuit module. The gate of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor through a resistor network. The drain of the fourth NMOS transistor is connected to the gate of the second NMOS transistor.
[0007] The bandgap core circuit module includes a first current branch and a second current branch. The first current branch is sequentially connected to the fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, the first transistor, and the third resistor; The second current branch is sequentially connected to the seventh PMOS transistor, the eighth PMOS transistor, the sixth NMOS transistor, and the second transistor; The fifth PMOS transistor and the sixth PMOS transistor form the first Cascode current mirror, and the seventh PMOS transistor and the eighth PMOS transistor form the second Cascode current mirror. The first Cascode current mirror and the second Cascode current mirror are mirror images of each other.
[0008] The emitter junction area of the second transistor and the first transistor are in a preset ratio, and the voltage across the third resistor is... This represents the base-emitter voltage difference between the second transistor and the first transistor. The PTAT current Iptat provided by the bandgap core circuit module is determined by the current flowing through the third resistor and satisfies the following relationship: ,in , VT is the thermal voltage, Ic0 and Ic1 are the collector currents of the first transistor and the second transistor, respectively, and Is0 and Is1 are their reverse saturation currents.
[0009] The bandgap core circuit module also includes a negative feedback loop, which includes a ninth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The gate of the ninth PMOS transistor is connected to the drain node of the sixth PMOS transistor; The gate and drain of the seventh NMOS transistor are connected together and connected to the drain of the ninth PMOS transistor. The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, and its source is connected to the base of the first transistor and the second transistor.
[0010] The first branch of the signal generation circuit module is connected in series with a fourth resistor, a third transistor, a fifth resistor, and a fourth transistor. The first reference voltage is drawn from the node between the third transistor and the fifth resistor or from the emitter of the fourth transistor. The second branch is connected in series with a sixth resistor and a fifth transistor, and the second reference voltage is drawn from the emitter of the fifth transistor.
[0011] The first reference voltage is composed of the voltage drop across the fourth and fifth resistors caused by the PTAT current flowing through the first branch, and the base-emitter voltages of the third and fourth transistors, and satisfies the following relationship: In the formula, Vbe4 and Vbe5 are the base-emitter voltages of the third and fourth transistors, respectively.
[0012] The comparison module also includes a Schmitt trigger and an output buffer unit; The input of the Schmitt trigger is connected to the output of the comparator, and its output is connected to the output buffer unit to serve as the power-on reset signal output of the composite circuit.
[0013] Secondly, this application provides a power-on reset method with temperature compensation, employing the following technical solution: A temperature-compensated power-on reset method, applied to the composite circuit described in any one of the first aspects, comprising the following steps: After the power supply is turned on, the startup circuit module provides a startup signal to the startup node of the bandgap core circuit module to assist it in starting from the degenerate point. After the bandgap core circuit module is started, it generates a PTAT current that is proportional to the absolute temperature and provides a feedback signal from the feedback node to the startup circuit module to stop it from working. Based on the PTAT current, a first reference voltage and a second reference voltage are generated in the signal generation circuit module; In the comparison module, the first reference voltage is compared with the second reference voltage; When the power supply voltage rises to the point that the second reference voltage exceeds the first reference voltage, the output of the comparison module flips and controls the first NMOS transistor to turn on, pulling the first reference voltage down by a bandgap voltage value, thereby creating a temperature-independent hysteresis in the output signal and completing the power-on reset.
[0014] Preferably, the hysteresis voltage value is equal to a bandgap reference voltage, which is determined by the difference between the first reference voltage before and after the first NMOS transistor is turned on.
[0015] In summary, the circuit of this application generates PTAT current through a bandgap core circuit, and generates a temperature-independent reference voltage and hysteresis window accordingly, so that the power-on reset threshold remains stable over the entire temperature range. At the same time, it uses internal feedback to automatically shut down the startup circuit after startup to reduce power consumption, and effectively suppresses power supply noise with its inherent hysteresis characteristics, thus providing a highly reliable power-on reset solution. Attached Figure Description
[0016] Figure 1 This is a schematic block diagram of the temperature-compensated power-on reset and bandgap reference composite circuit of this application. Figure 2 This is a schematic diagram of the specific circuit structure of the startup module in this application; Figure 3 This is a schematic diagram of the circuit structure of the bandgap core circuit module of this application; Figure 4 This is a schematic diagram of the circuit structure of the signal generation circuit module of this application; Figure 5 This is a schematic diagram of the first part of the overall circuit structure of this application; Figure 6 This is a schematic diagram of the second part of the overall circuit structure of this application; Figure 7 This is a schematic diagram of the third part of the overall circuit structure of this application. Detailed Implementation
[0017] The present application will be further described below with reference to the accompanying drawings. The principles of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
[0018] The naming conventions for this application are as follows: NMOS transistor (NM14), NMOS transistor (NM11), NMOS transistor (NM9), NMOS transistor (NM10), NMOS transistor (NM1), NMOS transistor (NM0), NMOS transistor (NM2), NMOS transistor (NM4), PMOS transistor (PM11), PMOS transistor (PM12), PMOS transistor (PM13), PMOS transistor (PM10), PMOS transistor (PM1), PMOS transistor (PM5), PMOS transistor (PM0), PMOS transistor (PM6), PMOS transistor (PM2), Resistor (R9), Resistor (R10), Resistor (R0), Resistor (R1), Resistor (R2), Resistor (R3), Transistor (Q1), Transistor (Q0), Transistor (Q4), Transistor (Q5), Transistor (Q6).
[0019] The circuit can be divided into four parts: a startup circuit to help the bandgap reference start, a bandgap core circuit to generate PTAT current, a signal generation circuit to generate a comparator reference signal, and a signal comparison module to generate a POR reset signal.
[0020] like Figure 1 As shown, when the external power supply rises to a certain voltage level, the startup circuit generates a startup signal to help the critical node of the bandgap core circuit get away from the degeneracy point, and after the startup is completed, the bandgap core circuit feeds back a shutdown signal to shut down the startup circuit.
[0021] The specific circuit of the startup module is as follows: Figure 2As shown, PM11, PM12, and PM13 are PMOS transistors, NM9, NM10, and NM11 are NMOS transistors, and R9 and R10 are resistors. The top power node is connected to the source of PMOS transistor PM11, the source of PMOS transistor PM10, one end of resistor R5, and one end of resistor R9. The bottom ground node is connected to the sources of NMOS transistors NM9, NM8, NM10, and NM11, as well as the other ends of resistors R8 and R10. The source of PM11 is connected to the power supply, and its gate and drain are connected to the source of PM12. The gate and drain of PM12 are shorted to connect to the gate of PM13, and the source of PM12 is connected to one end of resistor R10, with the other end of resistor R10 grounded. The source of PM13 is connected to one end of resistor R9, and its drain is connected to the drain and gate of NM9, with the source of NM9 grounded. PM10's gate is connected to Vbp2, and its drain is grounded through resistors R6, R7, and R8, connecting to the drain and gate of NM6, and then to the gate of NM10. NM6's source is connected to NM7's drain and gate. NM7's source is connected to the node between R7 and R8, and then to the drain of NM8. NM8's source is grounded, and its gate is connected to the gates of NM9 and NM11, and the drain of NM10. NM10's source is grounded. NM5's drain is connected to one end of resistor R5, and the other end of R5 is connected to the power supply. NM5's gate is connected to Vbn2, and its source is connected to the drain of NM11 and Vbp1. NM11's source is grounded. The circuit diagram in this application does not involve complex circuit components. The connections between components can be directly and unambiguously derived from the accompanying drawings. The above description of the connections is illustrative and will not be repeated hereafter.
[0022] PM11, PM12, PM13, NM9, and resistors R9 and R10 together form a self-biased circuit. Assuming that the threshold voltage Vth of the MOSFETs are the same, when the power supply voltage reaches about twice Vgs, NM9 outputs a voltage of about 1V. When the threshold voltage is reached, NM11 turns on and pulls the node voltage Vbp1 down to ground. After the bandgap core circuit is started, the gate of PM10 receives a voltage Vbp2 to turn it on. After PM10 turns on, due to the clamping effect of NM6, NM7, NM8 and resistors R6, R7, and R8, the gate voltage of NM10 will be pulled up. As a switch, the turn-on of NM10 will pull down the gate voltage of NM11, thus completing the turn-off after startup.
[0023] Bandgap core circuit module such as Figure 3As shown, PM1, PM5, NM1, Q1, and R0 constitute the first current branch of the bandgap core circuit; PM0, PM6, NM0, and Q0 constitute the second current branch; PM2, PM3, PM4, NM2, and Q2 constitute the third current branch; PM7, NM3, and Q3 constitute the fourth current branch; PM8, PM9, and NM13 constitute the fifth current branch; R4, NM4, and NM12 constitute the sixth current branch; and R5, NM5, and NM11 constitute the seventh current branch. The PMOS transistors PM0 and PM6, PM1 and PM5, PM2 and PM3, and PM8 and PM9 in the first, second, third, and fifth current branches form cascode current mirrors, while PM4 is used as a switching transistor, conducting only during power-up (details below). PM7 is a bias transistor, providing voltage bias for the second-layer cascode transistors PM3, PM5, PM6, and PM9, increasing impedance. The NMOS transistors NM0, NM1, NM2, NM3, and NM4 in the first, second, third, and fourth current branches are used to isolate the influence of power supply voltage changes on the collector voltage of the transistors below or the Vds of the MOS transistors, ensuring the accuracy of the current mirror's current replication. Their width-to-length ratio corresponds to the proportional relationship between the current magnitudes of their respective current branches. NM12 and NM13 in the fifth and sixth current branches are current mirrors used to replicate the Iptat current to the sixth current branch, providing bias current to the bases of the transistors in the first, second, third, and fourth current branches and regulating the collector current of the transistors. The seventh current branch is unrelated to the function of the bandgap core circuit and will not be discussed further here.
[0024] The bandgap core circuit has two important branches: the first and second current branches, which determine the output Iptat current, which is proportional to the absolute temperature. In this application, the upper PMOS portions of the first and second current branches are current mirrors. Assuming the width-to-length ratio of PM0 / PM1 is 16 / 4, and the width-to-length ratio of PM6 / PM5 is also 16 / 4, this means that the collector current Ic0 of transistor Q0 in the second and first current branches is four times the collector current Ic1 of transistor Q1. For transistor Q1 in the first current branch, the current in this branch is determined by the voltage drop across resistor R0, according to the transistor base-emitter formula: (1).
[0025] In the formula, Vbe is the base-emitter voltage of the transistor; VT is the thermal voltage, which is positively correlated with temperature, and the higher the temperature, the larger the value. At room temperature (27℃), VT is about 26mV; Ic is the collector current; Is is the reverse saturation current, which is positively correlated with the emitter junction area.
[0026] For the base-emitter voltage difference of transistors Q0 and Q1, we have: (2).
[0027] From the above equation, it can be seen that the emitter voltage of transistor Q1 in the first current branch is equal to the base-emitter voltage difference between Q1 and Q2. Substituting equation (1) into equation (2): (3).
[0028] Due to the cascode current mirror above, the collector current Ic0 flowing into transistor Q0 is four times that of Ic1. Here, we assume that the ratio of the emitter junction area of Q0 to Q1 is 1 / 2 (in practice, any ratio of 1 / 2, 1 / 4, or 1 / 8 is acceptable). Then, Is1 = 2Is0. Substituting this into equation (3), we can obtain: (4).
[0029] Therefore, the emitter voltage of Q1, or the voltage drop across R0, is determined. Ignoring the tiny base current of the transistor, we can obtain the emitter current of transistor Q1, which is the Iptat current flowing through the first current branch: (5).
[0030] It is important to note that there is a high-resistance node located at the drain of PM5 in the first current branch. This is because there is a current source composed of PM1 and PM5 above it, and a transistor below it that is only affected by temperature and can also be regarded as a current source. Therefore, the impedance at this point is very high. If there is even a slight current mismatch, this potential will either be pulled close to the power supply voltage or pulled low to close to ground. To solve this problem, this application introduces a negative feedback loop, namely PM2——NM2——NM4——Q0, Q1——PM0——PM1——PM2. The principle of this negative feedback path will be introduced below.
[0031] To better understand how this negative feedback works, this application assumes that this potential—that is, the leakage potential of PM5—is suddenly pulled down to near ground potential for some reason. This application previously assumed that there was no negative feedback path. Now, what happens when negative feedback is introduced? In this application, the gate terminal of PM2 is connected to the drain terminal of PM5. Now, this potential is pulled very low, meaning the gate voltage of the PMOS transistor PM2 is sharply pulled down. This causes the current of PM2 to increase. The NMOS transistor NM2 connected to the diode will fully respond to this current, and the Vgs of NM2 will become very large. This will raise the gate voltage of the N-layer transistor biased by NM2. Now, focus on NM4. When the gate voltage of NM4 rises, its source voltage will also rise. Because current changes take time, in order to maintain a constant current, the source voltage of NM4 rises. This will also raise the base voltage of Q0, Q1, Q2, and Q3. According to the current formula of the transistor amplification region, the relationship between the transistor Vbe and the collector current Ic is exponentially positively correlated. If Vbe increases slightly, the transistor current will increase even more. Because of R0, the Vbe of Q1 will always be less than that of Q0, which is determined by the circuit structure. Therefore, the current flowing through Q0 will increase more, and no matter how much the current of Q1 increases, it will not be greater than that of Q0. Here, due to the same base voltage change, the collector current of Q0 is greater than that of Q1. This will increase the current in the second current branch more. The gate of PM0 connected to the diode decreases, and the current mirror PM1 replicates the current of PM0, which is proportional to it, thus increasing the current of PM1. This injects more current into the node of the drain of PM5, raising its voltage. As a result, the gate voltage of PM2 increases until the gate voltage of PM2 equals the gate voltage of PM0, reaching circuit balance.
[0032] Signal generation circuit such as Figure 4 As shown, PM14, PM15, and PM16 act as PMOS current mirrors, replicating the Iptat current generated by the bandgap core circuit. NM15 and NM16 act as NMOS current mirrors, replicating the current flowing through PM15 into the branch containing NM16. The emitter junction areas of transistors Q4, Q5, and Q6 are the same as Q0, and the resistor types and values of resistors R1, R2, and R3 are the same as R0. The current flowing through R1, Q4, R2, and Q5 generates a temperature-independent voltage, which serves as the non-inverting input signal of comparator I0. This voltage is Vin+. (6).
[0033] In the formula, Iptat is the current proportional to absolute temperature, with a positive temperature coefficient VT; Vbe is a parameter with negative temperature characteristics. By adjusting the resistance value, a bandgap voltage that does not change with temperature, approximately 2.3V, can be obtained. Since the two transistors Q4 and Q5 carry the same current, their Vbe values are equal, and the resistances R1 and R2 are the same. Therefore: (7).
[0034] Assuming PM14 and PM15 have the same dimensions, and NM15 and NM16 also have the same dimensions, then due to the presence of the current mirror, the current flowing through these three branches is exactly the same. Therefore, the voltage drop across transistor Q6 and resistor R3 is equal to half of Vin+, which serves as the inverting input Vin- of the comparator. (8).
[0035] I0 is a comparator of arbitrary structure. Since many comparators can achieve similar effects, they will not be described in detail here. I1 is a Schmitt trigger, mainly used to shape the output waveform. PM17, NM17, PM18, and NM18 together form a buffer to provide load capacity. R11 is a large resistor that provides a weak pull-down, also for output shaping, pulling some relatively low but not zero voltages to ground to make the output cleaner.
[0036] This application also proposes a temperature-compensated power-on reset method, applied to the aforementioned temperature-compensated power-on reset and bandgap reference composite circuit, which specifically includes: Power-on phase: When the power supply VCC is powered on, the internal nodes of the circuit are not stable at this time. The voltage at the inverting input of the comparator is lower than the voltage at the non-inverting input of the comparator. The comparator outputs a high level. The output voltage rises with the power supply. After passing through the Schmitt trigger, the switching transistor NM14 is turned off.
[0037] As the power supply continues to operate, once the bandgap core circuit generates an Iptat current, the voltage at the non-inverting input no longer changes with the power supply VCC, while the voltage at the inverting input of the comparator continues to rise with the power supply. When the voltage at the inverting input exceeds the voltage at the non-inverting input, the comparator output flips, at which point the switching transistor NM14 turns on, pulling the voltage at the non-inverting input low. That is, around 1.2V. At this point, because the voltage at the non-inverting input decreases, the comparator output will remain in the flipping state, forming positive feedback.
[0038] Power-down phase: When the power supply VCC voltage begins to decrease, the voltage at the non-inverting input of the comparator is pulled down by half due to the conduction of switch NM14 in the previous phase. At this time, the power supply VCC voltage needs to drop even lower than before to make the voltage at the inverting input lower than the voltage at the non-inverting input, thus creating hysteresis. This hysteresis can prevent the POR circuit from becoming unstable due to power supply voltage fluctuations. The hysteresis range is Vin+ minus Vin-, which is exactly equal to a bandgap voltage. Furthermore, this hysteresis voltage is independent of temperature.
[0039] Overall physical process such as Figures 5 to 7 As shown ( Figure 5 , Figure 6 and Figure 7 The connection between the three parts can be based on Figures 2 to 4 (The connection relationships of nodes such as Vbp1 are directly obtained and will not be elaborated here): When the power supply is turned on and the VCC voltage reaches about twice the threshold voltage, the self-bias circuit first generates a voltage of about 1V to provide to NM11. After reaching the threshold voltage of NM11, NM11 turns on and pulls down the voltage of node Vbp1, which is connected to the gate terminal of the first layer cascode current mirror and the start-up transistor PM4. The gate-source voltages of PM2 and PM4 in the third current branch will increase with the rise of VCC until the turn-on condition is met. After these two P transistors turn on, the gate terminal voltage of NM2 connected to the diode is raised, and the NMOS transistors in the NM0~NM5 layer are turned on. When NM4 is turned on, the base voltage of transistors Q0~Q3 is raised and quickly enters amplification. In the saturation region, both the transistor and the N-transistor in the bandgap core circuit are activated. PM7, located in the fourth current branch, thus gains a path to ground. The gate voltage Vbp2 of PM7 is pulled low, and the cascode current mirror of the bandgap core circuit is biased. After entering the saturation region, since the gate-source voltage of PM3 is much greater than that of PM4, almost all the current flows through PM3. Therefore, the activation transistor PM4 is turned off. At this step, the bandgap core circuit is activated. After activation, the PTAT current generated by the bandgap core circuit is copied to PM10. After PM10 is turned on, it raises the gate voltage of the switching transistor NM10. Since the switching transistor is connected to the gate of NM11 and ground, after NM10 is turned on, it pulls down the gate voltage of NM11, and NM11 is turned off. Thus, the circuit activation is complete.
[0040] When the bandgap core circuit generates a PTAT current proportional to the absolute temperature, the signal generation circuit also starts. The voltage at the non-inverting input of the comparator is equal to twice the bandgap voltage, which is greater than the voltage at the inverting input. The comparator outputs a high level, and the switch NM14 is turned off. As the power supply voltage rises, the voltage at the non-inverting input remains constant, while the voltage at the inverting input rises with the power supply voltage. When the voltage at the inverting input is greater than the voltage at the non-inverting input, the comparator flips, the switch NM14 turns on, and pulls the voltage at the non-inverting input down by one bandgap voltage. The comparator state remains unchanged thereafter until the power supply voltage drops. When the power supply voltage drops, because the NM14 switch has been continuously on since power-on, the voltage at the non-inverting input is lower than before power-on. Therefore, the power supply voltage needs to drop to a level lower than before for the comparator to flip again, thus creating hysteresis.
[0041] The technical scope of this application is not limited to the contents of the above specification. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this application, and all such modifications and variations should fall within the scope of this application.
Claims
1. A composite circuit having a temperature-compensated power-on reset and bandgap reference, characterized by, It includes a startup circuit module, a bandgap core circuit module, a signal generation circuit module, and a comparison module: The output of the startup circuit module is connected to the startup node of the bandgap core circuit module; The PTAT current output terminal of the bandgap core circuit module is connected to the input terminal of the signal generation circuit module to provide a PTAT current proportional to the absolute temperature. The feedback node of the bandgap core circuit module is connected to the control terminal of the startup circuit module. The signal generation circuit module includes a first branch and a second branch, and the output nodes of the first branch and the second branch are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparison module; The comparison module includes a comparator and a first NMOS transistor. The non-inverting input and the inverting input of the comparator receive a first reference voltage and a second reference voltage, respectively. The output of the comparator is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the generation node of the first reference voltage, which is used to turn on when the comparator output flips and pull the first reference voltage down by a bandgap voltage value to form a temperature-independent hysteresis in the output signal of the power-on reset circuit.
2. The composite circuit of claim 1, wherein The startup circuit module includes a self-biasing circuit, a second NMOS transistor, and a shutdown control unit; The self-biased circuit is composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, and a first resistor and a second resistor connected together, and its output terminal is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the startup node of the bandgap core circuit module, and its source is grounded; The shutdown control unit includes a fourth PMOS transistor and a fourth NMOS transistor. The gate of the fourth PMOS transistor is connected to the feedback node of the bandgap core circuit module. The gate of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor through a resistor network. The drain of the fourth NMOS transistor is connected to the gate of the second NMOS transistor.
3. The composite circuit of claim 1, wherein The bandgap core circuit module includes a first current branch and a second current branch. The first current branch is sequentially connected to the fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, the first transistor, and the third resistor; The second current branch is sequentially connected to the seventh PMOS transistor, the eighth PMOS transistor, the sixth NMOS transistor, and the second transistor; The fifth PMOS transistor and the sixth PMOS transistor form the first Cascode current mirror, and the seventh PMOS transistor and the eighth PMOS transistor form the second Cascode current mirror. The first Cascode current mirror and the second Cascode current mirror are mirror images of each other.
4. The composite circuit according to claim 3, characterized in that, The second triode is in a preset proportion to the emitting junction area of the first triode, and the voltage across the third resistor is the base-emitter voltage difference of the second triode and the first triode; The PTAT current Iptat provided by the bandgap core circuit module is determined by the current flowing through the third resistor and satisfies the following relationship: ,in , VT is the thermal voltage, Ic0 and Ic1 are the collector currents of the first transistor and the second transistor, respectively, and Is0 and Is1 are their reverse saturation currents.
5. The composite circuit according to claim 3, characterized in that, The bandgap core circuit module also includes a negative feedback loop, which includes a ninth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The gate of the ninth PMOS transistor is connected to the drain node of the sixth PMOS transistor; The gate and drain of the seventh NMOS transistor are connected together and connected to the drain of the ninth PMOS transistor. The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, and its source is connected to the base of the first transistor and the second transistor.
6. The composite circuit according to claim 1, characterized in that, The first branch of the signal generation circuit module is connected in series with a fourth resistor, a third transistor, a fifth resistor, and a fourth transistor. The first reference voltage is drawn from the node between the third transistor and the fifth resistor or from the emitter of the fourth transistor. The second branch is connected in series with a sixth resistor and a fifth transistor, and the second reference voltage is drawn from the emitter of the fifth transistor.
7. The composite circuit according to claim 6, characterized in that, The first reference voltage is composed of the voltage drop across the fourth and fifth resistors caused by the PTAT current flowing through the first branch, and the base-emitter voltages of the third and fourth transistors, and satisfies the following relationship: In the formula, Vbe4 and Vbe5 are the base-emitter voltages of the third and fourth transistors, respectively.
8. The composite circuit according to claim 1, characterized in that, The comparison module also includes a Schmitt trigger and an output buffer unit; The input of the Schmitt trigger is connected to the output of the comparator, and its output is connected to the output buffer unit to serve as the power-on reset signal output of the composite circuit.
9. A power-on reset method with temperature compensation, applied to the composite circuit according to any one of claims 1 to 8, characterized in that, Includes the following steps: After the power supply is turned on, the startup circuit module provides a startup signal to the startup node of the bandgap core circuit module to assist it in starting from the degenerate point. After the bandgap core circuit module is started, it generates a PTAT current that is proportional to the absolute temperature and provides a feedback signal from the feedback node to the startup circuit module to stop it from working. Based on the PTAT current, a first reference voltage and a second reference voltage are generated in the signal generation circuit module; In the comparison module, the first reference voltage is compared with the second reference voltage; When the power supply voltage rises to the point that the second reference voltage exceeds the first reference voltage, the output of the comparison module flips and controls the first NMOS transistor to turn on, pulling the first reference voltage down by a bandgap voltage value, thereby creating a temperature-independent hysteresis in the output signal and completing the power-on reset.
10. The method according to claim 9, characterized in that, The hysteresis voltage value is equal to a bandgap reference voltage, which is determined by the difference between the first reference voltage before and after the first NMOS transistor is turned on.