High-voltage high-speed push-pull comparator circuit and use thereof

Abstract

Disclosed in the present invention are a high-voltage high-speed push-pull comparator circuit and a use thereof. An input protection circuit is connected to external input signals and processes the signals, and is then connected to a differential pre-amplifier; the pre-amplifier performs preliminary amplification on the input signals and converts high-voltage signals into low-voltage signals, and is connected to a low-voltage amplifier; the low-voltage amplifier performs second amplification on the input signals to generate two output signals; a current feedback circuit is connected to a second output signal of the low-voltage operational amplifier and processes the signal to generate two signals, and separately performs feedback control on an NMOS control circuit and a PMOS control circuit; and an LDO generates LVDD and HGND potentials, the HGND potential is connected to the PMOS control circuit, and the LVDD potential is connected to the low-voltage operational amplifier and the NMOS control circuit. The PMOS and NMOS control circuits process output signals of a two-stage operational amplifier circuit into digital logic signals, and the digital signals are processed by an output logic control circuit, so as to control the turn-on and turn-off of PMOS and NMOS push-pull transistors.

Description

A high-voltage, high-speed push-pull comparator circuit and its application Technical Field

[0001] This invention relates to a comparator circuit, specifically a high-voltage, high-speed push-pull comparator circuit and its applications, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] High-voltage comparators have a wide operating voltage range and voltage comparison range, and are widely used in power management, analog-to-digital conversion, and signal conditioning. They also have important applications in industrial control, automotive electronics, and communications.

[0003] High-voltage comparators function as low-voltage comparators, meaning they compare the voltage values ​​at two input ports and output the correct high / low level logic signal. In addition, high-voltage comparators have a wider operating voltage range, with the maximum operating voltage depending on the device's allowable voltage rating. They also have a wider input common-mode range and differential-mode signal comparison range, primarily depending on the power supply voltage.

[0004] However, traditional high-voltage comparators still have some drawbacks. Traditional high-voltage comparators primarily use an open-drain output structure, as shown in Figure 1. This requires an external pull-up resistor. Since the open-drain output can only drive the load in a low-level state, the external pull-up resistor charges the output port to provide a high level in the high-level state, which slows down the rise and fall edge response times of the signal. Figure 2 shows the output response of the high-voltage open-drain comparator under appropriate pull-up resistor selection. When the output is high, the output DENMOS transistor is off, and the power supply charges the output port through the pull-up resistor. As the output potential rises, the charging speed slows down, and the rise slope of the output potential decreases. When the output is low, the DENMOS transistor is on, and the gate level is fixed. Since the power supply charges the DENMOS through the pull-up resistor, the current through the DENMOS increases as the output potential decreases, causing the fall slope to slow down. During output switching, because the output stage DENMOS is always on when the output is low, it consumes a large current in high-frequency applications. The specific value of the current consumed depends on the size of the pull-up resistor, thus reducing power efficiency.

[0005] In addition, traditional high-voltage comparators generally use a single-stage operational amplifier structure with high-voltage devices, i.e., a single-stage high-voltage operational amplifier plus control logic. Under the condition of achieving the same gain, the response bandwidth of a single-stage operational amplifier is smaller than that of a multi-stage operational amplifier, and the response speed is slower; moreover, high-voltage devices are larger in area than low-voltage devices, and parasitic effects are more obvious, making it more difficult to achieve high speed under the same power consumption conditions. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-voltage, high-speed push-pull comparator circuit and its application, which can respond quickly to changes in the input signal, realize push-pull output, and improve the speed and power consumption utilization of the high-voltage comparator.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] A high-voltage, high-speed push-pull comparator circuit includes: an input protection circuit, a first-stage differential preamplifier circuit, a second-stage low-voltage amplifier circuit, a current feedback circuit, a low-dropout linear regulator, a PMOS control circuit, an NMOS control circuit, and an output logic control circuit.

[0009] The input protection circuit connects to two external input signals. After performing input protection processing on the external input signals, it obtains two output signals and sends them to the first-stage differential preamplifier circuit. The first-stage differential preamplifier circuit performs preliminary amplification on the input signals after input protection processing, and at the same time converts the pre-amplified signals from high voltage to low voltage. The converted low-voltage signals are then sent to the second-stage low-voltage amplifier circuit. The second-stage low-voltage amplifier circuit performs a second amplification on the low-voltage signals to obtain two output signals. The first output signal is connected to both the PMOS control circuit and the NMOS control circuit, and the second output signal is connected to the current feedback circuit.

[0010] The current feedback circuit processes the second output signal and generates two feedback control signals, CFB_P and CFB_N. CFB_P is sent to the PMOS control circuit for feedback control, and CFB_N is sent to the NMOS control circuit for feedback control. The low-dropout linear regulator generates a low-voltage supply potential LVDD with drive capability and higher than ground (GND), which is provided to the second-stage low-voltage amplifier circuit and the NMOS control circuit. The low-dropout linear regulator also generates a high-voltage supply potential H with drive capability and lower than the supply voltage VDD. GND is connected to the PMOS control circuit; the power supply voltage VDD is connected to the PMOS control circuit, and the ground potential GND is connected to the NMOS control circuit; the PMOS control circuit processes the first output signal to obtain the PMOS push-pull output control signal and sends it to the output logic control circuit; the NMOS control circuit processes the first output signal to obtain the NMOS push-pull output control signal and sends it to the output logic control circuit; the output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, thereby controlling the conduction and turn-off of the PMOS and NMOS push-pull transistors.

[0011] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0012] 1. This invention uses a two-stage operational amplifier circuit to amplify the input overdrive voltage, including a first-stage high-voltage differential pre-amplifier circuit and a second-stage low-voltage amplifier circuit. Compared with traditional single-stage high-voltage operational amplifiers, the two-stage operational amplifiers have a larger bandwidth and faster speed.

[0013] 2. In this invention, the first output terminal of the second-stage low-voltage amplifier circuit simultaneously controls the on and off states of MN10 and MN11. The current feedback circuit controlled by the second output terminal ensures that the current mirrors of the PMOS and NMOS control circuits have the same path length, making the output logic response times of the PMOS and NMOS control circuits identical. This avoids the formation of a current path from power supply to ground during output logic inversion caused by asynchronous gate potential responses of the push-pull output PMOS and NMOS transistors, which increases the dynamic power consumption of the push-pull comparator.

[0014] 3. The second-stage low-voltage amplifier circuit of this invention adopts a low-voltage structure. Compared with traditional DEMOS devices, the low-voltage device has a smaller size, smaller parasitic capacitance, and higher characteristic frequency under the same gm. It is easier to achieve high-speed amplification effect under the same power consumption, and therefore the response speed is faster.

[0015] 4. This invention uses an LDO to generate HGND and LVDD potentials, separating the operating voltage domains of the control output push-pull transistors PMOS and NMOS. Firstly, separating the logic signal voltage domains allows the logic signal to swing within a small range, improving the speed of the logic signal's switching response and thus increasing the comparator's speed. Secondly, since the output transistor DEMOS uses a thin-gate oxide device, the gate control potential must be below 5V. The small logic level swing ensures that the push-pull output control signal operates within the safe range of the output transistor's gate withstand voltage.

[0016] 5. This invention uses a current feedback circuit to control the PMOS control circuit and the NMOS control circuit. When the first output logic of the second-stage operational amplifier is high or low, the second output logic controls the current mirror current to decrease or increase. Through the current mirror, the current mirror MN12 of the PMOS control circuit and the current mirror MN7 of the NMOS control circuit are reduced or increased, thereby improving the utilization rate of the comparator's internal power consumption under high-speed operating conditions. Attached Figure Description

[0017] Figure 1 shows the structure of a traditional high-voltage open-leak comparator;

[0018] Figure 2 shows the output response of a traditional high-voltage open-leak comparator;

[0019] Figure 3 is a block diagram of the high-voltage high-speed push-pull comparator of the present invention;

[0020] Figure 4 is a circuit diagram of the high-voltage high-speed push-pull comparator of the present invention;

[0021] Figure 5 shows the output response of the high-voltage high-speed push-pull comparator of the present invention. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] As shown in Figure 3, the present invention provides a high-voltage high-speed push-pull comparator, including: an input protection circuit, a first-stage high-voltage differential amplifier circuit, a second-stage low-voltage amplifier circuit, a current feedback current, a low-dropout linear regulator (LDO), a PMOS control circuit, an NMOS control circuit, and an output logic control circuit.

[0024] The input protection circuit connects to the external input signal, processes the signal, and then connects to the first-stage high-voltage differential preamplifier circuit. The preamplifier circuit initially amplifies the input signal and converts the high-voltage signal to low voltage; the output signal is connected to the second-stage low-voltage amplifier circuit. The low-voltage amplifier circuit amplifies the input signal a second time; the first output signal is connected to both DENMOS10 and DENMOS11, and the second output signal is connected to the current feedback module. The sources of DENMOS10 and DENMOS11 are connected to fixed current mirrors, and their drain output signals are connected to the PMOS control circuit and NMOS control circuit, respectively, to convert the low-voltage signal to high voltage. The output signal of the low-voltage operational amplifier is transmitted to the output control terminal. The input terminal of the current feedback circuit is connected to the second output terminal of the low-voltage operational amplifier. After processing, it generates two signals, CFB_N and CFB_P, which provide feedback control to the NMOS control circuit and the PMOS control circuit, respectively. The LDO circuit generates a low-voltage power supply potential LVDD with driving capability, which is higher than the fixed value of GND, and a high-voltage domain low potential HGND, which is lower than the fixed value of VDD. The HGND potential is connected to the PMOS control circuit to provide it with the high-voltage domain power supply potential. LVDD is connected to the third part of the low-voltage operational amplifier and the NMOS control circuit to provide power supply potential to the two modules. The PMOS control circuit and the NMOS control circuit are used to process the output signals of the two-stage operational amplifier circuit into digital logic signals. After the digital signals of the two modules are processed by the output logic control circuit, they reach the high-voltage push-pull output stage, thereby controlling the conduction and turn-off of DEPMOS22 and DENMOS19.

[0025] The high-voltage, high-speed push-pull comparator circuit structure of this invention is shown in Figure 4.

[0026] The input signal is processed by the input protection circuit and arrives at the input terminal of the first-stage differential preamplifier, namely the gates of MP1 and MP2. The drains of MP1 and MP2 are connected to one end of the load resistors R1 and R2, and the source is connected to the current mirror composed of MP19 and DEMOS MP20, forming a differential amplifier circuit. Resistors R1 and R2 are used to adjust the common mode and provide gain impedance. The second-stage low-voltage amplifier consists of MP3, MP4, MN1, MN2, and MP21. MP3 and MP4 are the input pair transistors. The gate of MP3 is connected to one end of resistor R1, and the gate of MP4 is connected to one end of resistor R2. The sources of MP4 and MP3 are connected to the current mirror of MP21. MN1 and MN2 are of the same size and convert the drain output signals of MP3 and MP4 into single-ended signals. The drain of MN2 is the first output signal, which is connected to the gates of DEMOS MN10 and MN11 to control the conduction and turn-off of the two transistors. The gate of MN2 is the second output signal, which is connected to the gates of the current feedback circuit MN15, MN3, and MN4. The current through MN15, MN3, and MN4 is controlled under different states to improve the power consumption utilization of the comparator.

[0027] In the current feedback circuit, the sources of transistors MN3 and MN4 are connected to the drains of transistors MN5 and MN6, respectively, and their drains are connected to the sources of transistors MN8 and MN9, forming a high-voltage common-source common-gate structure. The drains of transistors MN8, MN10, MN9, and MN11 are connected to the self-biased current mirror composed of MP5 and PM8 and the self-biased current mirror composed of MP11 and MP3, respectively. MN15 and MN14 are self-biased current mirrors, and MN16 provides them with variable current. This current is reflected by MN16 and MN18 to control the current mirror transistor MN7 of the NMOS control circuit, and the current mirror also controls the current mirror MP7 of the PMOS control circuit.

[0028] The LDO generates LVDD and HGND potentials which are connected to the HGND and LVDD ports in Figure 4, respectively, becoming the low-voltage power supply for the low-voltage operational amplifier and the NMOS control circuit, and the high-voltage ground potential for the PMOS control circuit.

[0029] In the PMOS control circuit, the gate of MP6 is connected to a self-biased current mirror gate composed of MP5 and MP8 to mirror the current of MP5. The gate of MP7 is connected to a self-biased current mirror gate composed of MP15 and MP17 to mirror the current of MP15. MN12 and MN13 have a 1:1 size ratio. MN12 is connected to the drain of MP9, and the drain of MN13 is connected to the drain of MP10. This is equivalent to comparing the current through MP5 with the current through MP15, and obtaining the logic level in the high-voltage domain at the drain of MN12. The output logic level is connected to the input port of a Schmitt trigger, and the output result is transmitted to the output logic control module.

[0030] The NMOS control circuit structure is the same as the PMOS control circuit. The MP12 transistor mirrors the current generated by the bias current mirrors of MP11 and MP13, and the MN7 transistor mirrors the current generated by the bias current mirrors of MN16 and MN18. This is equivalent to comparing the current through MP15 with the current through MP11. The logic level signal in the low-voltage domain is obtained at the drain of MN6. Then, the logic signal is output to the input of the Schmitt trigger, and the output result is connected to the push-pull output logic control module.

[0031] The outputs of the PMOS and NMOS control circuits are processed by the output logic control circuit to control the gate potentials of DEMOS MP22 and MN19 in two voltage domains respectively, resulting in a high-speed, high-voltage push-pull output.

[0032] The working principle of the high-voltage high-speed comparator of this invention is as follows:

[0033] The input protection circuit limits large differential signals input, keeping the potential at the input port of the first-stage high-voltage differential amplifier within a safe operating range. This prevents the gates of the input pair transistors in the first-stage high-voltage differential amplifier from breaking down when a large differential signal is input.

[0034] The first-stage high-voltage differential amplifier amplifies the input differential signal and simultaneously converts the high-voltage input common-mode signal into a low-voltage common-mode signal, which is I. 19 / 2*R1 (or R2). MP1 and MP2 are the input transistor pair, using DEMOS, and are of the same size; the load resistors R1 and R2 have the same area and resistance value, and MP19 provides the tail current for the first-stage amplifier. The first stage needs to select appropriate tail current values ​​and load resistor values ​​to ensure that the output common-mode signal makes the input transistor pair of the second-stage op-amp operate in the normal saturation region.

[0035] The second-stage op-amp is a typical five-transistor op-amp. Its power supply potential is provided by the LVDD of the LDO, placing it in the low-voltage domain. Simultaneously, the first-stage high-voltage op-amp converts the changing input common-mode voltage signal into a low-voltage domain signal. Therefore, the second-stage op-amp uses low-voltage NMOS and low-voltage PMOS transistors, which, compared to DEMOS transistors, have smaller area, smaller parasitic capacitance, higher characteristic frequency, and are easier to achieve high bandwidth and high speed. The second-stage op-amp amplifies the output of the first-stage fully differential amplifier, ensuring sufficient gain in the comparator amplifier section and improving the comparator's accuracy.

[0036] The input transistors MP3 and MP4 are the same size, and their gates are connected to the input terminals of the first-stage high-voltage differential operational amplifier, forming a two-stage operational amplifier structure. The first output terminal of the second-stage operational amplifier, namely the drain of MN2, controls the gates of DEMOS transistors MN10 and MN11. MN10 and MN11, as switching transistors, need to be set to a smaller size to control the conduction and turn-off of the current mirrors MN5 and MN6, so that the PMOS control module responds simultaneously to the self-biased current mirrors MP5 and MP11.

[0037] When the first output potential of the second-stage op-amp increases, the current mirrors MN5 and MN6 turn on. The two currents simultaneously control the gate potentials of the self-biased current mirrors MP5 and MP11 to decrease, and then, through mirroring, increase the currents of MP6 and MP12. Meanwhile, the second output potential of the second-stage op-amp decreases, reducing the current flowing through MN16, which raises the gate potential of the self-biased current mirror MP15. This ultimately reduces the currents flowing through MN12 and MN7. Comparing the two currents, the drains of MN12 and MN7 become logic high. Conversely, when the second-stage op-amp outputs a low level, the currents mirrored by MP7 and MP12 decrease, while the currents mirrored by MN12 and MN7 increase, resulting in a logic low output. Therefore, it is necessary to properly set the ratios of MP6 and MN12, and MP12 and MN6, to ensure that the output potential flips quickly and correctly.

[0038] When the first output logic of the second stage is low, MN10 and MN11 are turned off, MN3 and MN4 are current mirror transistors, and MN8 and MN9 are common gate transistors. The ratio of MN1 to MN3 / MN4 is M:1, where M is set according to requirements. At this time, MN3 and MN4 mirror the current of MN1, ensuring that there is a certain current in the self-biased current mirrors of MP5 and MP11, preventing the response speed from slowing down when the current mirrors are completely turned off.

[0039] For the current feedback circuit, the second output of the second-stage operational amplifier controls the current change of the MN16 current mirror. This current change is then reflected by the MP15 self-biased current mirror, and finally by the MP16 and MP7 transistors, controlling the current of the PMOS control logic transistor MN12 and the NMOS control logic transistor MN7. This ensures that the signals reaching the PMOS and NMOS control circuits through the current feedback path are synchronized. In practical implementation, the ratio of MP16 to MP7 can be set to 1:1; the ratio of MN16 to MN7 to 1:1; and the ratio of MN12 to MN13 to 1:1. The ratios of MP11 and MP12 can be set to the same as those of MP5 and MP6, and the ratios of MN5 and MN6 can be equal, ensuring that the current response magnitudes of the two modules are the same and the path delays are equal.

[0040] In practical implementation, LDO circuits are required to generate LVDD (less than 5V) above ground potential and HGND (greater than HGND-5V) below power supply voltage. Firstly, for most high-voltage processes, the gate withstand voltage of the high-voltage transistor is 5.5V. During low-voltage comparator processing, the high-voltage output signal is the power supply voltage, and the low-voltage signal is ground potential. However, this can cause gate breakdown of the output transistor in a high-voltage structure. LDOs are needed to separate the voltage domains to protect the output transistor. Secondly, in the design of high-speed comparators, limiting the logic voltage swing can effectively improve the comparator's response speed. Therefore, using HGND and LVDD improves both the speed performance and safety of high-voltage high-speed comparators. In addition, to ensure a fast current mirror response, this invention uses MN3 and MN4 current mirror transistors and MN8 and MN9 common-gate transistors. The ratio of MN1 to MN3 / MN4 is M:1, where M is set according to requirements. The purpose is to ensure that MP5 and MP11 have a certain current when MN10 and MN11 are completely off, preventing a slowdown in response speed during logic flips due to the complete shutdown of the current mirror.

[0041] In the specific implementation method, the PMOS control circuit and the NMOS control circuit use the same type of devices. Specifically, isolated NMOS transistors are used for PMOS control circuits MN12 and MN13, and correspondingly, isolated NMOS transistors are used for NMOS control circuits MN7 and MN16. This ensures that the parasitic behavior of the two paths is the same, and the response delay is synchronized. Schmitt triggers are used in both the PMOS and NMOS control circuits to process the logic levels and prevent oscillations caused by logic disorder.

[0042] Finally, the output logic control circuit processes the synchronous response PMOS push-pull output control signals and NMOS push-pull output control signals. First, it enhances the ability of the logic signals to drive the push-pull output. Second, it delays the push-pull signals to prevent the push-pull NMOS and PMOS from conducting simultaneously, thus avoiding unnecessary dynamic power consumption. The processed signal reaches the gate of the push-pull output transistor, completing the implementation of the high-voltage, high-speed push-pull comparator. The output response of the high-voltage, high-speed push-pull comparator is shown in Figure 5.

[0043] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A high-voltage, high-speed push-pull comparator circuit, characterized in that, include: Input protection circuit, first-stage differential preamplifier circuit, second-stage low-voltage amplifier circuit, current feedback circuit, low-dropout linear regulator, PMOS control circuit, NMOS control circuit, and output logic control circuit. The input protection circuit connects to two external input signals. After performing input protection processing on the external input signals, it obtains two output signals and sends them to the first-stage differential preamplifier circuit. The first-stage differential preamplifier circuit performs preliminary amplification on the input signals after input protection processing, and at the same time converts the pre-amplified signals from high voltage to low voltage. The converted low-voltage signals are then sent to the second-stage low-voltage amplifier circuit. The second-stage low-voltage amplifier circuit performs a second amplification on the low-voltage signals to obtain two output signals. The first output signal is connected to both the PMOS control circuit and the NMOS control circuit, and the second output signal is connected to the current feedback circuit. The current feedback circuit processes the second output signal and generates two feedback control signals, CFB_P and CFB_N. CFB_P is sent to the PMOS control circuit for feedback control, and CFB_N is sent to the NMOS control circuit for feedback control. The low-dropout linear regulator generates a low-voltage supply potential LVDD with drive capability and higher than ground (GND), which is provided to the second-stage low-voltage amplifier circuit and the NMOS control circuit. The low-dropout linear regulator also generates a high-voltage supply potential H with drive capability and lower than the supply voltage VDD. GND is connected to the PMOS control circuit; the power supply voltage VDD is connected to the PMOS control circuit, and the ground potential GND is connected to the NMOS control circuit; the PMOS control circuit processes the first output signal to obtain the PMOS push-pull output control signal and sends it to the output logic control circuit; the NMOS control circuit processes the first output signal to obtain the NMOS push-pull output control signal and sends it to the output logic control circuit; the output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, thereby controlling the conduction and turn-off of the PMOS and NMOS push-pull transistors.

2. The high-voltage, high-speed push-pull comparator circuit according to claim 1, characterized in that, The first-stage differential preamplifier circuit includes first and second DepMOS transistors, a nineteenth PMOS transistor, a twentieth DepMOS transistor, and first and second resistors; the first output signal of the input protection circuit is connected to the gate of the first DepMOS transistor, and the second output signal of the input protection circuit is connected to the gate of the second DepMOS transistor; the drain of the first DepMOS transistor is connected to ground potential GND via the first resistor, and the drain of the second DepMOS transistor is connected to ground potential GND via the second resistor; the source of the first DepMOS transistor and the source of the second DepMOS transistor are respectively connected to the drain of the twentieth DepMOS transistor, the source of the twentieth DepMOS transistor is connected to the drain of the nineteenth PMOS transistor, the source of the nineteenth PMOS transistor is connected to the power supply voltage VDD, the gate of the nineteenth PMOS transistor is connected to the external current mirror VPB1, and the gate of the twentieth DepMOS transistor is connected to the external bias potential VPB3.

3. The high-voltage, high-speed push-pull comparator circuit according to claim 2, characterized in that, The second-stage low-voltage amplifier circuit includes a third to a fourth PMOS transistor, a twenty-first PMOS transistor, and a first to a second NMOS transistor; the gate of the third PMOS transistor is connected to the drain of the first DEPMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the second DEPMOS transistor; the sources of the third and fourth PMOS transistors are respectively connected to the drain of the twenty-first PMOS transistor, the source of the twenty-first PMOS transistor receives the low-voltage power supply potential LVDD generated by the low-dropout linear regulator, and the gate of the twenty-first PMOS transistor is connected to the external current mirror bias potential VPB2; The output signal of the third PMOS transistor drain is used as the second output signal of the second-stage low-voltage amplifier circuit and is connected to the current feedback circuit; the output signal of the fourth PMOS transistor drain is used as the first output signal of the second-stage low-voltage amplifier circuit and is connected to the PMOS control circuit and the NMOS control circuit. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the drain of the third PMOS transistor, and the gate of the second NMOS transistor; the gates of both the first and second NMOS transistors are connected to the current feedback circuit; the sources of both the first and second NMOS transistors are connected to ground potential GND; the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor.

4. The high-voltage, high-speed push-pull comparator circuit according to claim 3, characterized in that, The current feedback circuit includes the fifteenth to sixteenth PMOS transistors, the seventeenth to eighteenth DepMOS transistors, the third to fourth NMOS transistors, the eighth to ninth DenMOS transistors, the fourteenth to sixteenth NMOS transistors, and the seventeenth to eighteenth DenMOS transistors; the sources of the fifteenth and sixteenth PMOS transistors are both connected to the power supply voltage VDD; the gate of the fifteenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor, the drain of the fifteenth PMOS transistor is connected to the source of the seventeenth DepMOS transistor, the drain of the sixteenth PMOS transistor is connected to the source of the eighteenth DepMOS transistor, and the gates of the seventeenth and eighteenth DepMOS transistors are both connected to the external bias potential VPB3; The drain of the seventeenth DepMOS transistor is connected to the drain of the seventeenth DennoMOS transistor. The output signal of the drain of the seventeenth DepMOS transistor is used as the feedback control signal CFB_P generated by the current feedback circuit and connected to the PMOS control circuit. The drain of the eighteenth DepMOS transistor is connected to the drain of the eighteenth DennoMOS transistor. The output signal of the drain of the eighteenth DepMOS transistor is used as the feedback control signal CFB_N generated by the current feedback circuit and connected to the NMOS control circuit. The gates of the seventeenth and eighteenth densities are both connected to an external bias voltage VNB2, which keeps the fourteenth to sixteenth densities in the normal saturation region. The source of the seventeenth density is connected to the drain of the fifteenth and fourteenth densities, and the source of the eighteenth density is connected to the drain of the sixteenth density. The sources of the fourteenth, fifteenth, and sixteenth densities are all connected to ground potential GND. The gate of the fourteenth density is connected to an external current mirror bias potential VNB1, the gate of the fifteenth density is connected to the gate of the first and second densities, and the gate of the sixteenth density is connected to the drain of the eighteenth density. The gates of the eighth and ninth dendros is connected to an external bias voltage VNB3, which keeps the third and fourth dendros in the normal saturation region. The drain of the eighth dendro is connected to the PMOS control circuit, and the drain of the ninth dendro is connected to the NMOS control circuit. The source of the eighth dendro is connected to the drain of the third dendro, and the source of the ninth dendro is connected to the drain of the fourth dendro. The source of the third dendro is connected to the PMOS control circuit, and the source of the fourth dendro is connected to the NMOS control circuit.

5. The high-voltage, high-speed push-pull comparator circuit according to claim 4, characterized in that, The PMOS control circuit includes fifth to seventh PMOS transistors, eighth to tenth Depth-Medium-Semiconductor transistors, a fifth NMOS transistor, a tenth Denn-Medium-Semiconductor transistor, twelfth to thirteenth NMOS transistors, and a first Schmitt trigger. The sources of the fifth, sixth, and seventh PMOS transistors, as well as the first power supply terminal of the first Schmitt trigger, are all connected to the power supply voltage VDD. The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor and the drain of the eighth Depth-Medium-Semiconductor. The drain of the fifth PMOS transistor is connected to the source of the eighth Depth-Medium-Semiconductor, and the drain of the sixth PMOS transistor... The source of the ninth DepMOS transistor is connected to the external bias potential VPB4. The gates of the eighth, ninth, and tenth DepMOS transistors are connected to the external bias potential VPB4. The drain of the eighth DepMOS transistor is connected to the drain of the tenth DepMOS transistor and the drain of the eighth DepMOS transistor. The gate of the tenth DepMOS transistor is connected to the drain of the fourth PMOS transistor. The source of the tenth DepMOS transistor is connected to the source of the third NMOS transistor and the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the external current mirror bias potential VNB1. The source of the fifth NMOS transistor is connected to the ground potential GND. The gate of the seventh PMOS transistor is connected to the drain of the seventeenth DepMOS transistor, and the drain of the seventh PMOS transistor is connected to the source of the tenth DepMOS transistor. The drain of the ninth DepMOS transistor is connected to the input of the first Schmitt trigger and the drain of the twelfth NMOS transistor. The gate of the twelfth NMOS transistor is connected to the gate and drain of the thirteenth NMOS transistor. The sources of the twelfth and thirteenth NMOS transistors and the second power supply terminal of the first Schmitt trigger are all connected to the high-voltage power supply potential HGND. The drain of the tenth DepMOS transistor is connected to the drain of the thirteenth NMOS transistor. The output of the first Schmitt trigger is connected to the output logic control circuit.

6. The high-voltage, high-speed push-pull comparator circuit according to claim 5, characterized in that, The NMOS control circuit includes eleventh and twelfth PMOS transistors, thirteenth and fourteenth DepMOS transistors, sixth and seventh NMOS transistors, an eleventh DenMOS transistor, and a second Schmitt trigger. The source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, and the first power supply terminal of the second Schmitt trigger are all connected to a low-voltage power supply potential LVDD. The gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor, the drain of the thirteenth DepMOS transistor, and the drain of the ninth DenMOS transistor. The drain of the eleventh PMOS transistor is connected to the thirteenth DepMOS transistor. The source of the transistor, the gate of the thirteenth and fourteenth DEPMOS transistors are connected to the external bias potential VPB5, the drain of the thirteenth DEPMOS transistor is connected to the drain of the eleventh DENMOS transistor, the gate of the eleventh DENMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the eleventh DENMOS transistor is connected to the source of the tenth NMOS transistor and the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the external current mirror bias potential VNB1, and the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the second power supply terminal of the second Schmitt trigger are all connected to the ground potential GND. The drain of the twelfth PMOS transistor is connected to the source of the fourteenth DEPMOS transistor. The drains of the fourteenth DEPMOS transistor and the seventh NMOS transistor are both connected to the input of the second Schmitt trigger. The gate of the seventh NMOS transistor is connected to the gate of the sixteenth NMOS transistor, the drain of the eighteenth DENMOS transistor, and the drain of the eighteenth DEPMOS transistor. The output of the second Schmitt trigger is connected to the output logic control circuit.

7. The high-voltage, high-speed push-pull comparator circuit according to claim 6, characterized in that, The output logic control circuit performs logic processing on the PMOS and NMOS push-pull output control signals, thereby controlling the turn-on and turn-off of the PMOS and NMOS push-pull transistors. The gates of the PMOS and NMOS push-pull transistors are both connected to the output terminals of the output logic control circuit. The source of the PMOS push-pull transistor is connected to the power supply voltage VDD, the source of the NMOS push-pull transistor is grounded to the ground potential GND, and the drain of the PMOS push-pull transistor is connected to the drain of the NMOS push-pull transistor.

8. The high-voltage, high-speed push-pull comparator circuit according to claim 7, characterized in that, The first and second DePMOS transistors have the same dimensions. The first and second resistors have the same area and resistance value. The third and fourth PMOS transistors have the same dimensions. The sixteenth and seventh PMOS transistors have the same dimensions. The sixteenth and seventh NMOS transistors have the same dimensions. The twelfth and thirteenth NMOS transistors have the same dimensions. The fifth and sixth NMOS transistors have the same dimensions. The size ratio of the eleventh and twelfth PMOS transistors is equal to the size ratio of the fifth and sixth PMOS transistors. The ratio of the first NMOS transistor to the third or fourth NMOS transistor is M:1, where M is a preset value.

9. A chip circuit, characterized in that, The chip circuit includes a high-voltage, high-speed push-pull comparator circuit as described in any one of claims 1 to 8.

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