A metastable state elimination circuit, a comparator circuit, and an analog-to-digital converter
By designing a metastability elimination circuit in the SAR ADC, and utilizing an effective detection module and a forced correction module to determine and eliminate the metastability of the comparator, the problem of the comparator being in a metastable state for a long time is solved, thus improving the performance of the SAR ADC.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CANSEMI TECH INC
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-19
Smart Images
Figure CN121814094B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic device technology, and in particular to a metastability elimination circuit, a comparator circuit, and an analog-to-digital converter. Background Technology
[0002] An ADC (Analog-to-Digital Converter) is a circuit that converts analog signals into digital signals. ADCs have a wide range of applications, including communication equipment, testing instruments, and audio equipment. With the development of integrated circuit technology, SARADCs (Successive Approximation Analog-to-Digital Converters) have gained increasing attention due to their low power consumption and less susceptibility to process technology limitations.
[0003] In existing technologies, high-speed SAR ADCs often employ an asynchronous clock strategy. This means the comparator's clock is generated jointly by the comparison result and the logic circuitry, independent of an external clock supply. This strategy allows the SAR ADC to convert analog voltages into digital codes more quickly. After each bit comparison, the comparator is reset and proceeds to the next comparison, and so on, until the digital code of the sampled signal is obtained. As one of the most crucial circuit modules in a SAR ADC, the comparator is required to obtain the comparison result in a short time. However, when the difference between the sampled signals input to the comparator is small, the comparator cannot obtain a comparison result, thus entering a metastable state. This prevents it from resetting and proceeding to the next bit comparison, causing the SAR ADC to malfunction. Even if the comparator eventually emerges from the metastable state and obtains a comparison result, the comparison of that single bit will take excessive time, impacting the overall performance of the SAR ADC. Summary of the Invention
[0004] This application provides a metastability elimination circuit, a comparator circuit, and an analog-to-digital converter to detect whether the comparator is in a metastable state, and to forcibly assign a value to the comparison result of the comparator when the comparator is in a metastable state in order to eliminate the metastability of the comparator, so that the comparator can be quickly reset and start the next round of comparison. This solves the problem in the prior art that the comparator is in a metastable state for a long time, which affects the working performance of the SAR ADC.
[0005] In a first aspect, this application provides a metastability elimination circuit, including an effective detection module, a clock signal generation module, and a forced correction module, wherein:
[0006] The two input terminals of the valid detection module are used to connect to the two output terminals of the comparator. The detection signal output terminal of the valid detection module is connected to the input terminal of the clock signal generation module and the first input terminal of the forced correction module. The output terminal of the clock signal generation module is used to connect to the first clock input terminal of the comparator and the second input terminal of the forced correction module. The two output terminals of the forced correction module are respectively used to connect to the two output terminals of the comparator.
[0007] The valid detection module is used to detect whether the comparator outputs a valid comparison result and outputs a detection signal; the clock signal generation module is used to convert the detection signal into the clock signal of the comparator; the forced correction module is used to detect whether the comparator is in a metastable state according to the detection signal and the clock signal of the comparator, and to force the two output terminals of the comparator to be assigned values when the comparator is in a metastable state.
[0008] Optionally, the valid detection module includes an OR gate, the two inputs of which are connected to the two outputs of a comparator, and the output of which is connected to the input of the clock signal generation module.
[0009] Optionally, the clock signal generation module includes a first delay gate and a first inverter. The input of the first delay gate is connected to the detection signal output of the valid detection module, the output of the first delay gate is connected to the input of the first inverter, and the output of the first inverter is used to connect to the first clock input of the comparator and the second input of the forced correction module.
[0010] Optionally, the forced correction module includes a delay unit, a trigger control unit, and a forced assignment unit, wherein:
[0011] The input terminal of the delay unit is connected to the output terminal of the clock signal generation module, the output terminal of the delay unit is connected to the first input terminal of the trigger control unit, the second input terminal of the trigger control unit is connected to the detection signal output terminal of the valid detection module, the output terminal of the trigger control unit is connected to the control terminal of the forced assignment unit, the two input terminals of the forced assignment unit are respectively connected to the positive and negative terminals of the power supply, and the two output terminals of the forced assignment unit are respectively used to connect to the two output terminals of the comparator.
[0012] The delay unit is used to delay the clock signal transmitted by the clock signal generation module for a second preset duration, the second preset duration being longer than the normal comparison duration of the comparator; the trigger control unit is used to detect whether the comparator is in a metastable state based on the detection signal and the delayed clock signal, and if so, to send a trigger control signal to the forced assignment unit; the forced assignment unit is used to control the closure of the path between the corresponding input terminal and the output terminal when the trigger control signal is received.
[0013] Optionally, the delay unit includes a second delay gate, the input of which is connected to the output of the clock signal generation module, and the output of which is connected to the first input of the trigger control unit.
[0014] Optionally, the trigger control unit includes a data trigger, the second clock input terminal of the data trigger is connected to the output terminal of the delay unit, the data input terminal of the data trigger is connected to the positive terminal of the power supply, the reset input terminal of the data trigger is connected to the detection signal output terminal of the valid detection module, and the output terminal and the inverting output terminal of the data trigger are connected to the control terminal of the forced assignment unit.
[0015] Optionally, the forced assignment unit includes a second NMOS transistor and a second PMOS transistor. The output terminal of the data flip-flop is connected to the gate of the second NMOS transistor, the inverting output terminal of the data flip-flop is connected to the gate of the second PMOS transistor, the drain of the second NMOS transistor is used to connect to the first output terminal of the comparator, the drain of the second PMOS transistor is used to connect to the second output terminal of the comparator, the source of the second NMOS transistor is connected to the negative power supply, and the source of the second PMOS transistor is connected to the positive power supply.
[0016] Optionally, the forced assignment unit further includes a first NMOS transistor and a first PMOS transistor, wherein the gate and source of the first NMOS transistor are connected to the negative terminal of the power supply, the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, the gate and source of the first PMOS transistor are connected to the positive terminal of the power supply, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor.
[0017] Secondly, this application provides a comparator circuit, including a comparator and a metastability elimination circuit as described in the first aspect. The two input terminals of the effective detection module of the metastability elimination circuit are connected to the two output terminals of the comparator. The output terminal of the clock signal generation module of the metastability elimination circuit is connected to the first clock input terminal of the comparator. The two output terminals of the forced correction module of the metastability elimination circuit are connected to the two output terminals of the comparator.
[0018] Thirdly, this application provides an analog-to-digital converter including a comparator circuit as described in the second aspect.
[0019] In this application, a valid detection module, a clock signal generation module, and a forced correction module are incorporated into the metastability elimination circuit. The two inputs of the valid detection module are connected to the two outputs of the comparator. The detection signal output of the valid detection module is connected to the input of the clock signal generation module and the first input of the forced correction module. The output of the clock signal generation module is connected to the first clock input of the comparator and the second input of the forced correction module. The two outputs of the forced correction module are respectively connected to the two outputs of the comparator. The metastability elimination circuit uses the valid detection module to detect whether the comparator outputs a valid comparison result and outputs a detection signal. The clock signal generation module converts the detection signal into the comparator's clock signal. The forced correction module detects whether the comparator is in a metastable state based on the detection signal and the comparator's clock signal, and forces a value to be assigned to the two outputs of the comparator when the comparator is in a metastable state. By employing the aforementioned technical means, the comparator is detected to be in a metastable state using the detection signal output by the effective detection module and the clock signal output by the clock signal generation module. When the comparator is in a metastable state, a forced value is assigned to its output to eliminate the metastability, allowing the comparator to quickly reset and begin the next comparison. This solves the problem in existing technologies where prolonged metastability of the comparator affects the performance of the SAR ADC. Furthermore, when the comparator is not in a metastable state, the clock signal generation module and the effective detection module can automatically provide a clock signal to the comparator to ensure its normal operation. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a metastability elimination circuit provided in an embodiment of this application;
[0021] Figure 2 This is a schematic diagram of the comparator provided in an embodiment of this application;
[0022] Figure 3 This is a schematic diagram of the structure of the effective detection module provided in the embodiments of this application;
[0023] Figure 4 This is a schematic diagram of the clock signal generation module provided in an embodiment of this application;
[0024] Figure 5 This is a schematic diagram of the forced correction module provided in an embodiment of this application;
[0025] Figure 6 This is a signal waveform diagram of the comparator under normal conditions provided in the embodiments of this application;
[0026] Figure 7 This is a waveform diagram of the comparator in metastable state provided in an embodiment of this application;
[0027] In the diagram, 11 is the delay unit; 12 is the trigger control unit; 13 is the forced assignment unit; OR is the OR gate; OUTP is the first output of the comparator; OUTN is the second output of the comparator; INP is the first input of the comparator; INN is the second input of the comparator; VALID is the detection signal output; BUF1 is the first delay gate; INV is the first inverter; CMPCLK is the first clock input; BUF2 is the second delay gate; CMPCLK_D is the second clock input; VDD is the positive power supply; VSS is the negative power supply; DFF is the data flip-flop; D is the data input of the data flip-flop; R is the reset input of the data flip-flop; Q is the output of the data flip-flop; QN is the inverted output of the data flip-flop; MN9 is the second NMOS transistor; MN8 is the first NMOS transistor; MP7 is the second PMOS transistor; MP8 is the first PMOS transistor. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. A process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.
[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0030] In common existing implementations, high-speed SAR ADCs often employ an asynchronous clock strategy. This means the comparator's clock is generated jointly by the comparison result and the logic circuitry, independent of an external clock supply. This strategy allows the SAR ADC to convert analog voltage to digital code more quickly. After each bit comparison, the comparator is reset and proceeds to the next comparison, and so on, until the digital code of the sampled signal is obtained. As one of the most important circuit modules in a SAR ADC, the comparator is required to obtain the comparison result in a short time. However, when the difference between the sampled signals input to the comparator is small, the comparator cannot obtain a comparison result, thus entering a metastable state. It cannot be reset or proceed to the next bit comparison, causing the SAR ADC to malfunction. Even if the comparator eventually emerges from the metastable state and obtains a comparison result, the comparison of that single bit will take excessive time, affecting the overall performance of the SAR ADC.
[0031] To address the aforementioned issues, this embodiment provides a metastability elimination circuit to detect whether the comparator is in a metastable state, and to forcibly assign a value to the comparison result of the comparator when the comparator is in a metastable state, thereby eliminating the metastability of the comparator and enabling the comparator to quickly reset and start the next round of comparison.
[0032] Figure 1 A schematic diagram of a metastability elimination circuit provided in an embodiment of this application is given. Figure 1 As shown, the metastability elimination circuit includes a valid detection module, a clock signal generation module, and a forced correction module. The two inputs of the valid detection module are connected to the two outputs of the comparator. The detection signal output terminal VALID of the valid detection module is connected to the input of the clock signal generation module and the first input of the forced correction module. The output of the clock signal generation module is connected to the first clock input terminal CMPCLK of the comparator and the second input of the forced correction module. The two outputs of the forced correction module are respectively connected to the two outputs of the comparator. Specifically, the valid detection module detects whether the comparator outputs a valid comparison result and outputs a detection signal; the clock signal generation module converts the detection signal into the comparator's clock signal; and the forced correction module detects whether the comparator is in a metastable state based on the detection signal and the comparator's clock signal, and forces a value to be assigned to the two outputs of the comparator when the comparator is in a metastable state.
[0033] For example, Figure 2 This is a schematic diagram of the comparator provided in an embodiment of this application. Figure 2As shown, the comparator includes a first clock input terminal CMPCLK, a first input terminal INP, a second input terminal INN, a first output terminal OUTP, a second output terminal OUTN, and various MOSFETs. The comparator operates as follows: A single pulse signal is input to the first clock input terminal CMPCLK via SAMCLK. Under the action of this single pulse signal, the comparator initiates its first comparison, comparing the signals input to the first input terminal INP and the second input terminal INN, and outputting the comparison result through the first output terminal OUTP and the second output terminal OUTN. During the comparison, if the comparator determines that the signal at the first input terminal INP is greater than the signal at the second input terminal INN, or if the signal at the first input terminal INP is less than the signal at the second input terminal INN, the comparator controls one of the first output terminals OUTP and OUTN to output a high-level signal while the other outputs a low-level signal. If the comparator cannot determine which signal at the first input terminal INP or the second input terminal INN is greater, both the first output terminal OUTP and the second output terminal OUTN output low-level signals.
[0034] The comparator's first output terminal OUTP and second output terminal OUTN are connected to a valid detection module. The valid detection module detects whether the comparator outputs a valid comparison result based on whether the first output terminal OUTP and second output terminal OUTN output low-level signals simultaneously or high-level signals and low-level signals respectively. When the valid detection module confirms that the first output terminal OUTP and second output terminal OUTN output low-level signals simultaneously, it can confirm that the comparator is still in the comparison process and has not yet output a valid comparison result. The valid detection module then outputs a low-level detection signal to indicate that the comparator is still in the comparison process. When the valid detection module confirms that the first output terminal OUTP and second output terminal OUTN output low-level signals and high-level signals respectively, it can confirm that the comparator's comparison process has ended and a valid comparison result has been output. The valid detection module then outputs a high-level detection signal to indicate that the comparator's comparison process has ended.
[0035] Optionally, the valid detection module includes an OR gate, where the two inputs of the OR gate are connected to the two outputs of a comparator, and the output of the OR gate is connected to the input of a clock signal generation module. For example, Figure 3 This is a schematic diagram of the structure of the effective detection module provided in the embodiments of this application. For example... Figure 3As shown, the two inputs of the OR gate are connected to the first output OUTP and the second output OUTN of the comparator, respectively. The output of the OR gate serves as the detection signal output VALID to output the detection signal. The detection signal is transmitted to the input of the clock signal generation module and the first input of the forced correction module. This embodiment uses the OR gate as the core component for effective detection, realizing rapid detection of the comparator output validity. The circuit structure is simple and has a fast response speed, without additional complex logic, and is suitable for the stringent requirements of high-speed SAR ADCs for detection delay.
[0036] Of course, the valid detection module can also use a NOR gate. When the NOR gate outputs a high-level detection signal, it indicates that the comparator comparison has not yet ended or is being reset; when the NOR gate outputs a low-level detection signal, it indicates that the comparator comparison has ended. That is, the detection signals output by the NOR gate and the OR gate have completely opposite meanings. The structures of the clock signal generation module and the forced correction module can be adaptively set according to the meaning of the detection signals output by the valid detection module. Alternatively, the valid detection module can also use a combination circuit of a NOR gate and an inverter. That is, the input of the NOR gate is connected to the output of the comparator, the output of the NOR gate is connected to the input of the inverter, and the inverter outputs a detection signal. In this case, the detection signal output by the inverter has the same meaning as the detection signal output by the OR gate.
[0037] refer to Figure 1 The detection signal output terminal VALID of the valid detection module is connected to the input terminal of the clock signal generation module and the first input terminal of the forced correction module. When the detection signal output terminal VALID outputs a detection signal, the clock signal generation module converts the detection signal into the clock signal required by the comparator and outputs it, so that the output clock signal is input to the first clock input terminal CMPCLK of the comparator. This embodiment describes the comparison as a high-level detection signal indicating that the comparator has finished and a low-level detection signal indicating that the comparator has not finished. The clock signal generation module can be an inverter. When the valid detection module outputs a high-level detection signal, the comparator should start the next round of comparison. At this time, the comparator needs to input a low-level clock signal for reset. To this end, the clock signal generation module inverts the high-level detection signal to obtain a low-level clock signal, which is input to the first clock input terminal CMPCLK of the comparator. The comparator is reset under the action of the low-level clock signal. When the detection signal output terminal VALID outputs a low-level detection signal, the comparator should maintain the comparison process of that round. At this time, the comparator needs to input a high-level clock signal to maintain the comparison process. To this end, the clock signal generation module inverts the low-level detection signal to obtain a high-level clock signal, which is input to the first clock input terminal CMPCLK of the comparator. The comparator continues to compare under the action of the high-level clock signal.
[0038] Optional, Figure 4 This is a schematic diagram of the clock signal generation module provided in an embodiment of this application. Figure 4 As shown, the clock signal generation module includes a first delay gate BUF1 and a first inverter INV. The input of the first delay gate BUF1 is connected to the detection signal output VALID of the valid detection module, and the output of the first delay gate BUF1 is connected to the input of the first inverter INV. The output of the first inverter INV is used to connect to the first clock input CMPCLK of the comparator and the second input of the forced correction module. The clock signal generation module first delays the detection signal by a first preset time Td through the first delay gate BUF1 before transmitting it to the first inverter INV. The first inverter INV inverts the delayed detection signal to obtain the clock signal. Understandably, once the valid detection module detects a valid comparison result from the comparator, it outputs a high-level detection signal. If the detection signal is inverted and input to the comparator without delay processing, the comparator will immediately switch to a reset state. In the reset state, the comparator clears the comparison result within a short time, causing the first output terminal OUTP and the second output terminal OUTN to output low-level signals. This results in the detection signal output terminal VALID also being a low-level signal. After the low-level signal is inverted by the clock signal generation module to obtain a high-level signal, it is input to the comparator. The comparator will quickly enter the next comparison state from the reset state, which results in insufficient time for the comparator to reset, thus affecting the reliability of the comparator. To address this, this embodiment adds a first delay gate BUF1 to the clock signal generation module. The first delay gate BUF1 delays the detection signal for a certain period of time before inputting it to the comparator, allowing the comparator sufficient time to reset and ensuring the reliability of the comparator.
[0039] refer to Figure 1 The detection signal output terminal VALID of the effective detection module is connected to the first input terminal of the forced correction module, and the output terminal of the clock signal generation module is connected to the second input terminal of the forced correction module. The forced correction module can determine whether the comparator is in a metastable state based on the detection signal input at the detection signal output terminal VALID and the clock signal input at the clock signal generation module. When the comparator is in a metastable state, the first output terminal OUTP and the second output terminal OUTN of the comparator are forcibly assigned values to eliminate the metastability of the comparator.
[0040] In one embodiment, Figure 5 This is a schematic diagram of the forced correction module provided in an embodiment of this application. Figure 5As shown, the forced correction module includes a delay unit 11, a trigger control unit 12, and a forced assignment unit 13. The input of the delay unit 11 is connected to the output of the clock signal generation module, and the output of the delay unit 11 is connected to the first input of the trigger control unit 12. The second input of the trigger control unit 12 is connected to the detection signal output VALID of the valid detection module, and the output of the trigger control unit 12 is connected to the control terminal of the forced assignment unit 13. The two inputs of the forced assignment unit 13 are respectively connected to the positive power supply VDD and the negative power supply VSS, and the two outputs of the forced assignment unit 13 are respectively used to connect to the two outputs of the comparator. Specifically, the delay unit 11 delays the clock signal transmitted by the clock signal generation module by a second preset duration, which is longer than the normal comparison duration of the comparator. The trigger control unit 12 detects whether the comparator is in a metastable state based on the detection signal and the delayed clock signal; if so, it sends a trigger control signal to the forced assignment unit 13. The forced assignment unit 13, upon receiving the trigger control signal, controls the closure of the path between the corresponding input and output terminals.
[0041] When the delay unit 11 receives a clock signal transmitted by the SAMCLK transmission or the clock signal generation module, it delays the rising edge of the clock signal by a second preset duration, so that the rising edge of the clock signal is input to the trigger control unit 12 after the second preset duration. Before the rising edge of the clock signal arrives, the trigger control unit 12 receives the detection signal transmitted by the detection signal output terminal VALID. If the detection signal is a low-level signal, the trigger control unit 12 confirms that the comparator is in the comparison state and the comparison duration has not exceeded the normal comparison duration, thus determining that the comparator is not in a metastable state and not sending a trigger control signal to the forced assignment unit 13. If the detection signal is a high-level signal, the trigger control unit 12 confirms that the comparison of the comparator has ended, thus determining that the comparator is not in a metastable state and not sending a trigger control signal to the forced assignment unit 13. If the trigger control unit 12 still receives a low-level detection signal when the rising edge of the clock signal arrives, it confirms that the comparator is in the comparison state and the comparison duration exceeds the normal comparison duration, thus determining that the comparator is in a metastable state and sending a trigger control signal to the forced assignment unit 13. When no trigger control signal is received, the forced assignment unit 13 keeps the paths between the negative power supply VSS and the positive power supply VDD and the first output terminal OUTP and the second output terminal OUTN of the comparator disconnected, so that the output signals of the first output terminal OUTP and the second output terminal OUTN are the comparison results of the comparator. When the trigger control signal is received, the forced assignment unit 13 controls the paths between the negative power supply VSS and the positive power supply VDD and the first output terminal OUTP and the second output terminal OUTN of the comparator to be connected, so that one of the first output terminal OUTP and the second output terminal OUTN outputs a low level and the other outputs a high level. This causes the effective detection module to output a high-level detection signal. The high-level detection signal is converted into a low-level clock signal after inversion and then input to the comparator. Under the action of the low-level clock signal, the comparator switches from the metastable state to the reset state, thus smoothly getting out of the metastable state and avoiding the comparator being in the metastable state for a long time, which would affect the working performance of the SAR ADC.
[0042] Optional, see reference Figure 5 The delay unit 11 includes a second delay gate BUF2. The input of the second delay gate BUF2 is connected to the output of the clock signal generation module, and the output of the second delay gate BUF2 is connected to the first input of the trigger control unit 12. For example, the second delay gate BUF2 delays the clock signal by a second preset duration before inputting it to the trigger control unit 12. In this embodiment, the second delay gate BUF2 is used as the core of the delay unit 11 to achieve precise delay of the clock signal, providing a reliable timing reference for metastability judgment, and ensuring that the trigger control unit 12 only initiates correction when the comparator is indeed in a metastable state, thus avoiding false triggering.
[0043] Optional, see reference Figure 5 The trigger control unit 12 includes a data trigger DFF. The second clock input terminal CMPCLK_D of the data trigger DFF is connected to the output terminal of the delay unit 11. The data input terminal D of the data trigger DFF is connected to the positive power supply VDD. The reset input terminal R of the data trigger DFF is connected to the detection signal output terminal VALID of the valid detection module. The output terminal Q and the inverted output terminal QN of the data trigger DFF are connected to the control terminal of the forced assignment unit 13. For example, when the valid detection module outputs a low-level detection signal, the reset input terminal R of the data flip-flop DFF receives an invalid signal, causing the data flip-flop DFF to enter the working mode. The data input terminal D of the data flip-flop DFF receives a high-level signal transmitted from the positive power supply VDD. The second clock input terminal CMPCLK_D of the data flip-flop DFF receives a signal transmitted from the delay unit 11. If the second clock input terminal CMPCLK_D inputs a stable level signal or a falling edge signal, the output terminal Q of the data flip-flop DFF outputs a low-level signal and the inverting output terminal QN outputs a high-level signal. Under the action of the low-level signal transmitted at the output terminal, the forced assignment unit 13 disconnects the path between the negative power supply VSS and the first output terminal OUTP. Under the action of the high-level signal transmitted at the output terminal, the forced assignment unit 13 disconnects the path between the positive power supply VDD and the second output terminal OUTN. When the data flip-flop (DFF) enters the working mode, if the second clock input terminal CMPCLK_D receives a rising edge signal, the output terminal Q of the data flip-flop DFF outputs a high-level signal and the inverting output terminal QN outputs a low-level signal. Under the action of the high-level signal transmitted at the output terminal, the forced assignment unit 13 closes the path between the negative power supply VSS and the first output terminal OUTP. Under the action of the low-level signal transmitted at the output terminal, the forced assignment unit 13 closes the path between the positive power supply VDD and the second output terminal OUTN. The first output terminal OUTP is forced to output a low-level signal and the second output terminal OUTN is forced to output a high-level signal. When the detection signal output terminal VALID outputs a high-level detection signal, the reset input terminal R of the data flip-flop DFF receives a valid signal, causing the data flip-flop DFF to enter the reset mode. The output terminal Q of the data flip-flop DFF outputs a low level, the inverting output terminal QN outputs a high level, the path between the positive power supply VDD and the second output terminal OUTN is disconnected, and the path between the negative power supply VSS and the first output terminal OUTP is disconnected.
[0044] When the first output terminal OUTP is forced to output a low-level signal and the second output terminal OUTN is forced to output a high-level signal, the effective detection module inputs both high-level and low-level signals to output a high-level detection signal. This high-level detection signal is inverted by the clock signal generation module and then input to the comparator, forcing a reset to escape the metastability state. Simultaneously, the high-level detection signal acts on the reset input R of the data flip-flop DFF, causing DFF to enter reset mode. Output Q outputs a low level, and the inverted output QN outputs a high level. The path between the first output terminal OUTP and the negative power supply VSS, as well as the path between the second output terminal OUTN and the positive power supply VDD, is broken. This allows the comparator to output its comparison result normally, preventing forced assignment of values to the first and second output terminals OUTP and OUTN from affecting the comparator's normal operation and ensuring its reliability.
[0045] In this embodiment, a data flip-flop (DFF) is used as the core of the trigger control unit 12. By utilizing the working characteristics of the DFF, the detection signal and the delayed clock signal are precisely linked logically, thereby accurately determining whether the comparator is in a metastable state, ensuring the accuracy of the trigger control signal output, and thus ensuring the reliable operation of the forced correction unit.
[0046] Optional, see reference Figure 5The forced assignment unit 13 includes a second NMOS transistor MN9 and a second PMOS transistor MP7. The output terminal Q of the data flip-flop DFF is connected to the gate of the second NMOS transistor MN9, and the inverted output terminal QN of the data flip-flop DFF is connected to the gate of the second PMOS transistor MP7. The drain of the second NMOS transistor MN9 is connected to the first output terminal OUTP of the comparator, and the drain of the second PMOS transistor MP7 is connected to the second output terminal OUTN of the comparator. The source of the second NMOS transistor MN9 is connected to the negative power supply VSS, and the source of the second PMOS transistor MP7 is connected to the positive power supply VDD. For example, when the gate of the second NMOS transistor MN9 receives a high-level signal from the output terminal Q of the data flip-flop DFF, and the gate of the second PMOS transistor MP7 receives a low-level signal from the inverted output terminal QN of the data flip-flop DFF, the path between the source and drain of the second NMOS transistor MN9 is closed, so that the first output terminal OUTP of the comparator is connected to the negative power supply VSS, and the first output terminal OUTP is forced low. The path between the source and drain of the second PMOS transistor MP7 is closed, connecting the second output terminal OUTN of the comparator to the positive power supply VDD, thus forcing OUTN to a high level. Subsequently, the valid detection module outputs a high-level signal to the reset input R of the data flip-flop DFF, causing DFF to enter reset mode. When output Q is low and the inverting output QN is high, the path between the second PMOS transistor MP7 and the second NMOS transistor MN9 is broken. This allows the first output terminal OUTP and the second output terminal OUTN of the comparator to output the comparison result normally, preventing prolonged forced assignment of values to the first and second output terminals OUTP and OUTN, which could affect the normal operation of the comparator.
[0047] This embodiment utilizes the conduction and cutoff characteristics of a MOSFET to quickly pull the first output terminal OUTP and the second output terminal OUTN of the comparator to the negative power supply VSS and the positive power supply VDD respectively under the output of the data flip-flop DFF, thereby achieving rapid exit from metastability.
[0048] Optional, see reference Figure 5The forced assignment unit 13 further includes a first NMOS transistor MN8 and a first PMOS transistor MP8. The gate and source of the first NMOS transistor MN8 are connected to the negative power supply VSS, the drain of the first NMOS transistor MN8 is connected to the drain of the second PMOS transistor MP7, the gate and source of the first PMOS transistor MP8 are connected to the positive power supply VDD, and the drain of the first PMOS transistor MP8 is connected to the drain of the second NMOS transistor MN9. For example, the gate and source of the first PMOS transistor MP8 are shorted through the positive power supply VDD. When the second NMOS transistor MN9 is in the on state, the first PMOS transistor MP8 is in the off state. The gate and source of the first NMOS transistor MN8 are shorted through the negative power supply VSS. When the second PMOS transistor MP7 is in the on state, the first NMOS transistor MN8 is in the off state. The first NMOS transistor MN8 and the first PMOS transistor can be used to balance the load of the first output terminal OUTP and the second output terminal OUTN, improving the symmetry of the comparator.
[0049] To better understand the operation of the metastability elimination circuit, this embodiment will... Figures 3-5 Taking the metastability elimination circuit, which combines the effective detection module, clock signal generation module, and forced correction module, as an example, and combining it with... Figure 6 and Figure 7 The diagram shows the signal waveforms of the comparator in its normal state and in its metastable state, illustrating the working principle of the metastability elimination circuit.
[0050] like Figure 6 As shown, the single-pulse signal emitted by SAMPCLK is inverted and then input to the first clock input terminal CMPCLK of the comparator. At the first falling edge of the single-pulse signal, the first clock input terminal CMPCLK receives the first rising edge signal, and the comparator starts the first round of comparison. The comparator comparison takes time, so initially, both the first output terminal OUTP and the second output terminal OUTN output low-level signals, thus effectively detecting that the detection signal output terminal VALID of the detection module is also low-level in the early stage. Since the first clock input terminal CMPCLK of the comparator is connected to the input terminal of the second delay gate BUF2, the first rising edge signal of the clock signal is delayed by a second preset time T. META Then it is transmitted to the second clock input CMPCLK_D of the data flip-flop DFF. The comparator completes the normal comparison time T. CMPAfter outputting a valid comparison result, the detection signal output terminal VALID rises from a low level to a high level. The detection signal at the detection signal output terminal VALID is delayed by a first preset time Td through the first delay gate BUF1 and then inverted to generate a clock signal. The first falling edge signal at the first clock input terminal CMPCLK arrives after a delay of Td from the first rising edge signal of the detection signal. At this time, the comparator enters the reset state under the action of the falling edge signal. In the reset state, the comparator clears the first output terminal OUTP and the second output terminal OUTN to zero. When the first output terminal OUTP and the second output terminal OUTN are cleared, the detection signal falls from a high level to a low level. The low-level detection signal is delayed by Td and then inverted to generate a clock signal. The second rising edge signal at the first clock input terminal CMPCLK arrives after a delay of Td from the first falling edge signal of the detection signal. The comparator starts the second round of comparison under the action of the second rising edge signal at the first clock input terminal CMPCLK. This achieves normal operation of the comparator even with the addition of a metastability elimination circuit.
[0051] It should be noted that the signal at the second clock input terminal CMPCLK_D is equivalent to shifting the entire signal at the first clock input terminal CMPCLK backward by T. META That is, the rising edge signal of the second clock input terminal CMPCLK_D is the rising edge signal of the first clock input terminal CMPCLK after passing through T. META After a delay, the data trigger DFF is reached. If the comparator is operating normally, the detection signal at the detection signal output terminal VALID must be high. Otherwise, the data trigger DFF will control the second PMOS transistor MP7 and the second NMOS transistor MN9 to conduct, forcibly assigning values to the first output terminal OUTP and the second output terminal OUTN of the comparator, interfering with the normal operation of the comparator. Therefore, the second preset duration T... META The range of values is greater than the normal comparison time T of the comparator. CMP And less than or equal to the normal comparison duration T CMP The sum of the first preset duration Td ensures that when the rising edge signal of the second clock input CMPCLK_D arrives at the data flip-flop DFF, the data flip-flop DFF is in a reset state.
[0052] like Figure 7 As shown, when the actual comparison time of the comparator exceeds the second preset time T METASubsequently, the reset input R of the data flip-flop (DFF) receives a low-level signal from the detection signal output VALID and the first rising edge signal from the second clock input CMPCLK_D. The output Q of the DFF then outputs a high-level signal, and the inverting output QN outputs a low-level signal. This forces the first output OUTP of the comparator to a low level and the second output OUTN to a high level. The detection signal output VALID rises from a low level to a high level, outputting the first rising edge signal. The first rising edge signal of the detection signal output VALID is delayed by Td by the first delay gate BUF1 and then inverted. The second falling edge signal received by the first clock input CMPCLK is Td later than the first rising edge signal of the detection signal output VALID. The first clock input CMPCLK enters a reset state under the influence of the falling edge signal. After the reset state ends, it waits for the next rising edge signal to start the next round of comparison. This achieves the metastability elimination circuit forcibly switching the comparator from a metastable state to a reset state, preventing the comparator from remaining in a metastable state for an extended period and affecting the performance of the SAR ADC. Furthermore, the high-level signal output from the detection signal output terminal VALID acts on the reset input terminal R of the data flip-flop DFF, causing the data flip-flop DFF to enter reset mode. The output terminal Q of the data flip-flop DFF outputs a low-level signal, and the inverting output terminal QN outputs a high-level signal. This disconnects the paths of the second PMOS transistor MP7 and the second NMOS transistor MN9, allowing the comparator's first output terminal OUTP and second output terminal OUTN to output the comparator's comparison result normally. Afterward, the comparator can start comparing upon receiving a rising edge signal and output the corresponding comparison result through the first output terminal OUTP and the second output terminal OUTN.
[0053] In summary, the metastability elimination circuit provided in this application includes a valid detection module, a clock signal generation module, and a forced correction module. The two inputs of the valid detection module are connected to the two outputs of the comparator. The detection signal output terminal VALID of the valid detection module is connected to the input of the clock signal generation module and the first input of the forced correction module. The output of the clock signal generation module is connected to the first clock input terminal CMPCLK of the comparator and the second input of the forced correction module. The two outputs of the forced correction module are respectively connected to the two outputs of the comparator. The metastability elimination circuit uses the valid detection module to detect whether the comparator outputs a valid comparison result and outputs a detection signal. The clock signal generation module converts the detection signal into the comparator's clock signal. The forced correction module detects whether the comparator is in a metastable state based on the detection signal and the comparator's clock signal, and forces a value to be assigned to the two outputs of the comparator when the comparator is in a metastable state. By employing the aforementioned technical means, the comparator is detected to be in a metastable state using the detection signal output by the effective detection module and the clock signal output by the clock signal generation module. When the comparator is in a metastable state, a forced value is assigned to its output to eliminate the metastability, allowing the comparator to quickly reset and begin the next comparison. This solves the problem in existing technologies where prolonged metastability of the comparator affects the performance of the SAR ADC. Furthermore, when the comparator is not in a metastable state, the clock signal generation module and the effective detection module can automatically provide a clock signal to the comparator to ensure its normal operation.
[0054] Based on the above embodiments, this embodiment also provides a comparator circuit, which includes a comparator and a metastability elimination circuit as described in the above embodiments. The two input terminals of the effective detection module of the metastability elimination circuit are connected to the two output terminals of the comparator. The output terminal of the clock signal generation module of the metastability elimination circuit is connected to the first clock input terminal CMPCLK of the comparator. The two output terminals of the forced correction module of the metastability elimination circuit are connected to the two output terminals of the comparator. Specifically, the structure of the comparator and the metastability elimination circuit can be found in [reference needed]. Figure 2 and Figure 1 This will not be elaborated further here. In this embodiment, the metastability elimination circuit is integrated with the comparator to solve the metastability problem of the comparator in high-speed comparison scenarios, so that the comparator can output valid results quickly, with faster response speed and significantly improved working stability.
[0055] Based on the above embodiments, this embodiment also provides an analog-to-digital converter (ADC) including the comparator circuit described in the above embodiments. This embodiment adds a comparator circuit with metastability cancellation function to the ADC to solve the problem of reduced conversion efficiency of SAR ADCs caused by comparator metastability, significantly improving the overall operating stability and conversion efficiency of the ADC.
[0056] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application. The scope of this application is determined by the scope of the claims.
Claims
1. A metastability elimination circuit, characterized by, It includes an effective detection module, a clock signal generation module, and a forced correction module, wherein: The two input terminals of the valid detection module are used to connect to the two output terminals of the comparator. The detection signal output terminal of the valid detection module is connected to the input terminal of the clock signal generation module and the first input terminal of the forced correction module. The output terminal of the clock signal generation module is used to connect to the first clock input terminal of the comparator and the second input terminal of the forced correction module. The two output terminals of the forced correction module are respectively used to connect to the two output terminals of the comparator. The valid detection module is used to detect whether the comparator outputs a valid comparison result and outputs a detection signal; the clock signal generation module is used to convert the detection signal into the clock signal of the comparator; the forced correction module is used to detect whether the comparator is in a metastable state according to the detection signal and the clock signal of the comparator, and to force the two output terminals of the comparator to be assigned values when the comparator is in a metastable state. The forced correction module includes a delay unit, a trigger control unit, and a forced assignment unit, wherein: the input terminal of the delay unit is connected to the output terminal of the clock signal generation module; the output terminal of the delay unit is connected to the first input terminal of the trigger control unit; the second input terminal of the trigger control unit is connected to the detection signal output terminal of the valid detection module; the output terminal of the trigger control unit is connected to the control terminal of the forced assignment unit; the two input terminals of the forced assignment unit are respectively connected to the positive and negative terminals of the power supply; and the two output terminals of the forced assignment unit are respectively used to connect to the two output terminals of the comparator. The delay unit is used to delay the clock signal transmitted by the clock signal generation module for a second preset duration, the second preset duration being longer than the normal comparison duration of the comparator. The trigger control unit is used to detect whether the comparator is in a metastable state based on the detection signal and the delayed clock signal; if so, it sends a trigger control signal to the forced assignment unit. The forced assignment unit is used to control the closure of the path between the corresponding input terminal and the output terminal upon receiving the trigger control signal.
2. The metastability-cancelling circuit of claim 1, wherein, The effective detection module includes an OR gate, the two inputs of which are connected to the two outputs of a comparator, and the output of which is connected to the input of the clock signal generation module and the first input of the forced correction module.
3. The metastability-cancelling circuit of claim 1, wherein, The clock signal generation module includes a first delay gate and a first inverter. The input of the first delay gate is connected to the detection signal output of the valid detection module, and the output of the first delay gate is connected to the input of the first inverter. The output of the first inverter is used to connect to the first clock input of the comparator and the second input of the forced correction module.
4. The metastability-cancelling circuit of claim 1, wherein, The delay unit includes a second delay gate, the input of which is connected to the output of the clock signal generation module, and the output of which is connected to the first input of the trigger control unit.
5. The metastability-cancelling circuit of claim 1, wherein, The trigger control unit includes a data trigger. The second clock input of the data trigger is connected to the output of the delay unit. The data input of the data trigger is connected to the positive terminal of the power supply. The reset input of the data trigger is connected to the detection signal output of the valid detection module. The output and inverted output of the data trigger are connected to the control terminal of the forced assignment unit.
6. The metastability-cancelling circuit of claim 5, wherein, The forced assignment unit includes a second NMOS transistor and a second PMOS transistor. The output terminal of the data flip-flop is connected to the gate of the second NMOS transistor, the inverting output terminal of the data flip-flop is connected to the gate of the second PMOS transistor, the drain of the second NMOS transistor is connected to the first output terminal of the comparator, the drain of the second PMOS transistor is connected to the second output terminal of the comparator, the source of the second NMOS transistor is connected to the negative terminal of the power supply, and the source of the second PMOS transistor is connected to the positive terminal of the power supply.
7. The metastability-cancelling circuit of claim 6, wherein, The forced assignment unit further includes a first NMOS transistor and a first PMOS transistor. The gate and source of the first NMOS transistor are connected to the negative terminal of the power supply, the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, the gate and source of the first PMOS transistor are connected to the positive terminal of the power supply, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor.
8. A comparator circuit, characterized by The device includes a comparator and a metastability elimination circuit as described in any one of claims 1-7, wherein the two input terminals of the effective detection module of the metastability elimination circuit are connected to the two output terminals of the comparator, the output terminal of the clock signal generation module of the metastability elimination circuit is connected to the first clock input terminal of the comparator, and the two output terminals of the forced correction module of the metastability elimination circuit are connected to the two output terminals of the comparator.
9. An analog-to-digital converter, characterized by Includes the comparator circuit as described in claim 8.