Method, device, storage medium and program product for writing data to a register

Abstract

This disclosure relates to the field of register read / write technology, and in particular provides a method, apparatus, storage medium, and program product for writing data to a register. The method includes: acquiring current data being transferred by a target processor to a hardware control register, and acquiring a modification permission identifier of the target processor; acquiring target data corresponding to a data bit in the current data, and acquiring first interface control data stored in the hardware control register; modifying the data corresponding to the data bit in the first interface control register to the target data, thereby obtaining the latest interface control data. When the target processor writes data to the hardware control register, it can only modify the data stored in the data bit indicated by the modification permission identifier in the hardware control register, and cannot modify the data stored in other data bits in the hardware control register. This effectively prevents one processor from overwriting data written to the hardware control register by other processors.

Description

Technical Field

[0001] This disclosure relates to the field of register read / write technology, and in particular to a method, apparatus, storage medium, and program product for writing data to a register. Background Technology

[0002] In a multiprocessor (CPU) system, when multiple independent CPUs need to concurrently write to different bit fields of the same set of hardware control registers (such as I / O data registers and direction registers), a write operation by one CPU may unintentionally overwrite bit field data that has been written by other CPUs but has not yet been detected by them. This data overwriting can cause chaos in the hardware control state, leading to abnormal system behavior that is difficult to predict and debug, and reducing the reliability and stability of the system. Summary of the Invention

[0003] This disclosure is made in view of the above-mentioned problems. This disclosure provides a method, apparatus, storage medium, and program product for writing data to a register.

[0004] According to a first aspect of this disclosure, a method for writing data to a register is provided, comprising:

[0005] The system obtains the current data transmitted by the target processor to the hardware control register, and obtains the modification permission identifier of the target processor, wherein the modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register; Obtain the target data corresponding to the data bit in the current data, and obtain the first interface control data stored in the hardware control register; Modify the data corresponding to the data bit in the first interface control data to the target data to obtain the latest interface control data.

[0006] Furthermore, according to the method for writing data to a register according to the first aspect of this disclosure, obtaining the modification permission identifier of the target processor includes: Obtain the mask register corresponding to the target processor; Obtain the mask value stored in the mask register; The mask value is used as the modification permission identifier, and the data bits corresponding to the target value in the mask value are the data bits indicated by the modification permission identifier.

[0007] Furthermore, the method for writing data to a register according to the first aspect of this disclosure also includes: During the initialization phase of the operating system that manages the target processor, the modification permission identifier is configured for the target processor by the running main processor.

[0008] Furthermore, according to the method for writing data to a register according to the first aspect of this disclosure, obtaining the current data that the target processor needs to write to the hardware control register includes: The target processor reads the second interface control data stored in the hardware control register. In the memory of the target processor, the data corresponding to the data bit in the second interface control data is modified to the target data to obtain the current data.

[0009] Furthermore, according to the method for writing data to a register according to the first aspect of this disclosure, obtaining the current data that the target processor needs to write to the hardware control register includes: Randomly generate original data with the same number of bits as the hardware control register; The data corresponding to the data bit in the original data is modified to the target data to obtain the current data.

[0010] Furthermore, the method for writing data to a register according to the first aspect of this disclosure also includes: While reading the second interface control data stored in the hardware control register through the target processor, the second interface control data stored in the hardware control register is also read through the remaining processor, which is any processor other than the target processor that controls the hardware control register; Obtain the modification permission identifier of the remaining processor, which is used to indicate the target data bit that the remaining processor has the right to modify in the hardware control register; In the memory of the remaining processor, modify the data in the second interface control data corresponding to the target data bit to obtain the desired write data; If it is detected that the remaining processor is transmitting the desired write data to the hardware control register, the data corresponding to the target data bit stored in the hardware control register is modified to the desired write data.

[0011] According to a second aspect of this disclosure, an apparatus for writing data to a register is provided, comprising: The first acquisition module is used to acquire the current data transmitted by the target processor to the hardware control register, and to acquire the modification permission identifier of the target processor, wherein the modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register; The second acquisition module is used to acquire the target data corresponding to the data bit in the current data, and to acquire the first interface control data stored in the hardware control register; The modification module is used to modify the data corresponding to the data bit in the first interface control data to the target data, thereby obtaining the latest interface control data.

[0012] According to a third aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, the processor executing the computer program to implement the steps of the method described in the first aspect.

[0013] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program / instructions stored thereon that, when executed by a processor, implements the steps of the method described in the first aspect.

[0014] According to a fifth aspect of this disclosure, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the steps of the method described in the first aspect.

[0015] As will be described in detail below, in the method for writing data to a register according to an embodiment of this disclosure, the target processor is configured with a modification permission identifier. This modification permission identifier is used to indicate the data bits in the hardware control register that the target processor has the right to modify. Thus, when the target processor writes data to the hardware control register, it can only modify the data stored in the data bits indicated by the modification permission identifier, and cannot modify the data stored in other data bits of the hardware control register. This effectively avoids one processor overwriting data written to the hardware control register by other processors, solving the problem of value overwriting that occurs during multi-processor write operations in related technologies. This allows multiple processors to better control the modification of the same register during program execution. Furthermore, when the solution of this disclosure is applied to a printing device, it can effectively reduce unpredictable problems caused by register value issues during the overall operation of the printing device.

[0016] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0017] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 This is a schematic diagram of multiprocessor reading and writing data registers in related technologies.

[0019] Figure 2 This is a flowchart illustrating a method for writing data to a register according to an embodiment of the present disclosure.

[0020] Figure 3 This is a schematic diagram illustrating the application of a multiprocessor to read and write data registers according to an embodiment of this disclosure.

[0021] Figure 4 This is a schematic diagram of the structure of a device for writing data to a register according to an embodiment of the present disclosure.

[0022] Figure 5 This is a hardware block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0023] Figure 6 This is a schematic diagram illustrating a computer program product according to an embodiment of the present disclosure. Detailed Implementation

[0024] The technical methods of the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings.

[0025] The printer controller integrates three independent CPUs: CPUA runs Linux and handles USB, network, and print data; CPUB controls the printing, motor, and sensor operations; and CPUC controls the scanning motor and sensor operations. Each of the three processors controls different external devices through the controller chip's I / O ports.

[0026] To save on hardware control register usage during chip design, I / O ports with similar functions are grouped together so that a single hardware control register can control this group of I / O ports. Typically, each I / O interface is controlled by one or two data bits in the hardware control register. For example, using two data bits, when both data bits are 11, the corresponding I / O interface level is pulled high, and the I / O interface is turned on; when both data bits are 00, the corresponding I / O interface level is pulled low, and the I / O interface is turned off.

[0027] In different projects, when arranging I / O, the functions of a set of I / O ports are assigned to different CPUs. For example, I / O1 is assigned to CPUA for USB plug-in identification input, I / O2 to CPUB for controlling the power supply of the printer motor, and I / O3 to CPUC for controlling the scanner home sensor. All three CPUs then need to access the same hardware control register for this set of I / O ports simultaneously.

[0028] In related technologies, register read / write schemes suffer from the drawback that, when multiple CPUs control the same hardware control register, a value written by one CPU can be overwritten by values ​​written by other CPUs. Please refer to... Figure 1 , Figure 1 This involves adopting a multi-CPU register read / write scheme from relevant technologies.

[0029] like Figure 1 As shown, the initial value of the 16-bit DATA register is 0x1234. Three unrelated CPUs, CPUA, CPUB, and CPUC, simultaneously write values ​​to the DATA register. At time 1, CPUA, CPUB, and CPUC simultaneously read the initial value 0x1234 from the DATA register and store it in their respective memory locations. At time 2, CPUA modifies the lower four bits (0x4) to 0xf, leaving the other bits unchanged, and finally writes 0x123f into the DATA register.

[0030] Due to the characteristics of registers, CPUB cannot write a value simultaneously with CPUA during time2. It can only perform the write operation immediately afterward during time3. At this time, the value of the DATA register stored in CPUB's memory is 0x1234. However, after CPUA finishes writing its value, the value in the DATA register has already been updated to 0x123f. Therefore, when CPUB writes 0x12f4 to the DATA register, the original 0x123f in the DATA register will be overwritten with 0x12f4. The same applies to CPUC. CPUC originally stored a value of 0x1234 in the DATA register. Writing 0xff34 to it will overwrite the values ​​written by CPUA and CPUB. Ultimately, the value in the DATA register will be 0xff34, instead of the expected 0xffff.

[0031] To alleviate the technical problems existing in related technologies, embodiments of this disclosure provide a method, apparatus, device, storage medium, and computer program product for writing data to a register.

[0032] To facilitate understanding of this embodiment, a method for writing data to a register disclosed in this disclosure will first be described in detail. See [link to relevant documentation]. Figure 2 The diagram shows a flowchart of a method for writing data to a register according to an embodiment of this disclosure. The method includes the following steps: Step 201: Obtain the current data transmitted by the target processor to the hardware control register, and obtain the modification permission identifier of the target processor. The modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register.

[0033] It should be understood that the number of bits in the current data is the same as the number of bits in the hardware control register. For example, if the hardware control register is a 16-bit register, then the current data is also 16 bits. The hardware control registers here include, but are not limited to, the DATA register and the direction (DIR) register.

[0034] In this embodiment, there is no order in which the current data and the modification permission identifier are obtained. The current data can be obtained first and then the modification permission identifier can be obtained, or the modification permission identifier can be obtained first and then the data can be obtained, or the current data and the modification permission identifier can be obtained simultaneously.

[0035] In this embodiment, the target processor can be any one of multiple processors. These multiple processors refer to processors corresponding to a set of I / O interfaces, whose functions are allocated to different processors. It should be understood that, based on the characteristics of registers, multiple processors can read the hardware control register simultaneously, but cannot write data to the hardware control register simultaneously.

[0036] In this embodiment, a target processor can write data to multiple hardware control registers, and the I / O interfaces controlled by these multiple hardware control registers belong to different I / O interface groups. The modification permission flag of the target processor can be applied to these multiple hardware control registers, that is, the data bits that the target processor has the right to modify in multiple hardware control registers are the same, for example, the flag bits that have the right to modify are all the lower four bits. This can reduce the setting of modification permission flags for the target processor and reduce resource consumption.

[0037] Alternatively, a modification permission flag can be set for each hardware control register of the target processor. In this case, when obtaining the modification permission flag of the target processor, it is necessary to combine the target processor and the hardware control register to be written to obtain the modification permission flag.

[0038] In this embodiment, a modification permission identifier for the target processor is pre-configured. Different target processors have different modification permission identifiers, meaning that different target processors have completely different data bits that they are allowed to modify in the hardware controller.

[0039] For example, the modification permission identifier of target processor 1 indicates that target processor 1 has the right to modify the lower four bits in the hardware controller, the modification permission identifier of target processor 2 indicates that target processor 2 has the right to modify the middle four bits in the hardware controller, and the modification permission identifier of target processor 3 indicates that target processor 3 has the right to modify the higher four bits in the hardware controller.

[0040] In one embodiment, a mask register can be used to set the modification permission flag for the target processor. The mask register stores a mask value, which serves as the modification permission flag for the target register. The data bits corresponding to the target value in the mask are the data bits indicated by the modification permission flag.

[0041] In this embodiment, each target processor corresponds to a unique mask register. When setting the mask value in the mask register, the data bits in the mask register can be divided into two parts. The first part is the same as the data bits that the target processor has the right to modify in the hardware control register, and the second part consists of the data bits in the mask register excluding the first part. By setting different values ​​for these two parts of the data bits in the mask register, the indication of the data bits that the target processor has the right to modify in the hardware control register can be achieved.

[0042] In one embodiment, the mask register multiplexes a data register or a direction register, and the mask register has the same number of bits as the hardware control register.

[0043] For an example, please refer to Table 1 for the mask values ​​stored in the 16-bit mask register: Table 1

[0044] When the position is 1, the value of the data bit in the corresponding hardware control register will not be modified; when the position is 0, the value of the data bit in the corresponding hardware control register can be modified.

[0045] In this example, the target value is 0, and the data bits corresponding to 0 in the mask value are the high eight bits. Therefore, the mask value indicates that the target register has the right to modify the high eight bits in the hardware control register.

[0046] In one embodiment, during the initialization phase of the operating system managing the target processor, the modification permission identifier is configured for the target processor by the started main processor, that is, a mask register storing the mask value is configured for the target processor.

[0047] During the initialization phase, even if there are multiple processors in the chip, only the main processor runs; the other processors wait to be woken up by the main processor after the initialization phase. The main processor can be one of multiple processors. During the initialization phase, the running main processor configures the mask register before starting the other processors. This avoids the problem of write operations from multiple processors simultaneously operating the mask register being overwritten. Optionally, this initialization phase includes, but is not limited to, the boot phase.

[0048] In one embodiment, the current data transmitted by the target processor to the hardware control register originates from an update of the second interface control data stored in the hardware control register.

[0049] Specifically, obtaining the current data that the target processor needs to write to the hardware control register can include the following steps: The target processor reads the second interface control data stored in the hardware control register. In the target processor's memory, the data corresponding to the data bit in the second interface control data is modified to the target data to obtain the current data.

[0050] It should be understood that the second interface control data here can be either the initial data in the hardware control register or data written to the hardware control register by other processors. Taking the second interface control data as the initial data as an example, the initial data read is 0x1234. The target processor modifies the lower four bits of the initial data (0x4) to 0xf, leaving the other bits unchanged, to obtain the current data 0x123f.

[0051] This embodiment obtains the current data by modifying the second interface control data read from the hardware control register. This process is consistent with the process of reading and writing registers in related technologies. By obtaining the current data through this process, this solution is compatible with the process steps of related technologies.

[0052] In one embodiment, the remaining processors can simultaneously read the second interface control data stored in the hardware control register with the target processor, and modify the second interface control data in memory as needed so as to write it into the hardware control register.

[0053] The remaining processors are any processor other than the target processor that controls the hardware control registers.

[0054] Specifically, while reading the second interface control data stored in the hardware control register through the target processor, the remaining processor also reads the second interface control data stored in the hardware control register; obtains the modification permission identifier of the remaining processor, which indicates the target data bit that the remaining processor has the right to modify in the hardware control register; modifies the data corresponding to the target data bit in the second interface control data in the memory of the remaining processor to obtain the expected write data; and when it is detected that the remaining processor is transmitting the expected write data to the hardware control register, modifies the data corresponding to the target data bit stored in the hardware control register to the expected write data.

[0055] In this embodiment, multiple processors simultaneously read the second interface control data in the hardware control register. When multiple processors write data to the hardware control register one after another, the modification permission identifier corresponding to each processor specifies the data bit that the processor can write data to the register. This can prevent one processor from overwriting the data written to the hardware control register by other processors when writing data to the hardware control register.

[0056] In one embodiment, the current data transferred by the target processor to the hardware control register is derived from an update of the randomly generated original data.

[0057] Specifically, obtaining the current data that the target processor needs to write to the hardware control register can include the following steps: Randomly generate raw data with the same number of bits as the hardware control register; Modify the data corresponding to the data bits in the original data to the target data to obtain the current data.

[0058] This embodiment obtains the current data by randomly generating original data with the same number of bits as the hardware control register and modifying the original data, which can save the step of reading the hardware control register.

[0059] Step 202: Obtain the target data corresponding to the data bit in the current data, and obtain the first interface control data stored in the hardware control register.

[0060] The first interface control data here can be the same as the aforementioned second interface control data. This indicates that after the target processor reads the second interface control data, no other processor has written data to the hardware control register before transmitting the current data to it. Alternatively, the first interface control data can be different from the aforementioned second interface control data. This indicates that after the target processor reads the second interface control data, but before transmitting the current data to it, another processor has written data to the hardware control register, thus updating the second interface control data in the hardware control register to the first interface control data.

[0061] Step 203: Modify the data corresponding to the data bit in the first interface control data to the target data to obtain the latest interface control data.

[0062] In the solution provided in this embodiment, the target processor is configured with a modification permission identifier. This identifier indicates the data bits in the hardware control register that the target processor has the right to modify. Thus, when the target processor writes data to the hardware control register, it can only modify the data stored in the data bits indicated by the modification permission identifier, and cannot modify the data stored in other data bits of the hardware control register. This effectively prevents one processor from overwriting data written to the hardware control register by other processors, solving the value overwriting problem that occurs during multi-processor write operations in related technologies. It allows multiple processors to better control the modification of the same register during program execution. Furthermore, when the solution of this disclosure is applied to a printing device, it can effectively reduce unpredictable problems caused by register value issues during the overall operation of the printing device.

[0063] Combination Figure 2 An embodiment of the method for writing data to a register is shown, and the following is given: Figure 3 The specific example shown is writing data to a register, such as Figure 3 As shown, the chip contains three unrelated processors: CPUA, CPUB, and CPUC. During the initialization phase, mask registers are configured for each processor: MASK_A for CPUA, MASK_B for CPUB, and MASK_C for CPUC. Then, at time 1, CPUA, CPUB, and CPUC read the initial data 0x1234 stored in the DATA register and place it into their respective memory locations.

[0064] At time 2, CPUA modifies the lower four bits (0x4) of the initial data read from memory to 0xf, leaving the other bits unchanged, thus obtaining 0x123f. This 0x123f is then transferred to the hardware control register. The hardware control register queries the corresponding MASK_A register for CPUA. MASK_A specifies that CPUA can only modify the lower four bits of the DATA register. Therefore, although the value written at time 2 is 0x123f, only the lowest four bits (f) are actually written. The higher twelve bits remain unchanged regardless of what value CPUA writes. The data stored in the hardware control register is updated from 0x1234 to 0x123f.

[0065] At time 3, CPUB modifies the middle four bits of the initial data read from memory to 'f', leaving the other bits unchanged, resulting in 0x12f4. It then transmits 0x12f4 to the hardware control register. The hardware control register queries the corresponding MASK_B register of CPUB. MASK_B specifies that CPUB can only modify the middle four bits of the DATA register. Therefore, although the value written at time 2 is 0x12f4, only the middle four bits ('f') are actually written. The high eight bits and low four bits remain unchanged regardless of what value CPUB writes. The data stored in the hardware control register is updated from 0x123f to 0x12ff.

[0066] At time 4, the CPUC modifies the high eight bits of the initial data read from memory to 'f', leaving the other bits unchanged, resulting in 0xff34. This 0xff34 is then transferred to the hardware control register. The hardware control register queries the corresponding MASK_C register of the CPUC. MASK_C specifies that the CPUC can only modify the high eight bits of the DATA register. Therefore, although the value written at time 3 is 0xff34, only the high four bits 'f' can actually be written. The eighth bit will not be modified regardless of what value the CPUC writes. The data stored in the hardware control register is updated from 0x12ff to 0xffff.

[0067] In this embodiment, the hardware control register can be implemented using a DATA register or a DIR register. When the DATA register or DIR register is 32 bits, the first 16 bits of the DATA register or DIR register are used as hardware control registers, and the last 16 bits of the DATA register or DIR register are used as MASK registers. MASK_A register, MASK_B register, and MASK_C register can be implemented using the last 16 bits of different DATA registers, or using the last 16 bits of different DIR registers. The first 16 bits of the DATA register or DIR register can be used as hardware control registers.

[0068] In this embodiment, when the DATA register is used to implement the hardware control register, please refer to Tables 2, 3 and 4 for the MASK_A register, MASK_B register and MASK_C register respectively.

[0069] Table 2

[0070] Table 3

[0071] Table 4

[0072] As shown in Tables 2, 3, and 4, the MASK_A register is implemented using the last 16 bits of I / O_DATA_A, and the lower four bits of the MASK_A register are 0, indicating that the CPUA has the right to modify only the lower four bits in the hardware control register. That is, the CPUA only modifies the lower four bits of the DATA register, and the higher twelve bits will not be modified regardless of what value the CPUA writes to the DATA register.

[0073] The MASK_B register is implemented using the last 16 bits of I / O_DATA_B, and the middle four bits of the MASK_B register are 0, indicating that the CPUB has the right to modify only the middle four bits in the hardware control register. That is, the CPUB only modifies the middle four bits of the DATA register; the high eight bits and low four bits will not be modified regardless of what value the CPUB writes to them.

[0074] The MASK_C register is implemented using the last 16 bits of I / O_DATA_C, and the high eight bits of the MASK_C register are 0, indicating that the CPU has the right to modify only the high eight bits in the hardware control register. That is, the CPU only modifies the high eight bits of the DATA register, and the low eight bits will not be modified regardless of what value the CPU writes to them.

[0075] It should be understood that the first 16 bits of I / O_DATA_A, I / O_DATA_B, and I / O_DATA_C can be used as hardware control registers. As an example, using I / O_DATA_A as an example, a diagram illustrating the use of the first 16 bits as a hardware control register is shown in Table 5.

[0076] Table 5

[0077] When using the DIR register to implement the hardware control register, please refer to Tables 6, 7 and 8 for the MASK_A register, MASK_B register and MASK_C register respectively.

[0078] Table 6

[0079] Table 7

[0080] Table 8

[0081] As shown in Tables 6, 7, and 8, the MASK_A register is implemented using the last 16 bits of I / O_DIR_A, and the lower four bits of the MASK_A register are 0, indicating that CPUA has the right to modify the lower four bits of data in the hardware control register. The MASK_B register is implemented using the last 16 bits of I / O_DIR_B, and the middle four bits of the MASK_B register are 0, indicating that CPUB has the right to modify the middle four bits of data in the hardware control register. The MASK_C register is implemented using the last 16 bits of I / O_DIR_C, and the higher eight bits of the MASK_C register are 0, indicating that CPUC has the right to modify the higher eight bits of data in the hardware control register.

[0082] It should be understood that the first 16 bits of I / O_DIR_A, I / O_DIR_B, and I / O_DIR_C can be used as hardware control registers. As an example, using I / O_DIR_A as an example, a diagram illustrating the use of the first 16 bits as a hardware control register is given; please refer to Table 9.

[0083] Table 9

[0084] This disclosure also provides a register read / write apparatus for performing the method of writing data to a register provided in any of the above embodiments. Figure 4 As shown, the device includes: The first acquisition module 41 is used to acquire the current data transmitted by the target processor to the hardware control register, and to acquire the modification permission identifier of the target processor, wherein the modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register; The second acquisition module 42 is used to acquire the target data corresponding to the data bit in the current data, and to acquire the first interface control data stored in the hardware control register; Modification module 43 is used to modify the data corresponding to the data bit in the first interface control data to the target data, thereby obtaining the latest interface control data.

[0085] In some embodiments, the first acquisition module 41 is used for: Obtain the mask register corresponding to the target processor; Obtain the mask value stored in the mask register; The mask value is used as the modification permission identifier, and the data bits corresponding to the target value in the mask value are the data bits indicated by the modification permission identifier.

[0086] In some embodiments, the device is further used for: During the initialization phase of the operating system that manages the target processor, the modification permission identifier is configured for the target processor by the running main processor.

[0087] In some embodiments, the first acquisition module 41 is used for: The target processor reads the second interface control data stored in the hardware control register. In the memory of the target processor, the data corresponding to the data bit in the second interface control data is modified to the target data to obtain the current data.

[0088] In some embodiments, the first acquisition module 41 is used for: Randomly generate original data with the same number of bits as the hardware control register; The data corresponding to the data bit in the original data is modified to the target data to obtain the current data.

[0089] In some embodiments, the device is further used for: While reading the second interface control data stored in the hardware control register through the target processor, the second interface control data stored in the hardware control register is also read through the remaining processor, which is any processor other than the target processor that controls the hardware control register; Obtain the modification permission identifier of the remaining processor, which is used to indicate the target data bit that the remaining processor has the right to modify in the hardware control register; In the memory of the remaining processor, modify the data in the second interface control data corresponding to the target data bit to obtain the desired write data; If it is detected that the remaining processor is transmitting the desired write data to the hardware control register, the data corresponding to the target data bit stored in the hardware control register is modified to the desired write data.

[0090] The register read / write device provided in this disclosure and the method for writing data to a register provided in this disclosure are based on the same inventive concept and have the same beneficial effects as the methods they employ, operate, or implement.

[0091] This disclosure also provides an electronic device for performing the above-described method of writing data to a register. Please refer to... Figure 5 It illustrates a schematic diagram of an electronic device provided by some embodiments of this disclosure. For example... Figure 5As shown, the electronic device 5 includes: a processor 500, a memory 501, a bus 502, and a communication interface 503. The processor 500, the communication interface 503, and the memory 501 are connected via the bus 502. The memory 501 stores a computer program that can run on the processor 500. When the processor 500 runs the computer program, it executes the method for writing data to a register provided in any of the foregoing embodiments of this disclosure.

[0092] The memory 501 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this device network element and at least one other network element is achieved through at least one communication interface 503 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc.

[0093] Bus 502 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. Memory 501 is used to store programs. After receiving an execution instruction, the processor 500 executes the program. The method for writing data to registers disclosed in any of the foregoing embodiments of this disclosure can be applied to the processor 500, or implemented by the processor 500.

[0094] The processor 500 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 500 or by instructions in software form. The processor 500 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 501. The processor 500 reads the information in memory 501 and, in conjunction with its hardware, completes the steps of the above method.

[0095] The electronic device provided in this disclosure and the method for writing data to a register provided in this disclosure are based on the same inventive concept and have the same beneficial effects as the methods they employ, operate, or implement.

[0096] This disclosure also provides a computer-readable storage medium corresponding to the method of writing data to a register provided in the foregoing embodiments. The computer-readable storage medium is an optical disc, on which a computer program (i.e., a computer program product) is stored. When the computer program is run by a processor, it executes the method of writing data to a register provided in any of the foregoing embodiments.

[0097] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0098] The computer-readable storage medium provided in the above embodiments of this disclosure and the method for writing data to a register provided in the embodiments of this disclosure are based on the same inventive concept and have the same beneficial effects as the methods used, run or implemented by the applications stored therein.

[0099] This disclosure also provides a computer program product; please refer to [link / reference]. Figure 6 The computer program product 600 carries program code, namely computer program 601. The instructions included in the computer program 601 can be used to execute the steps of the method of writing data to the register as described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0100] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0101] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0102] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0103] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0104] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0105] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0106] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0107] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for writing data to a register, characterized in that, include: The system obtains the current data transmitted by the target processor to the hardware control register, and obtains the modification permission identifier of the target processor, wherein the modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register; Obtain the target data corresponding to the data bit in the current data, and obtain the first interface control data stored in the hardware control register; Modify the data corresponding to the data bit in the first interface control data to the target data to obtain the latest interface control data.

2. The method according to claim 1, characterized in that, Obtaining the modification permission identifier of the target processor includes: Obtain the mask register corresponding to the target processor; Obtain the mask value stored in the mask register; The mask value is used as the modification permission identifier, and the data bits corresponding to the target value in the mask value are the data bits indicated by the modification permission identifier.

3. The method according to claim 1 or 2, characterized in that, Also includes: During the initialization phase of the operating system that manages the target processor, the modification permission identifier is configured for the target processor by the running main processor.

4. The method according to claim 1, characterized in that, Obtain the current data that the target processor needs to write to the hardware control registers, including: The target processor reads the second interface control data stored in the hardware control register. In the memory of the target processor, the data corresponding to the data bit in the second interface control data is modified to the target data to obtain the current data.

5. The method according to claim 1, characterized in that, Obtain the current data that the target processor needs to write to the hardware control registers, including: Randomly generate original data with the same number of bits as the hardware control register; The data corresponding to the data bit in the original data is modified to the target data to obtain the current data.

6. The method according to claim 4, characterized in that, Also includes: While reading the second interface control data stored in the hardware control register through the target processor, the second interface control data stored in the hardware control register is also read through the remaining processor, which is any processor other than the target processor that controls the hardware control register; Obtain the modification permission identifier of the remaining processor, which is used to indicate the target data bit that the remaining processor has the right to modify in the hardware control register; In the memory of the remaining processor, modify the data in the second interface control data corresponding to the target data bit to obtain the desired write data; If it is detected that the remaining processor is transmitting the desired write data to the hardware control register, the data corresponding to the target data bit stored in the hardware control register is modified to the desired write data.

7. An apparatus for writing data to a register, characterized in that, include: The first acquisition module is used to acquire the current data transmitted by the target processor to the hardware control register, and to acquire the modification permission identifier of the target processor, wherein the modification permission identifier is used to indicate the data bits that the target processor has the right to modify in the hardware control register; The second acquisition module is used to acquire the target data corresponding to the data bit in the current data, and to acquire the first interface control data stored in the hardware control register; The modification module is used to modify the data corresponding to the data bit in the first interface control data to the target data, thereby obtaining the latest interface control data.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-6.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-6.

Images