Detection method, device and equipment of PCIe device and storage medium

Abstract

This disclosure provides a method, apparatus, device, and storage medium for detecting PCIe devices, relating to the field of computer technology, particularly to the fields of chips, cloud computing, and autonomous driving. Specifically, the host computer software communicates with the CPU of a CPU system, which includes a slot for at least one PCIe device. During implementation, the CPU system can receive detection commands sent by the host computer software, the commands including preset detection items; and the PCIe device is detected based on these preset detection items.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of chips, cloud computing, and autonomous driving. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect processors to external devices. As PCIe technology continues to evolve towards higher speeds, anomalies are becoming increasingly prominent. Different PCIe devices across various industries often exhibit implementation differences, requiring verification and validation to ensure long-term stable operation under workload and environmental stress, thereby meeting product quality and reliability requirements. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for detecting PCIe devices.

[0004] According to one aspect of this disclosure, a method for detecting a PCIe device is provided, wherein host computer software communicates with the CPU of a CPU system, the CPU system including a slot for at least one PCIe device, the method comprising: Receive detection instructions sent by host computer software, wherein the detection instructions include preset detection items; The PCIe device is tested based on preset test items.

[0005] According to another aspect of this disclosure, a PCIe device verification apparatus is provided, comprising: The host computer software is used to send detection instructions to the CPU of the CPU system; the detection instructions include preset detection items. A CPU system is used to detect the PCIe device in the slot based on the preset detection items. The CPU system includes a slot for at least one PCIe device to be plugged in, and a memory unit and a hard disk unit that are communicatively connected to the CPU. The memory unit provides high-speed storage space for the CPU during operation; The hard disk unit is used to store the operating system.

[0006] According to another aspect of this disclosure, a detection device for a PCIe device is provided, wherein host computer software communicates with the CPU of a CPU system, the CPU system including a slot for at least one PCIe device, the device comprising: The receiving module is used to receive detection instructions sent by the host computer software, the detection instructions including preset detection items; The testing module is used to test the PCIe device based on preset test items.

[0007] According to another aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and The memory is communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the methods described in the present disclosure.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform any of the methods according to embodiments of this disclosure.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods according to embodiments of this disclosure.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic flowchart of a PCIe device detection method according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of a PCIe device testing device according to another embodiment of the present disclosure; Figure 3 This is another schematic flowchart of a PCIe device detection method according to an embodiment of the present disclosure; Figure 4 This is another schematic flowchart of a PCIe device detection method according to an embodiment of the present disclosure; Figure 5 This is another schematic flowchart of a PCIe device detection method according to an embodiment of the present disclosure; Figure 6 This is another schematic flowchart of a PCIe device detection method according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of a PCIe device verification apparatus according to an embodiment of the present disclosure; Figure 8This is a schematic diagram of the structure of a detection device for a PCIe device according to an embodiment of the present disclosure; Figure 9 This is a block diagram of an electronic device used to implement the PCIe device detection method of the embodiments of this disclosure. Detailed Implementation

[0012] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0013] The terms “first,” “second,” etc., used in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0014] It should be noted that, unless it is explicitly stated that there is a sequential order of execution between different operations, or that there is a sequential order of execution between different operations in terms of technical implementation, the execution order between multiple operations may not be significant, and multiple operations may be executed simultaneously.

[0015] PCIe, as a high-speed serial expansion bus, plays a critical data channel role in autonomous driving domain controllers. With the evolution of speeds towards Gen (Generation) 4 / Gen5, the verification of signal integrity and protocol consistency has become significantly more challenging. Due to differences in PCIe PHY (Physical Layer) / MACMedia Access Control (MAC) implementations among different vendors, and given the extreme environmental stresses and functional safety requirements of automotive applications, it is essential to verify PCIe devices through various means to ensure their reliability throughout their entire lifecycle, thereby meeting the safety requirements of autonomous driving systems.

[0016] In view of this, embodiments of this disclosure provide a method for detecting PCIe devices. This method is applicable to devices connected to a CPU (Graphics Processing Unit) system via PCIe devices. The CPU system can be controlled by host computer software to verify the PCIe device. Therefore, embodiments of this disclosure propose a method for detecting PCIe devices, which can be applied to the aforementioned host computer software. Alternatively, the host computer software can send corresponding verification commands to the CPU system, allowing the CPU system to complete the verification of the PCIe device and obtain the verification result. When multiple detection items of the PCIe device need to be verified, the verification results of some detection items can be determined by the CPU system, while the verification results of others can be determined by the host computer software.

[0017] In this disclosure, the host computer software communicates with the CPU of a CPU system, which includes slots for at least one PCIe device. For example... Figure 1 The diagram shown is a flowchart of a PCIe device testing method, including the following: S101, Receive a detection command sent by the host computer software, the detection command includes preset detection items; During implementation, the PCIe devices connected to the CPU system can be power-on initialized first. Power-on initialization refers to the startup sequence of PCIe devices from a power-off state to normal operation.

[0018] Then the host computer software sends the detection command to the CPU of the CPU system, and the CPU executes the detection command.

[0019] S202, perform testing on PCIe devices based on preset test items.

[0020] The preset test items are a set of test items predefined according to the device type and application scenario, including at least one of the following: test steps, expected results and judgment criteria.

[0021] This disclosure discloses the verification of PCIe devices, which can be for PCIe devices in the computing units of autonomous vehicles, and can be used for verification during product development, as well as for incoming quality control (IQC) inspection, factory verification, or verification of faulty parts returned for repair. It can also be used for the verification of PCIe devices used as storage devices.

[0022] In this embodiment, the CPU system integrates a slot, enabling pluggable support for PCIe devices and facilitating the detection of different PCIe devices. During the detection process, the host computer software can send detection commands to operate the CPU system and complete the detection of the PCIe devices. This detection method allows the host computer software to flexibly detect PCIe devices according to requirements, and at the software level, it can achieve a unified control architecture from the underlying signal layer to the high-level business logic, eliminating the need for separate modules for different detection layers in the detection of PCIe devices.

[0023] It can verify the PCIe devices connected to the CPU system after power-on initialization. During implementation, the verification of PCIe devices can be tailored to specific scenario requirements, especially those specific to autonomous driving.

[0024] In order to better enable the verification of PCIe devices in the field of autonomous driving, in some embodiments, the CPU system is connected to slots of various types, including slots that support computing units and slots that support storage units.

[0025] In the field of autonomous driving, two main categories of PCIe devices are involved. One category is computing units, used for autonomous driving computation. For this, embodiments of this disclosure provide CEM slots (PCI Express Card Electromechanical) and / or MXM slots (Mobile PCI Express Module) to support PCIe devices serving as computing units. The other category is storage units, used to store autonomous driving data. For this, embodiments of this disclosure provide at least one slot, including M.2 (Next Generation Form Factor), U.2 (Unified Form Factor), or E1.s (Enterprise & Data Center Solid State Drive Form Factor E1.S) slots, to serve as PCIe devices serving as storage devices. Embodiments of this disclosure also provide external expansion interfaces to support the verification of PCIe devices using miniSAS (mini Serial Attached SCSI) slots. MiniSAS slots can support both computing units and storage units.

[0026] For example, the structure of the PCIe device verification device 200 is as follows: Figure 2As shown, the device includes a CPU 101, a PCH (Platform Controller Hub) 102, host computer software 103, a BMC (Baseboard Management Controller) 104, a debugger 105, a memory unit 106, a hard disk unit 107, a Flash memory 108, and six slot types of PCIe devices to be verified. Figure 2 As shown, it integrates: CEM slot 109, MXM slot 110, miniSAS interface 111, M.2 slot 112, U.2 slot 113 and E1.s slot 114.

[0027] Among them, CPU 101, as the core processing unit, communicates with PCH 102 through the DMI (Direct Media Interface) bus.

[0028] The PCH 102 is a device required for the normal operation of the CPU. It is responsible for managing low-speed peripherals and I / O interfaces, connecting to the flash memory 108, and connecting to the debugger 105 via the USB (Universal Serial Bus) interface. The PCH plays a core role in I / O management, peripheral bridging, and function expansion, and is equivalent to the "I / O central nervous system" of the hardware system.

[0029] The host computer software 103 is the control center of the entire verification platform. It connects to the debugger 105 via USB for low-level hardware debugging and firmware-level operations. The host computer software communicates with the BMC 104 via network or serial communication, enabling remote management of PCIe devices. This includes issuing test commands to PCIe devices, real-time monitoring, data collection and analysis, and generating test reports. Alternatively, the CPU can be controlled by the host computer software to perform the corresponding tests, obtain the test results, store them on the hard disk unit 107, and then return them to the host computer software.

[0030] The BMC 104 is a dedicated embedded management chip, independent of the CPU 101 and operating system, used in servers, industrial computers, and other devices. As an independent management chip, the BMC 104 connects to the CPU 101 via PCIe x1 and can monitor hardware status based on out-of-band management functions. It supports communication with the host computer software 103 via serial or network communication interfaces. Its core function is to enable the host computer software to remotely monitor, manage, and troubleshoot PCIe devices in any state. The CPU system log can be obtained through the BMC.

[0031] The debugger 105 connects to the PCH 102 via USB, providing a communication channel between the host computer software and the CPU system.

[0032] The memory unit 106 provides high-speed storage space for the CPU during operation; the hard disk unit 107 is used to store the operating system, testing tools, and historical data.

[0033] Flash memory 108 is used to store UEFI (Unified Extensible Firmware Interface) / BIOS (Basic Input / Output System) files.

[0034] In this embodiment, the CPU system includes at least: a CPU 101, a PCH 102, a debugger 105, a memory unit 106, a hard disk unit 107, a flash memory 108, and a slot for a PCIe device. When connection stability testing of the PCIe device is required, the CPU system also includes a BMC 104 to synchronize relevant information of the PCIe device to the host computer software 103, so that the host computer software can analyze and obtain the verification results.

[0035] Among them, such as Figure 2 As shown, the CEM slot (PCIe x16) can be used to test standard full-height / half-height expansion cards; the MXM slot (PCIe x16) can be used to test mobile form factor graphics card modules; the m.2 slot (PCIe x4) is used to test compact NVMe SSDs (Non-Volatile Memory Express Solid State Drives); the U.2 slot (PCIe x4) is used to test enterprise-grade 2.5-inch NVMe solid state drives; the E1.5 slot (PCIe x4) is used to test specific form factor enterprise-grade modules; and the miniSAS interface (PCIe x16) is used to connect external high-speed storage arrays, thus forming a relatively complete PCIe device verification platform suitable for autonomous driving systems.

[0036] The PCIe device refers to a device located in one or more of the following slots: CEM slot, MXM slot, miniSAS interface, m.2 slot, U.2 slot, and E1.s slot. Each device in the CEM slot, MXM slot, miniSAS interface, m.2 slot, U.2 slot, and E1.s slot can be used as a PCIe device for testing. Alternatively, multiple devices in multiple slots can be used as PCIe devices for verification, depending on the requirements of the test scenario.

[0037] In this embodiment of the disclosure, the total number of PCIe lanes supported by each slot is marked in the figure. In practice, a larger number of PCIe lanes can be set for the corresponding slot to achieve backward compatibility. For example, a PCIe x16 (i.e., 16 lanes) slot is compatible with backward x8, x4, x2, and x1 devices.

[0038] In this embodiment, the CPU system can simultaneously connect to computing unit slots and storage device slots, enabling unified verification of heterogeneous computing devices and high-speed storage devices. This eliminates the need to build dedicated test platforms for different types of PCIe devices, significantly reducing costs. Furthermore, based on the universality of the PCIe bus, the CPU can adapt to devices with different bandwidth requirements through flexible lane configuration (x1 / x4 / x16), achieving hierarchical connection of high-end computing cards (x16) and storage devices (x4), maximizing the utilization of the CPU's PCIe channel resources and reducing channel waste or bandwidth bottlenecks.

[0039] In some embodiments, preset tests for PCIe devices include functional tests and / or physical layer tests.

[0040] Among them, functional testing is used to verify whether the logical functions of PCIe devices can be correctly implemented. The testing scope includes, but is not limited to, at least one of the following: whether the PCIe device can be correctly enumerated, whether the configuration is correct, whether the driver is normal, and whether the performance is normal.

[0041] Physical layer testing is used to evaluate the signal quality of PCIe devices, such as link quality and connection stability. This includes, but is not limited to, at least one of the following: whether the device can be initialized normally, whether the signal connection quality meets requirements, and whether the connection stability meets requirements.

[0042] In this embodiment, multiple defects can be fully covered and accurately located through functional testing and physical layer testing. Single-layer testing has blind spots; for example, pure functional testing may miss occasional errors caused by insufficient signal margin, while pure physical layer testing cannot detect virtualization function implementation defects. Functional testing can detect whether the logical functions of PCIe devices conform to specifications, while physical layer testing is used to quantify signal quality. The two work together to achieve complete detection of defects and underlying hardware faults.

[0043] In practice, functional testing may specifically include at least one of the following: 1) Device configuration detection, used to check whether the configuration parameters of the PCIe device match the expected configuration; 2) Driver detection, used to detect whether the drivers of PCIe devices can be used normally; 3) Performance testing, used to stress test PCIe devices; 4) Autonomous driving service testing, used to test the PCIe device's ability to support specific autonomous driving services.

[0044] The support capabilities for autonomous driving services can be set according to specific business needs. For example, the support capabilities can be ultimately determined as either supported or not supported, or they can be divided into specific supported services and specific unsupported services. Different support levels can also be defined for supported services. In specific implementation, these settings can be configured according to actual needs, and this disclosure does not limit this aspect.

[0045] In summary, device configuration testing, driver testing, and performance testing can be achieved through the PCIe standard protocol, applicable to all PCIe device types. Autonomous driving business testing requires customization based on specific device types; therefore, autonomous driving business testing also needs to test GPU devices and solid-state drives.

[0046] In this embodiment, device configuration is the foundation for system identification and management of hardware. Incorrect configuration can prevent PCIe devices from booting or cause system instability. Therefore, device configuration detection can quickly identify problems such as incorrect device identity, resource conflicts, or abnormal configuration information, reducing the likelihood of PCIe devices being unrecognized or causing compatibility issues due to mismatched basic information. Driver-level problems can cause PCIe devices to malfunction or have limited performance. Driver detection can reduce PCIe device failures and crashes caused by driver incompatibility or functional defects. Performance detection can quantify the true performance level of PCIe devices, ensuring they meet business requirements and minimizing the impact of performance issues on overall efficiency. Furthermore, autonomous driving services have extremely high requirements for real-time performance and reliability, and the special data patterns in this business logic may trigger potential defects. Therefore, this embodiment provides autonomous driving service detection, which can promptly identify business-layer problems that general testing cannot cover, enabling PCIe devices to operate stably for extended periods in mission-critical scenarios.

[0047] In some embodiments, the device configuration detection mentioned in 1) above can be specifically implemented as follows: detecting whether the PCIe device enumeration is successful, and detecting whether the PCIe device's identity information and configuration space are correct. If any of the above is found to be incorrect, the device configuration detection result is recorded as incorrect device configuration; otherwise, the detection result is recorded as accurate device configuration.

[0048] If at least one of the following occurs: PCIe device enumeration fails, identity information verification fails, or PCIe device configuration space is incorrect, then the device configuration is recorded as incorrect.

[0049] In practice, after the PCIe device is powered on and initialized, the CPU system will automatically complete the device enumeration. The host computer software or the CPU can monitor the enumeration status through the BMC, obtain the enumeration results of the CPU system, and determine whether the enumeration was successful.

[0050] During implementation, the success of the enumeration can be determined based on any one of the following methods or a combination of them: A. To determine whether the vendor identifier enumeration was successful, the following can be implemented: The link status read request is routed from the host computer software → USB → debugger → USB → PCH → DMI → CPU, so that the CPU can obtain the Vendor ID value in the device configuration space. If the Vendor ID value in the configuration space is equal to the preset vendor identifier, the enumeration is considered successful, the enumeration success flag is written to the memory unit, and it is also synchronously recorded to the hard disk unit. If the value is not equal to the preset vendor identifier, the enumeration is considered unsuccessful, the enumeration failure flag is written to the memory unit, and the verification result of whether the enumeration was successful can be synchronously recorded to the hard disk unit.

[0051] B, to determine whether the link training state has been successfully established, can be implemented as follows: The link status read request is routed from the host computer software → USB → debugger → USB → PCH → DMI → CPU to obtain the link status information used to indicate the link connection status. If the link status indicates that the link training has entered an active state, such as L0, then the link training status enumeration is considered successful. The BMC updates the successful enumeration status to the memory and disk logs and reports it to the host computer. Otherwise, the enumeration of the link training status is recorded as a failure.

[0052] C, Configure the access response judgment, which can be implemented as follows: After the host computer software triggers a device configuration access request, the request is sent to the PCIe device via USB → debugger → PCH. If the PCIe device successfully returns a completion packet, meaning it has responded to the configuration request, the enumeration of the configuration access response is confirmed to be successful. The successful enumeration result is recorded in the memory and hard disk units, completing the verification process. If the PCIe device does not return a completion packet, meaning it has not responded to the configuration request, it is determined that its configuration access response enumeration has failed.

[0053] In some embodiments, the verification of the PCIe device's identity information can be implemented as follows: the host computer software sends a Device ID read command to the debugger via the USB interface, and the debugger forwards it to the CPU via the DMI-1 bus; the CPU initiates a configuration space read transaction to the PCIe device and extracts the Device ID value from the configuration space; the BMC monitors the configuration access completion message returned by the PCH through the internal bus, captures the actual Device ID, and automatically compares it with the expected Device ID (imported from the manufacturer's specification or device manual) pre-stored in the memory unit; if the actual Device ID matches the expected Device ID, the PCIe device's identity information verification is successful; the BMC writes the successful authentication status to the hard disk unit and notifies the host computer software; if the actual Device ID does not match the expected Device ID, the PCIe device's identity information verification is unsuccessful, triggering error log recording.

[0054] Understandably, for the preset detection items, the host computer software can trigger the corresponding verification command (such as the identity information verification request described above). This request is then sent to the CPU via USB → debugger → PCH, and then executed. During execution, the execution result can be sent to the host computer software for final verification result analysis via BMC, or the CPU can complete the verification result analysis and return the analysis result to the host computer software via BMC.

[0055] In some embodiments, the key registers and key fields in the PCIe device configuration space are verified. Specifically, the host computer software initiates a key register and key field read transaction to the PCIe device through the CPU; the key fields in the configuration space are compared with the expected fields. If they are consistent, the configuration space is correct; if they are inconsistent, the configuration space is determined to be incorrect.

[0056] In some embodiments, the driver detection mentioned in 2) above can be determined by querying the device's functional status information (such as firmware version, clock speed, voltage, current, temperature, error count, etc.) through PCIe device manufacturer-specific diagnostic tools or operating system standard interfaces.

[0057] The criteria for judgment are as follows: if the above hardware and software status information can be successfully obtained and there are no fatal error flags (such as overheating, power failure, etc.), then the driver is judged to be loaded and working normally; if the query fails (the tool returns "device not found" or timed out) or returns an abnormal value, then the driver is judged to be abnormal or not loaded.

[0058] In some embodiments, the performance testing mentioned in 3) above may include stress testing. For example, if the PCIe device is a hard drive, direct write stress testing can be performed using commonly used tools such as fio (Flexible I / O Tester) and stress-ng (Stress-ng). If the PCIe device is a GPU, power or computing power checks can be performed. For power checks, a GPU burn (long-term full-load stress test) can be performed.

[0059] For hard drives, stress test commands can be sent to the CPU via host computer software to perform direct write stress tests on PCIe devices. This simulates high-load scenarios in real-world applications, such as continuous random writes, sequential writes, or mixed read / write operations, to test the hard drive's performance and stability under the PCIe link. The host computer software controls the CPU to operate on the corresponding slot's PCIe registers, thereby controlling the hard drive's operating state and load level. During the stress test, the CPU system needs to record performance indicators such as the PCIe device and hard drive's write speed (throughput), IOPS (input / output operations per second), latency, error rate, and temperature changes. Simultaneously, the CPU system needs to monitor CPU system resource usage, such as CPU utilization, memory utilization, and PCIe link occupancy. If abnormal phenomena occur during the stress test, such as data write interruptions, error reports, sudden drops in speed (e.g., the drop value exceeds the preset drop value, or the drop rate exceeds the preset drop rate), or system response delays, the CPU system can automatically record and mark them as abnormal. This can be implemented by comparing performance data before and after the stress test to determine if it is within the expected range. For example, if the write speed is significantly lower than the theoretical maximum, or if data verification errors, timeout errors, or system crashes occur, it is considered abnormal. Simultaneously, real-time monitoring of the PCIe link status is used to confirm whether there is link congestion, speed degradation, or other link-level problems, ensuring that the stress test results accurately reflect the interaction performance between the hard drive and the PCIe interface.

[0060] When a PCIe device is a computing unit such as a GPU, the host computer software controls the GPU to execute corresponding test instructions through the CPU. The CPU system reads information such as the current power consumption, maximum power consumption, memory capacity, number of CUDA (Compute Unified Device Architecture) cores, and computing capability version (CC) of the computing unit; and compares it with the specifications or manufacturer data to verify whether it meets expectations. The CPU system records the verification results and saves them to the hard disk unit.

[0061] In addition, the host computer software controls the computing unit to perform long-term high-load operations (such as rendering and computationally intensive tasks) through the CPU; the CPU system monitors the power consumption, temperature, operating status and performance of the computing unit; and determines and records any abnormalities such as performance degradation, temperature exceeding limits, or system crash.

[0062] In some embodiments, the autonomous driving service testing mentioned in 4) above may include specific testing for autonomous driving scenarios. These include disk write scenarios unique to autonomous driving services, such as: normal multi-concurrency mode (small data volume but many disk write processes, i.e., multi-process, multi-queue depth approach for disk writing); burst mode (Burst Data Logging Mode / Burst Write Mode), scenarios requiring data capture during rapid OTA updates or when problems occur; and scenarios involving short-term (e.g., within 60 seconds) full-speed writing of extremely large data volumes (10GB~50GB). For disk write scenarios unique to autonomous driving services, targeted data write performance testing is required. To this end, testing PCIe devices based on preset testing items can be implemented as follows: Figure 3 As shown: S301, if the preset detection items include autonomous driving service detection, control the target hard drive in the PCIe device to perform at least one of the following preset operations: Operation 1: Use multiple processes to concurrently write a first preset data volume, where the first preset data volume is less than a first preset threshold. The first preset data volume simulates a scenario with small data volumes in autonomous driving operations, such as simulating the continuous small-volume data writing from multiple sensors in autonomous driving operations.

[0063] Operation 2: Write a second preset amount of data within the target duration, where the second preset amount of data is greater than the second preset threshold; the first preset threshold is less than the second preset threshold. The second preset data volume is used to simulate sudden large-scale data writing in autonomous driving business, such as ultra-large data volume (10GB (Gigabyte) ~ 50GB).

[0064] The target duration is shorter than the preset duration to facilitate testing for large write demands in a short period of time.

[0065] S302 collects the I / O (Input / Output) latency and write speed of the PCIe device for each preset operation.

[0066] I / O wait time is the time a process is blocked while waiting for disk, network or other peripheral devices to complete data read / write operations.

[0067] S303 determines the data write performance of PCIe devices in autonomous driving scenarios based on IO wait time and write speed.

[0068] During implementation, for different autonomous driving services, the IO wait time and write speed can be compared to see if they are within the expected time and if they are within the expected speed range, and the comparison results can be recorded.

[0069] In this embodiment, test items are designed for data write-to-disk scenarios unique to autonomous driving services (such as high concurrency, burst writes, and short-term full-speed writes) to improve the applicability and accuracy of the tests, thereby enhancing the specificity of the verification of PCIe devices required for autonomous driving services. By collecting key indicators such as IO wait time and write speed, the performance of PCIe devices in specific business scenarios is comprehensively evaluated, thereby improving the reliability of PCIe devices.

[0070] Furthermore, in some embodiments, the detection of autonomous driving services mentioned in 4) above may also include the detection of capabilities of operators specific to autonomous driving scenarios. Perception algorithms specific to autonomous driving services utilize GPUs for visual stitching, BEV (Bird's Eye View), and spatial fusion perception of LiDAR and camera data. To this end, detecting PCIe devices based on preset detection items can be implemented as follows: Figure 4 As shown: S401, when the preset detection items include autonomous driving business detection, control the target GUP and target hard disk in the PCIe device to execute specific operators in the autonomous driving scenario.

[0071] In autonomous driving business testing, specific perception algorithm operators are further introduced as testing items. These specific operators include visual stitching, BEV generation, and multi-sensor data fusion (such as spatial alignment and fusion of LiDAR and camera data). These specific operators typically have high requirements for real-time performance, data throughput, and data consistency. During testing, the target GPU and target hard drive in the PCIe device are controlled to execute these specific operators to simulate the data processing flow and hardware coordination requirements of a real autonomous driving system. This step enhances the relevance of the test to the actual application scenarios of autonomous driving businesses by executing operators relevant to actual business operations, rather than just general performance testing.

[0072] S402, based on the execution result of a specific operator, determines the PCIe device's support capability for that specific operator.

[0073] After executing a specific operator, the CPU system analyzes and evaluates the execution results, such as whether the operator processing was successfully completed, whether the processing latency was within the expected range, whether the data was complete and error-free, and whether any transmission interruptions or packet loss occurred. These execution results determine whether the PCIe device can provide sufficient and stable bandwidth between the GPU and the hard drive, and whether it meets the requirements of specific operators in autonomous driving scenarios regarding data transmission latency, parallel processing capabilities, and data integrity, thereby determining its support capability for those specific operators.

[0074] In this embodiment of the disclosure, by executing specific operators in real autonomous driving business scenarios, the collaborative processing capability of PCIe devices in autonomous driving systems can be evaluated more accurately, thereby improving the practicality and relevance of the test.

[0075] During implementation, given the high requirements of operators for data bandwidth, latency, and concurrency, it can effectively identify potential performance bottlenecks or compatibility issues in PCIe devices at the low-level communication layer. Testing specific operators can specifically verify the stability and reliability of PCIe devices under high-load algorithm processing scenarios, enhancing the overall operational assurance capabilities of autonomous driving systems. It also provides strong testing evidence for optimizing data transmission between GPUs and storage devices in autonomous driving systems, helping to improve the matching degree between hardware selection and system design.

[0076] In summary, autonomous driving service testing can be used to evaluate the performance of GPU and NVMe. By monitoring GPU usage, core frequency and other status information during testing, and NVMe monitoring IO wait, write speed and other core status information, it can assess whether PCIe devices can properly support autonomous driving services.

[0077] In addition to the functional testing described above, physical layer testing is also included, as explained above. In some embodiments, physical layer testing includes at least one of the following: (1) Initialization capability detection is used to check whether the initialization result is correct after the PCIe device is powered on and initialized.

[0078] During implementation, if the initialization capability test result of the PCIe device indicates that there is no device fault in the PCIe device, a functional test is performed to improve the accuracy of the functional test results.

[0079] The detection of PCIe devices based on preset detection items can be implemented as follows: when performing initialization capability detection, obtain the first parameter set after the PCIe device is initialized; the first parameter set represents the initialization result of the PCIe device; and determine whether the PCIe device has a device fault based on the first parameter set.

[0080] For example, the first set of parameters for initial capability detection includes, but is not limited to, connection status, number of channels, rate (Genversion), and detection of any errors.

[0081] The connection status detection is used to check whether the PCIe device has successfully established a connection with the CPU. Specifically, it can be implemented by reading the link status register in the PCIe configuration space and checking whether the link status is marked as successfully established. If so, the connection status detection is successful; otherwise, it means that the PCIe device has not been correctly identified or the connection has failed.

[0082] The channel count detection is used to check whether the number of physical channels used by the PCIe device is correct (e.g., x1, x4, x16, etc.). Specifically, it can be implemented as follows: read the channel number segment from the PCIe configuration space; check whether the actual number of PCIe channels used by the PCIe device matches the system configuration or device specifications (e.g., x1, x4, x16); if they match, it indicates that the device is correctly using channel resources or the system configuration is accurate; otherwise, it indicates that the device is not correctly using channel resources or the system configuration is incorrect.

[0083] Rate detection is used to check whether the PCIe device has negotiated the correct PCIe version (such as Gen1 to Gen5) with the CPU system after initialization. Specifically, it reads the rate field in the PCIe configuration space and checks whether the negotiated rate of the PCIe device is the expected PCIe Gen version (such as Gen1, Gen2, Gen3, Gen4). If the negotiated rate is lower than the highest rate supported by the device or does not meet the specified requirements, it is considered abnormal; otherwise, the rate is correct.

[0084] Error detection is used to check for errors during initialization (such as link training errors, device identification errors, etc.). This can be implemented as follows: obtain the target information from the status field in the PCIe configuration space or the system log, and check whether there are error flags (such as Link Error, Device Error, Transaction Error) set in the target information. If there are error flags, it is determined to be abnormal and further investigation is required; otherwise, no error is recorded.

[0085] The initialization capability checks of PCIe devices, such as connection status, number of channels, speed (Gen version), and error detection, comprehensively assess the normal operating status of PCIe devices during the system initialization phase. Specifically, connection status detection verifies whether the PCIe device has successfully established a communication link with the CPU; channel count detection confirms whether the actual number of physical channels used by the device matches the system configuration or device specifications, such as x1, x4, x16, ensuring accurate resource allocation and preventing resource conflicts; speed detection checks whether the speed negotiated between the PCIe device and the CPU is consistent with the highest speed supported by the device or the required system version, such as Gen1 to Gen5, ensuring that data transmission performance meets application requirements; and error detection checks for abnormal flags such as link training errors and device identification errors by reading status fields in the configuration space or system logs, thereby promptly identifying and eliminating potential faults during the initialization process.

[0086] The initialization capability test of PCIe devices is highly operable and systematic, which can improve the compatibility, stability and reliability of PCIe devices during the initialization phase, provide a reliable hardware foundation for subsequent service testing, and help improve the efficiency of debugging and troubleshooting.

[0087] (2) Physical link quality detection, as the name suggests, is used to detect the physical link quality of PCIe devices.

[0088] In this embodiment of the disclosure, the physical link quality is mainly evaluated through the margin of the PCIe device, and can be implemented as follows: Figure 5 As shown: S501, when performing physical link quality detection, adjusts the target parameters of the PCIe device to obtain multiple sampled values ​​of the target parameters; the target parameters include time offset and / or voltage offset.

[0089] During implementation, testing can be performed on time offset only, voltage offset only, or both simultaneously.

[0090] Whether testing one or both, the host computer software can send commands to the PCIe device's Lane Margin Control Register via the CPU to adjust the horizontal time offset (phase) and / or vertical voltage offset of the PCIe device's sampling points sequentially according to the set step values, so that the sampling points are scanned from the center of the eye diagram outwards.

[0091] S502, obtain the margin corresponding to multiple sampled values ​​of the PCIe device pin.

[0092] Each time an offset position is set, a sample value is obtained. The margin status corresponding to the sample value is read from the PCIe device's Lane MarginStatus Register (used to indicate whether the downlink can still receive data correctly at the current offset).

[0093] S503 constructs an eye diagram based on the margins corresponding to multiple sampled values.

[0094] During implementation, the margins of all sampled values ​​are converted into eye diagrams. These margins are organized according to a combination of time offset and / or voltage offset, and then converted into visual data of the eye diagram. An eye diagram is a graphical representation of high-speed signal quality by observing the waveform of the margin signal at different time offset and / or voltage offset positions. The margin of this waveform at that offset position is then converted into the "open" or "closed" state of the signal eye diagram. Each margin represents the maximum disturbance (such as time margin or voltage margin) that the link can tolerate at that offset position. If the margin value is ≥ a preset threshold (e.g., time margin ≥ 50 ps, ​​voltage margin ≥ 20 mV), the signal is considered to still be able to transmit normally at that offset position, i.e., the "open" state; if the margin value is < a preset margin threshold, the signal is considered to be unable to transmit reliably at that offset position, i.e., the "closed" state. For each sampled value, the corresponding signal state is plotted at the offset position; if the signal is "on" at that point, the point is marked as an effective region in the eye diagram; if the signal is "closed", it is marked as an invalid region; by continuously plotting these points, the "eye" boundary contour of the eye diagram is formed.

[0095] S504 matches the eye diagram with the template to obtain the matching result.

[0096] In other words, by comparing the eye diagram with the corresponding template, signal integrity indicators such as eye width, eye height, eye opening, jitter, and bit error rate can be extracted from the generated eye diagram. Among these, a1) Eye Width: This can be represented as the widest interval in the eye diagram on the target axis, and is usually determined by the margin value. a2) Eye Height: The highest interval in the eye diagram on the target axis; for example, based on the voltage offset, the relationship between voltage and margin is constructed to obtain the highest interval in the eye diagram on the voltage axis. a3) Eye Opening: The "sharpness" of the signal at a certain offset point, which can be represented by the absolute or relative value of the margin value; the center parameter in the target parameters can be selected as the "certain offset point". At this point, the "eye" of the eye diagram is the largest, indicating that the signal is the clearest and the bit error rate is the lowest.

[0097] a4) Jitter: In an eye diagram, jitter manifests as lateral jitter in the signal waveform. It affects the eye width. Lateral jitter typically refers to the deviation of the signal along the time axis, causing the "eye" of the eye diagram to become blurred or even closed horizontally. To quantify lateral jitter in an eye diagram, information related to the time offset can be extracted from the collected margin data and combined with the eye diagram construction logic to reflect the impact of jitter on signal integrity. For example, by finding the position on the time axis where the "margin is 0" or "margin is below the threshold," the jitter tolerance can be determined. The lateral jitter tolerance of the signal is the maximum allowable time offset value (i.e., the maximum absolute value of the margin). When the margin waveform shifts from the signal center to the left and right, the margin begins to decrease. A critical point where the margin decreases to the margin threshold can be located on each side. The distance between these two critical points is the jitter tolerance (Eye Width).

[0098] a5) Bit Error Rate (BER): The bit error rate at this offset can be estimated based on the margin value.

[0099] S505 determines the physical link quality of PCIe devices based on the matching results.

[0100] If all parameters meet the requirements of the preset template (e.g., eye width ≥ first preset value, eye height ≥ second preset value, jitter ≤ third preset value, bit error rate within preset range), the link status is determined to be "Pass", meaning the physical quality of the link is normal; if any parameter exceeds the preset threshold, it is determined to be "Fail", meaning the physical link quality is abnormal, and the specific reason for failure can be recorded (e.g., jitter greater than the jitter threshold, i.e., jitter too large, eye height lower than the eye height threshold, i.e., eye height too low, etc.).

[0101] In this embodiment, eye diagrams constructed using margin are used to detect the physical link quality of PCIe devices. This method can intuitively reflect the integrity and reliability of signals during transmission. By analyzing the opening degree of the eye diagram, the margin value of the signal at different offset positions is evaluated, thereby determining whether there is excessive jitter, noise, or attenuation in the link. The wider the eye diagram and the larger the margin value, the clearer the signal, the lower the bit error rate, and the better the link quality. Conversely, a severely closed eye diagram indicates that the signal is interfered with, the bit error rate may increase, and the link stability decreases. This method can help quickly locate bottlenecks in signal transmission, optimize design parameters, or adjust hardware configurations to ensure that PCIe devices maintain reliable communication performance under high-speed transmission.

[0102] In some embodiments, if the initialization capability test result of a PCIe device indicates a device fault, a physical link quality test is performed. That is, if the initialization test determines that the PCIe device is faulty, it indicates a potential problem with the physical link quality. Performing a physical link quality test allows for targeted testing and verification of the PCIe device, improving the efficiency and accuracy of PCIe device verification.

[0103] (3) Connection stability test.

[0104] During implementation, the connection stability test is controlled by the host computer. The host computer software controls the relevant registers of the corresponding PCIe slot of the CPU via USB through the PCH to complete the connection stability test.

[0105] In this embodiment of the disclosure, the connection stability detection includes at least one of the following: b1) Connection rate switching test, used to detect the connection stability of PCIe devices when switching between two connection rates.

[0106] Connection rate switching tests are used to assess the communication stability of PCIe devices when switching between different connection rates. The test can use adjacent or non-adjacent rates for switching, including unidirectional switching from a high rate to a low rate, unidirectional switching from a low rate to a high rate, and bidirectional switching between the two. This test verifies whether the PCIe device can maintain normal communication functionality during switching, ensuring the continuity and reliability of data transmission, and avoiding problems such as increased bit error rate, link disconnection, or protocol layer anomalies caused by switching. Therefore, it evaluates the performance and compatibility of PCIe devices under scenarios of changing connection rates.

[0107] During implementation, the host computer software controls the registers of the PCIe devices in the CPU's PCIe slot to set their speed, thereby switching between different speed modes (such as Gen1 to the highest speed supported by the device).

[0108] In each rate mode before and after the switch, acquire link status information (such as connection status, error count, bandwidth utilization, etc.) and device response data. After acquiring the link status information and device response data, perform the following analysis: b1-1) Connection status check: Confirm whether the link is in "Link Up", that is, the communication has been established. If so, it means that the device has successfully identified and switched to the current rate mode.

[0109] b1-2) Error Count Analysis: Check the link error count (such as Link Training Errors, Recovery Errors, etc.). If the error count remains within the preset baseline value or does not increase significantly before and after the switching rate (such as the increase is greater than the preset increase), it is considered normal. If there is an abnormal increase or the value exceeds the threshold, it indicates that there is an error in the link.

[0110] b1-3) Bandwidth utilization analysis: Monitor whether the bandwidth utilization during the communication process before and after the handover is stable and close to the theoretical maximum value. If the fluctuation is too large (such as exceeding the fluctuation threshold) or cannot reach the expected value (it may be the maximum value or other values ​​determined by the business scenario), there may be a rate mismatch or transmission abnormality.

[0111] b1-4) Device response verification: Check whether the device responds to requests normally at the set rate. If there is packet loss, delay or response failure, it indicates that there may be an abnormality in the function.

[0112] During implementation, the connection speed switching test can control the PCIe rate to switch between Gen1 and the highest speed supported by the device. The number of test cycles is n (for efficiency and functional reliability considerations, such as n>200, <1000), to verify the reliability of the limit rate switching function.

[0113] b1-5) Cyclic test consistency: Test at different speeds multiple times and observe whether the link status and device response are consistent in each test. If the test results are stable and without abnormalities at the same speed, it indicates that the connection stability and functional reliability are good.

[0114] In summary, if the link status is normal, the error count is stable, the bandwidth utilization is reasonable, and the device response is normal before and after the two rates, it means that the link connection stability before and after the switch meets expectations. Otherwise, the link connection stability does not meet expectations. Regardless of the result, it should be recorded.

[0115] b2) Tiered rate switching test, used to detect the connection stability of PCIe devices when multiple connection speeds are switched sequentially; Reliability of tiered rate switching, i.e., testing from Gen1->Gen2-> Switch to the highest speed, then switch back to Gen1. The number of test loops can be m, such as m > 200, < 1000.

[0116] In one possible implementation, when performing a tiered rate switching test, the registers of the PCIe device are controlled to change the connection rate of the PCIe device sequentially; after each change of the connection rate, the set connection rate and the connection speed performed by the PCIe device are compared to see if they are consistent, and the comparison result after each change of connection rate is obtained; based on the comparison result after each change of connection rate, the test result of the tiered rate switching test is obtained.

[0117] This method can verify whether the final switching result meets expectations after multiple switching rates.

[0118] During implementation, the connection speed executed by the PCIe device can be sent to the host computer software via the BMC, so that the host computer software can perform the following: compare whether the set connection speed and the connection speed executed by the PCIe device are consistent, and obtain the comparison result after each change of connection speed; based on the comparison result after each change of connection speed, obtain the test result of the tiered rate switching test.

[0119] By conducting tiered rate switching tests and verifying whether the actual rate after each switch is consistent with the setting, the communication stability of the device during the rate switching process is comprehensively evaluated, ensuring that it can operate reliably and continuously in different rate modes.

[0120] Furthermore, this test can primarily focus on connection stability during multiple rate switching sessions. For each rate, connection status checks, error count analysis, bandwidth utilization analysis, and device response verification can be performed using the methods described above. This ensures that the PCIe device continues to function normally after each rate switch.

[0121] Based on this, if the link status and device response are basically consistent after multiple cyclic tests, i.e. the error is within the preset range, then the test is considered passed; otherwise, the test is considered to have failed, and the final test result is recorded.

[0122] By conducting tiered rate switching tests, the protocol consistency, hardware responsiveness, and communication stability of PCIe devices during rate transitions can be evaluated, ensuring their reliable and continuous operation under different rate modes.

[0123] b3) Recovery capability test, used to test the PCIe device's link recovery capability in the event of link abnormality or disconnection.

[0124] During implementation, the host computer software controls the operation via USB through the PCH to manipulate the registers representing the recovery capability of the corresponding PCIe slot on the CPU, thereby achieving reliability testing of the link retraining and recovery functions. This test item is mainly used to verify whether the PCIe link can correctly retrain and restore the connection state under abnormal or disconnection conditions.

[0125] During implementation, the host computer software controls the CPU to trigger the disconnection of the PCIe link (which can be a simulated disconnection or an actual physical disconnection) to initiate the retraining process. During retraining, the CPU performs the link retraining operation after the disconnection. At this time, the device (i.e., the PCIe device inserted in the slot) should respond and attempt to re-establish the connection. After the retraining is completed, check whether the link can return to normal working status, such as confirming whether the PCIe device has been re-enumerated and whether communication is normal.

[0126] The connection can be interrupted multiple times during the test, and at least one of the following information can be analyzed and recorded: After each disconnection, check whether the link re-enters the Link Up state within the predetermined time (i.e., determine whether the recovery was successful). The specific time points for state transitions, such as the exact time points from Link Down to Training, and then to Link Up; A state transition sequence records the complete transition path of the link state, for example: disconnection → retraining → connection establishment → error → disconnection; The duration of the link status is used to record the duration of each status (such as Training, Link Up) during the disconnection process and to determine whether it is abnormal; The success rate of link recovery is obtained by determining the ratio of the number of times the link recovers from Link Down to Link Up to the number of times the Link Down state is recorded. After each disconnection, check whether the link re-enters the Link Up state within the predetermined time to determine the time required for retraining; Analyze the CPU system's error codes and BMC logs to determine and record the causes and frequency of retraining failures in order to identify potential hardware or driver issues.

[0127] Of course, during implementation, other test items and recorded analysis content can be added as needed, and this disclosure does not limit this.

[0128] Recovery capability testing can improve the robustness of PCIe devices in the face of sudden link interruptions in actual use, ensuring the continuity and stability of communication; it can comprehensively test the collaborative working ability of the device and host during the retraining process, ensuring that the link can be reliably re-established; it can help to discover and fix potential protocol compatibility issues, enhancing the overall stability and reliability of the system.

[0129] b4) Link enable test, used to test the enable and / or disable functions of PCIe devices; In other words, the host computer software sets the registers of the PCIe device's relevant enable status through the CPU, and verifies whether the PCIe device can maintain a stable working state when the link is frequently enabled or disabled, so as to avoid communication interruption or performance degradation caused by frequent switching.

[0130] During implementation, PCIe devices can be configured to enter and exit enabled / disabled states multiple times. At least one of the following information will be collected: Switchover success rate: This refers to the number of successful enable / disable operations to determine if switchover failures or link unrecoverable situations occur. Within a specified number of test loops (n>200, <1000), the success rate of enable and disable operations must reach the expected level, such as above 99%. Switching latency analysis: Measure the time required for each enable and disable operation to determine whether the link response speed is normal and whether there is abnormal latency.

[0131] Error log analysis: Analyze whether training failures, abnormal link status, error codes, etc. occur during the switching process. If errors occur, analyze their causes, such as whether they are hardware limitations, firmware defects, or protocol compatibility issues. Communication stability analysis: After the handover is completed, data communication tests are performed to check for packet loss, delays, or communication interruptions.

[0132] Link enable testing can improve the robustness of PCIe devices to enable switching in actual use, ensuring the continuity and stability of communication; it can also comprehensively test the ability of both the device and the CPU host to enable and disable functions, helping to discover enabling problems and enhance the overall stability and reliability of the system.

[0133] b5) Rebalancing test, used to test the PCIe device's ability to rebuild the link and restore communication after the CPU system is rebalanced; In PCIe versions 3.0+ and above, the host computer software can control the CPU to send ordered sets to renegotiate the equalization parameters at the transmitting end. This verifies whether the PCIe device can correctly adjust the equalizer, complete link reconstruction, and restore data communication after the CPU actively changes the signal compensation settings.

[0134] During implementation, the rebalancing test can be conducted using the following method: Step A1: Baseline recording, which confirms that the link is in L0 state (optional, defined as power consumption state and power saving state), records the current PCIe rate (Gen3 / 4 / 5), link width (x16 / x8) and correctable error count (CE).

[0135] Step A2 triggers re-equalization, which means that the host computer software forces the CPU Root Port to enter the Recovery.Equalization state and resends the equalization training sequence (by modifying the Tx Preset value to simulate changes in the signal environment).

[0136] Step A3, monitoring the balancing phase, involves observing whether the CPIe device sequentially completes Phase 0 (rate negotiation) → Phase 1-3 (Preset request / response) → RcvrLock without any state machine freezing. In practice, this step can be confirmed by monitoring the CPU system's system logs.

[0137] Step A4, link recovery confirmation, i.e., verifying whether the EP has successfully returned to the initial state (such as L0), and the link rate / width is almost consistent with the baseline (such as no degradation to Gen1 / 2 or x8 / x4), and the Correctable Error count does not surge.

[0138] Step A5: Perform full-bandwidth DMA read / write or high-load service tests for a target duration, such as 5-10 minutes, to confirm that there are no data transmission errors, no retries (NAK / REPLAY), and that the PCIe device has not been disconnected from the CPU system.

[0139] If the CPIe device recovers to its previous state (such as L0 state) within a specified number of seconds after CPU rebalancing, the link configuration is not degraded, the error count hardly increases (i.e., the growth rate or the amount of increase is lower than the corresponding growth threshold), and the service traffic is stable and uninterrupted, then the connection stability of the rebalancing test is considered relatively reliable.

[0140] b6) Reset function test, used to test the reset function of PCIe devices; In other words, the host computer software sends a reset signal to the secondary bus by controlling the register of the corresponding PCIe slot through the CPU.

[0141] During implementation, PCIe link status logs and device enumeration information can be read from the BMC. The test results are obtained by analyzing whether the device was successfully reset.

[0142] The rebalancing test is used to verify whether PCIe devices can correctly rebuild links and restore communication after the CPU system is rebalanced (such as resource reallocation, power management, or system configuration changes). This test can improve the stability of communication of PCIe devices during dynamic system adjustments, enhance the adaptability and reliability of the system, detect the device's response to changes in link status, and verify its compatibility and robustness in complex environments.

[0143] b7) Power switching function test, used to test the power mode switching function of PCIe devices.

[0144] The host computer software controls the registers of the corresponding PCIe slot through the CPU to set the PCIe link to enter L1 low power mode, and then set it to other modes, such as L0 mode. The link is retrained, and after a preset delay, the link up status is read. The operation is repeated p times or more (the value range of p is the same as n). Each successful read of link up means the test is successful, and each failure means the test fails (that is, the power switching function test fails).

[0145] Power switching function testing helps improve the flexibility of PCIe devices in adjusting power consumption under system energy-saving requirements, thereby enhancing the overall system's energy efficiency management capabilities; it verifies the communication stability and protocol compatibility of devices during power switching, preventing data transmission anomalies or connection interruptions caused by power consumption changes; and it enhances the performance and reliability of devices in low-power mode, meeting high-energy-efficiency design requirements.

[0146] In summary, the embodiments disclosed herein can support the verification of various PCIe devices. They are particularly suitable for the verification of PCIe devices in autonomous vehicles. Overall, the general testing process is as follows: Figure 6 As shown, it includes: S601, PCIe device power-on initialization, performs basic connection parameter checks. That is, initialization capability detection, which can be defined as Level 0 verification, including: connection status, number of channels, speed, and whether there are any errors.

[0147] S602, determine whether Level 0 verification passed. If it passed, execute S603; otherwise, execute S604.

[0148] S603 initiates functional and performance testing, including Level 1 device configuration testing, Level 2 driver testing, Level 3 performance testing, and Level 4 autonomous driving service testing, and records the test results for each test.

[0149] Among them, Level 1 device configuration detection mainly checks whether the PCIe device enumeration is successful and whether the device ID and configuration space are correct. Level 2 driver detection primarily checks whether the drivers for PCIe devices are functioning correctly. Level 3 performance testing mainly involves enabling stress tests, such as hard drive fio, stress ng, and dd direct write stress tests; GPU power and computing power checks, and gpu_burn stress tests, etc. Level 4 autonomous driving business testing mainly includes GPU-specific operator testing and autonomous driving disk placement method testing.

[0150] S604 enables PCIe physical channel signal margin verification, realizing physical link quality detection.

[0151] Among them, physical channel signal margin verification is a function supported by the PCIe protocol since version 4.0. The specific implementation of this invention is that the host computer software logs into the CPU system through the serial port, configures the PCIe lane margin function through the setpci tool in the Linux system, and reads the PCIe lane margin result from the corresponding register to obtain the eye diagram to evaluate the physical connection quality status of the link. It is compared with the preset eye diagram template to obtain the pass and fail results, that is, the result of successful matching and failed matching.

[0152] S605, enable PCIe connection stability test and record the test results. As described above, this includes the above 7 connection stability tests, which will not be repeated here.

[0153] S606, Test complete. The host computer analyzes the test results and can provide a pass / fail indicator or cause of failure for the PCIe device.

[0154] In summary, this disclosure provides a PCIe device testing method that supports verification of commonly used PCIe devices in autonomous driving products. It integrates CPU debugging functionality, allowing access to the CPU's internal PCIe registers (e.g., Level 0, Level 1, signal margin test, connection stability test) from the lowest-level code via host computer software to complete verifications such as connection stability testing. Furthermore, this disclosure provides a PCIe device testing method that can perform full-link verification from functional performance verification (e.g., Level 2-4) to the underlying physical link connection reliability (e.g., Level 0, signal margin verification, connection stability test). It can effectively detect faults in PCIe devices and satisfy the requirements of the PCIe device physical layer (e.g., Level 0, signal margin verification, connection stability test), link layer, and transaction layer (e.g., Level 3-4). Functional verification in autonomous driving applications requires simultaneous verification of these two layers, especially for Level 3 layer detection, which requires recording DLLP (Data Link Layer) and TLP (Transaction Layer). Verification requirements extend from the transaction layer (e.g., level 2) to the autonomous driving business layer (e.g., level 4), enabling full-process and all-stage verification of PCIe devices. This improves fault detection rates, and verification during the design phase helps improve the design. During implementation, the host computer software provides a user interface, which facilitates batch automated verification and provides convenient and comprehensive verification functions.

[0155] Based on the same technological concept, such as Figure 7 As shown in the illustration, this disclosure also provides a PCIe device verification apparatus 700. It is understood that the structure and connection relationships of the PCIe device verification apparatus 700 can be referenced. Figure 2 The process of completing the PCIe device testing can be performed using the aforementioned method, and will not be described in detail in this embodiment. The structural relationships will be introduced later, such as... Figure 7 As shown, it includes: The host computer software 701 is used to send detection instructions to the CPU 7021 of the CPU system; the detection instructions include preset detection items. CPU system 702 is used to detect the PCIe device in the slot based on the preset detection items. The CPU system includes a slot 7022 for at least one PCIe device to be plugged in, and a memory unit 7023 and a hard disk unit 7024 that are communicatively connected to the CPU. The memory unit 7023 provides high-speed storage space for the CPU during operation; The hard disk unit 7024 is used to store the operating system.

[0156] In this embodiment, the CPU system can connect to and control PCIe devices of the required type via slots. The entire CPU system acts as a debugger for the PCIe devices, responding to detection commands from the host computer software to debug and verify them. The host computer software can send detection commands to the CPU system according to testing requirements, enabling on-demand testing. The entire verification device achieves a unified control architecture from the underlying signal layer to the high-level business logic at the software level, eliminating the need for fragmented modules at different detection layers when detecting PCIe devices.

[0157] In some embodiments, the CPU system further includes a debugger and a PCH, the PCH being connected to the CPU, and the host computer software sending the detection instructions to the CPU through the debugger and the platform control center.

[0158] This architecture, while maintaining ease of debugging, adds a security isolation layer and system management capabilities through PCH, realizing a unified platform for testing, debugging, and operation and maintenance, reducing hardware complexity, and improving system maintainability.

[0159] In some embodiments, the PCH is specifically used to expand the USB interface and access the flash memory of the CPU system; The PCH is used to communicate with the debugger via the PCH's USB interface; The host computer software communicates with the debugger via a USB interface.

[0160] In this implementation, the PCH simultaneously carries three data paths through a unified USB interface: an out-of-band control channel for connecting to a debugger, firmware-level access via direct connection to the CPU system's Flash memory, and an expansion interface for standard USB peripherals—forming a closed loop of "debugging-storage-expansion." This design makes the PCH an I / O scheduling center independent of the CPU: even if the CPU fails, the host computer can still directly read and write to the Flash memory via the USB→debugging→PCH path to complete system recovery; during normal operation, the same USB physical layer serves both business expansion and debug access without additional wiring; the PCH's protocol conversion capability also naturally isolates the direct interaction between the host computer and the CPU, simplifying hardware while ensuring underlying security.

[0161] In some embodiments, the CPU system further includes a Baseboard Management Controller (BMC), which communicates with the host computer software via a serial port or network to send the CPU status log to the host computer software and provide out-of-band CPU management; the status log is used by the host computer software to determine the verification result of the PCIe device.

[0162] In this implementation, the BMC serial port channel and the PCH-debugger USB channel complement each other, enabling a dual-track verification mechanism for PCIe device testing: the BMC can report CPU operating status logs in real time (such as link training, error count, hot-plug events), and even if the PCIe link causes the CPU to crash, the BMC can still provide feedback on the fault scene, and the host computer software can complete the verification, improving the debugging efficiency and fault coverage of complex PCIe devices.

[0163] In some embodiments, when performing a connection stability test on the PCIe device, the detection instruction is used to set the registers of the PCIe device in the CPU to complete the physical layer detection.

[0164] This design achieves efficient verification of PCIe connection stability through software-defined physical layer testing: the host computer directly issues register configuration instructions through the debugger-PCH channel to precisely control PCIe physical layer parameters without relying on operating system drivers or CPU applications, thus avoiding software stack interference; it can realize automated, repeatable, and high-coverage detection of physical layer faults, improving the verification efficiency of PCIe devices.

[0165] During implementation, detection involving the device interaction layer can be achieved by collecting information from the link where the debugger is located and feeding it back to the host computer software. The host computer software then analyzes the detection results, which may include, for example: Device configuration detection (reading configuration space and register values); Connection speed switching test; Tiered rate switching test; Reset function test; Performance testing (such as stress testing, DMA data acquisition).

[0166] For detections involving the system monitoring layer, information collected from the link where the BMC is located can be fed back to the host computer software, which can then analyze the detection results, including, for example: Link enable / disable test; Recovery capability test (system recovery assessment); Rebalancing test (initiated by the system); Power consumption switching function detection (power consumption mode controlled by the system); Partial driver detection (requires system logs); Autonomous driving business detection (requires interaction with the device business layer).

[0167] It is understandable that if link enable / disable and power switching are only used for status monitoring, it is reasonable for the BMC to collect information from the link. However, if active triggering is required, it actually depends on the debugger issuing instructions, and the BMC only provides feedback. Therefore, in this case, detection is completed collaboratively.

[0168] Based on the same technical concept, this disclosure also provides a PCIe device detection device 800, wherein the host computer software communicates with the CPU of a CPU system, the CPU system including a slot for at least one PCIe device; as Figure 8 As shown, it includes: The receiving module 801 is used to receive a detection command sent by the host computer software, the detection command including preset detection items; Test module 802 is used to test PCIe devices based on preset test items.

[0169] In some embodiments, the preset detection items include functional detection and / or physical layer detection.

[0170] In some embodiments, functional testing includes at least one of the following: Device configuration detection is used to check whether the configuration parameters of a PCIe device match the expected configuration. Driver detection is used to check whether the drivers for PCIe devices are working properly. Performance testing is used for stress testing of PCIe devices; Autonomous driving service testing is used to test the PCIe device's ability to support specific autonomous driving services.

[0171] In some embodiments, the test module includes: The first test unit is used to control the target hard disk in the PCIe device to perform at least one of the following preset operations when the preset test items include autonomous driving business testing: Operation 1, using multi-process concurrent writing of a first preset data amount, where the first preset data amount is less than a first preset threshold; Operation 2, writing a second preset data amount within a target duration, where the second preset data amount is greater than a second preset threshold; where the first preset threshold is less than the second preset threshold. The acquisition unit is used to acquire the I / O wait time and write speed of the PCIe device for each preset operation; The first determining unit is used to determine the data write performance of the PCIe device in the autonomous driving scenario based on IO wait time and write speed.

[0172] In some embodiments, the test module includes: The second test unit is used to control the target GPU and target hard drive in the PCIe device to execute specific operators in the autonomous driving scenario when the preset test items include autonomous driving business test. The second determining unit is used to determine the PCIe device's support capability for a specific operator based on the execution result of that specific operator.

[0173] In some embodiments, physical layer detection includes at least one of the following: Initialization capability detection, physical link quality detection, and connection stability detection.

[0174] In some embodiments, the test module includes: The third test unit is used to obtain the first parameter set of the PCIe device after initialization when performing initialization capability detection; the first parameter set represents the initialization result of the PCIe device. The third determining unit is used to determine whether the PCIe device has a device fault based on the first parameter set.

[0175] In some embodiments, the test module includes: The fourth test unit is used to adjust the target parameters of the PCIe device to obtain multiple sampled values ​​of the target parameters when performing physical link quality testing; the target parameters include time offset and / or voltage offset. The acquisition unit is used to acquire the margins corresponding to multiple sampled values ​​of the PCIe device pins. The construction unit is used to construct an eye diagram based on the margins corresponding to multiple sampled values; The matching unit is used to match the eye diagram with the template to obtain the matching result; The fourth determining unit is used to determine the physical link quality of the PCIe device based on the matching results.

[0176] In some embodiments, a first triggering module is also included, which performs physical link quality detection when the detection result of the PCIe device initialization capability detection indicates that the PCIe device has a device fault.

[0177] In some embodiments, a second triggering module is also included, which performs a functional test if the detection result of the PCIe device initialization capability test indicates that the PCIe device does not have a device fault.

[0178] In some embodiments, connection stability detection includes at least one of the following: The connection rate switching test is used to detect the connection stability of PCIe devices when switching between two connection rates; The tiered rate switching test is used to detect the connection stability of PCIe devices when multiple connection speeds are switched sequentially. Recovery capability test is used to test the link recovery capability of PCIe devices in the event of link abnormality or disconnection. Link enable test, used to test the enable and / or disable functions of PCIe devices; The rebalancing test is used to test the PCIe device's ability to rebuild the link and restore communication after the CPU system is rebalanced. Reset function test, used to test the reset function of PCIe devices; The power switching function test is used to test the power mode switching function of PCIe devices.

[0179] In some embodiments, the test module includes: The second test unit is used to control the registers of the PCIe device to change the connection rate of the PCIe device sequentially when performing a tiered rate switching test. The comparison unit is used to compare the set connection rate and the connection speed performed by the PCIe device after each change of the connection rate, and to obtain the comparison result after each change of the connection rate. The fifth determining unit is used to obtain the test results of the tiered rate switching test based on the comparison results after each change in connection rate.

[0180] In some embodiments, the CPU system is connected to slots of various types, including slots that support computing units and slots that support storage units.

[0181] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.

[0182] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0183] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0184] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0185] like Figure 9 As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 902 or a computer program loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0186] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0187] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the PCIe device detection method. For example, in some embodiments, the PCIe device detection method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program can be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the PCIe device detection method described above can be performed. Alternatively, in other embodiments, the computing unit 901 can be configured to perform the PCIe device detection method by any other suitable means (e.g., by means of firmware).

[0188] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0189] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0190] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0191] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0192] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0193] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0194] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0195] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for detecting a PCIe device, wherein, The host computer software communicates with the CPU of the CPU system, the CPU system including a slot for at least one PCIe device, the method comprising: Receive detection instructions sent by host computer software, wherein the detection instructions include preset detection items; The PCIe device is tested based on preset test items.

2. The method according to claim 1, wherein, The preset detection items include functional detection and / or physical layer detection.

3. The method according to claim 2, wherein, The functional testing includes at least one of the following: Device configuration detection is used to detect whether the configuration parameters of the PCIe device match the expected configuration. Driver detection is used to detect whether the driver of the PCIe device is working properly. Performance testing, used to stress test the PCIe device; Autonomous driving service detection is used to detect the PCIe device's ability to support specific autonomous driving services.

4. The method according to claim 3, wherein, The detection of the PCIe device based on preset detection items includes: When the preset detection item includes the autonomous driving service detection, the target hard drive in the PCIe device is controlled to perform at least one of the following preset operations: Operation 1, using multi-process concurrent writing of a first preset data amount, where the first preset data amount is less than a first preset threshold; Operation 2, writing a second preset data amount within a target duration, where the second preset data amount is greater than a second preset threshold; where the first preset threshold is less than the second preset threshold. For each preset operation, the I / O wait time and write speed of the PCIe device are collected; Based on the IO wait time and the write speed, the data write performance of the PCIe device in the autonomous driving scenario is determined.

5. The method according to claim 3, wherein, The detection of the PCIe device based on preset detection items includes: The preset detection items include controlling the target GPU and target hard drive in the PCIe device to execute specific operators in the autonomous driving scenario when the autonomous driving service detection is detected. Based on the execution result of the specific operator, the PCIe device's support capability for the specific operator is determined.

6. The method according to claim 2, wherein, The physical layer detection includes at least one of the following: Initialization capability detection, physical link quality detection, and connection stability detection.

7. The method according to claim 6, wherein, The detection of the PCIe device based on preset detection items includes: When performing the initialization capability detection, a first parameter set after the PCIe device is initialized is obtained; the first parameter set represents the initialization result of the PCIe device. Based on the first set of parameters, determine whether the PCIe device has a device fault.

8. The method according to claim 6, wherein, The detection of the PCIe device based on preset detection items includes: When performing the physical link quality test, the target parameters of the PCIe device are adjusted to obtain multiple sampled values ​​of the target parameters; the target parameters include time offset and / or voltage offset. Obtain the margin corresponding to each of the multiple sampled values ​​for the PCIe device; An eye diagram is constructed based on the margins corresponding to the multiple sampled values. The eye diagram is matched with the template to obtain the matching result; The physical link quality of the PCIe device is determined based on the matching results.

9. The method according to claim 8, further comprising: The initialization capability test result of the PCIe device indicates that the physical link quality test is performed when the PCIe device has a device fault.

10. The method of claim 6, further comprising: The initialization capability test result of the PCIe device indicates that the PCIe device is not faulty, and the functional test is performed.

11. The method according to claim 6, wherein, The connection stability detection includes at least one of the following: The connection rate switching test is used to detect the connection stability of the PCIe device when switching between two connection rates; The tiered rate switching test is used to detect the connection stability of the PCIe device when multiple connection speeds are switched sequentially. Recovery capability test is used to test the link recovery capability of the PCIe device in the event of link abnormality or disconnection. Link enable test, used to test the enable and / or disable functions of the PCIe device; The rebalancing test is used to test the PCIe device's ability to rebuild the link and restore communication after the CPU system is rebalanced. Reset function test, used to test the reset function of the PCIe device; The power consumption switching function test is used to test the power consumption mode switching function of the PCIe device.

12. The method according to claim 11, wherein, The detection of the PCIe device based on preset detection items includes: When performing the tiered rate switching test, the registers of the PCIe device are controlled to change the connection rate of the PCIe device sequentially. After each change in connection rate, the PCIe device compares whether the set connection rate and the connection speed executed by the PCIe device are consistent, and obtains the comparison result after each change in connection rate. The test results of the tiered rate switching test are obtained based on the comparison results after each change in connection rate.

13. The method according to any one of claims 1-12, wherein, The CPU system is connected to slots of various types, including slots that support computing units and slots that support storage units.

14. A PCIe device verification apparatus, comprising: The host computer software is used to send detection instructions to the CPU of the CPU system; the detection instructions include preset detection items. A CPU system is used to detect the PCIe device in the slot based on the preset detection items. The CPU system includes a slot for at least one PCIe device to be plugged in, and a memory unit and a hard disk unit that are communicatively connected to the CPU. The memory unit provides high-speed storage space for the CPU during operation; The hard disk unit is used to store the operating system.

15. The apparatus according to claim 14, wherein, The CPU system also includes a debugger and a platform control hub (PCH). The PCH is connected to the CPU, and the host computer software sends the detection command to the CPU through the debugger and the platform control hub.

16. The apparatus of claim 15, wherein the PCH is specifically used to expand the USB interface and access the flash memory of the CPU system; The PCH is used to communicate with the debugger via the PCH's USB interface; The host computer software communicates with the debugger via a USB interface.

17. The apparatus of claim 14, wherein the CPU system further comprises a baseboard management controller (BMC), the BMC and the host computer software communicating via a serial port or network, the BMC being used to send the CPU status log to the host computer software and provide out-of-band CPU management; the status log being used by the host computer software to determine the verification result of the PCIe device.

18. In the apparatus according to any one of claims 14-17, when performing a connection stability test on the PCIe device, the detection instruction is used to set the registers of the PCIe device in the CPU to complete the physical layer detection.

19. A detection device for a PCIe device, wherein, The host computer software communicates with the CPU of the CPU system, the CPU system including a slot for at least one PCIe device, the device comprising: The receiving module is used to receive detection instructions sent by the host computer software, the detection instructions including preset detection items; The testing module is used to test the PCIe device based on preset test items.

20. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-13.

21. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-13.

22. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-13.

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