Charge / discharge control circuit, charge / discharge control device, and battery device

Abstract

A charge / discharge control circuit, a charge / discharge control device, and a battery device are disclosed. When multiple protection ICs are cascaded, the circuit size can be suppressed. The battery device includes: a battery; a first predetermined state detection unit for detecting a first predetermined state of a first cell; a first logic circuit for performing first control based on the detection result of the first predetermined state detection unit; a second predetermined state detection unit for detecting a second predetermined state of a second cell; a charger connection detection unit for detecting whether the battery is connected to the charger; and a second logic circuit for performing second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and a first notification from the first logic circuit indicating the first predetermined state. The first and second predetermined states are overcharged or over-discharged states. When the detection result of the charger connection detection unit meets the predetermined conditions, the second logic circuit blocks the first notification from the first logic circuit and performs the second control.

Description

Technical Field

[0001] This disclosure relates to a charge / discharge control circuit, a charge / discharge control device, and a battery device. Background Technology

[0002] In a battery (battery pack) circuit comprising multiple cells (single cells) connected in series, there is a known circuit in which multiple integrated circuits (ICs) are cascaded together (see Patent Document 1).

[0003] [Existing Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2005-117780 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] However, in such existing circuits, when overcharging and over-discharging states are cleared during cascaded communication of multiple cells, a dedicated terminal is required for communication between multiple protection ICs regarding the status of the external voltage input terminal, which serves as the voltage VM terminal.

[0008] Therefore, in such existing circuits, the chip size and the number of pins in the package sometimes increase due to the increase in pads.

[0009] This disclosure was made in view of this situation, and its object is to provide a charge-discharge control circuit, charge-discharge control device, and battery device that can suppress the circuit size when multiple protection ICs are cascaded.

[0010] [Technical means to solve the problem]

[0011] One embodiment is a charge / discharge control circuit, comprising: a battery, with a plurality of cells including a first cell and a second cell connected in series; a first predetermined state detection unit for detecting a first predetermined state of the first cell; a first logic circuit for performing first control based on the detection result of the first predetermined state detection unit; a second predetermined state detection unit for detecting a second predetermined state of the second cell; a charger connection detection unit for detecting whether the battery is connected to the charger; and a second logic circuit for performing second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and a first notification from the first logic circuit indicating the first predetermined state, wherein the first predetermined state and the second predetermined state are an overcharge state or an over-discharge state, and when the detection result of the charger connection detection unit meets predetermined conditions, the second logic circuit blocks the first notification from the first logic circuit and performs the second control.

[0012] [The effects of the invention]

[0013] This disclosure enables the reduction of circuit size in charge / discharge control circuits, charge / discharge control devices, and battery devices when multiple protection ICs are cascaded. Attached Figure Description

[0014] Figure 1A This is a diagram illustrating the structure of the charge / discharge control circuit, charge / discharge control device, and battery device according to the embodiment, as well as the first state of the battery device.

[0015] Figure 1B This is a diagram illustrating the structure of the charge / discharge control circuit, charge / discharge control device, and battery device according to the embodiment, as well as the first state of the battery device.

[0016] Figure 2A This is a diagram showing the second state of the battery device according to the embodiment.

[0017] Figure 2B This is a diagram showing the second state of the battery device according to the embodiment.

[0018] Figure 3A This is a diagram showing the third state of the battery device according to the embodiment.

[0019] Figure 3B This is a diagram showing the third state of the battery device according to the embodiment.

[0020] Figure 4A This is a diagram showing the fourth state of the battery device according to the embodiment.

[0021] Figure 4B This is a diagram showing the fourth state of the battery device according to the embodiment.

[0022] Figure 5 (A) to Figure 5 (H) is a diagram representing an example of a timing diagram related to overcharging in an implementation.

[0023] Figure 6 (A) to Figure 6 (H) is a diagram representing an example of a timing diagram related to over-discharge in an implementation.

[0024] Figure 7A This is a diagram illustrating the structure of the comparative example's charge / discharge control circuit, charge / discharge control device, and battery device, as well as the first state of the battery device.

[0025] Figure 7B This is a diagram illustrating the structure of the comparative example's charge / discharge control circuit, charge / discharge control device, and battery device, as well as the first state of the battery device.

[0026] Figure 8A This is a diagram showing the second state of the battery device in the comparative example.

[0027] Figure 8B This is a diagram showing the second state of the battery device in the comparative example.

[0028] Figure 9A This is a diagram showing the third state of the battery device in the comparative example.

[0029] Figure 9B This is a diagram showing the third state of the battery device in the comparative example.

[0030] Figure 10A This is a diagram showing the fourth state of the battery device in the comparative example.

[0031] Figure 10B This is a diagram showing the fourth state of the battery device in the comparative example.

[0032] Figure 11A This is a diagram showing the fifth state of the battery device in the comparative example.

[0033] Figure 11B This is a diagram showing the fifth state of the battery device in the comparative example.

[0034] Figure 12A This is a diagram showing the sixth state of the battery device in the comparative example.

[0035] Figure 12B This is a diagram showing the sixth state of the battery device in the comparative example.

[0036] Figure 13 (A) to Figure 13 (I) is a diagram representing an example of a timing diagram related to overcharge for a comparative example.

[0037] Figure 14 (A) to Figure 14 (I) is a diagram representing an example of a timing diagram related to over-discharge in a comparative example.

[0038] Figure 15 (A) to Figure 15 (H) is a diagram representing the removal of the overcharge and over-discharge states in the reference example.

[0039] Explanation of icon numbers

[0040] 10, 310: Battery device

[0041] 11: Battery

[0042] 11A, 11B: Battery section

[0043] 13: Short-circuit load

[0044] 14, 71A, 71B, 72A, 72B: Switches

[0045] 20, 320: Charge / discharge control device

[0046] 21: FET for discharge control

[0047] 22: FET for charging control

[0048] 30, 30A, 30B, 330, 330A, 330B: Charge / discharge control circuit

[0049] 40: Charger

[0050] 51A, 52A, 53A, 51B, 52B, 53B: Trapezoidal resistors for over-discharge detection

[0051] 54A, 55A, 56A, 54B, 55B, 56B: Trapezoidal resistors for overcharge detection

[0052] 62A, 562A: First logic circuit

[0053] 62B, 562B: Second Logic Circuit

[0054] 81A, 81B: Over-discharge detection comparators

[0055] 82A, 82B: Overcharge detection comparators

[0056] 91A, 91B: Discharge control signal detection circuit

[0057] 92A, 92B: Charging control signal detection circuit

[0058] 93A, 93B: Discharge control signal output circuit

[0059] 94A, 94B: Charging control signal output circuit

[0060] 95A, 95B: Charger connection detection circuit

[0061] 111A: First battery cell

[0062] 111B: Second cell

[0063] 511A, 511B: Charger connection detection signal output circuit

[0064] 1011, 1012, 1013, 1014, 1015, 1111, 1112, 1113, 1114, 1115, 1211, 1212, 1213, 1214, 1215, 1216, 1311, 1312, 1313, 1314, 1315, 1316, 2011, 2012, 2013, 2014, 2015: Characteristics

[0065] 2111, 2112: Status deactivated

[0066] a1, a2, a3, a4, a5, a6: symbols

[0067] C1A, C1B, C2A, C2B: Power input terminals

[0068] C4A, C4B: External voltage input terminals

[0069] C5A, C5B: FET gate connection terminals for discharge control

[0070] C6A, C6B: FET gate connection terminals for charging control

[0071] C7A, C7B: DO terminal output control terminals

[0072] C8A, C8B: CO terminal output control terminals

[0073] C11A, C11B, C12A, C12B: Voltage connection terminals

[0074] C31A, C31B: Charger connection signal output terminal

[0075] t1, t2, t3, t4, t5, t6, t11, t12, t13, t14, t15, t16, t21, t22, t23, t24, t25, t26, t27, t31, t32, t33, t34, t35, t36, t37: time

[0076] tCU: Overcharge detection delay time

[0077] tCL: Overcharge release delay time

[0078] tCTLC: CTLC terminal detection delay time

[0079] tCTLD: CTLD terminal detection delay time

[0080] tDL: Over-discharge detection delay time

[0081] tDU: Over-discharge release delay time

[0082] tRCTLC: CTLC terminal release delay time

[0083] tRCTLD: CTLD terminal release delay time

[0084] VBATn, VC(n), VC(n+1), VCO, VCOH, VCTLC, VCTLD, VDD, VDO, VDOH, VEB, VM, VMO, VMOL, VSS: Voltage

[0085] VCHG: Charger detection voltage

[0086] VCL: Overcharge release voltage

[0087] VCTLCDET: CTLC terminal detection voltage

[0088] VCTLDDET: CTLD terminal detection voltage

[0089] VCU: Overcharge detection voltage

[0090] VDL: Over-discharge detection voltage

[0091] VDU: Over-discharge release voltage Detailed Implementation

[0092] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0093] [Battery Device]

[0094] Figure 1A and Figure 1B This is a diagram illustrating the structural example of the charge / discharge control circuit 30, the charge / discharge control device 20, and the battery device 10 in the embodiment, as well as the first state of the battery device 10.

[0095] The battery device 10 includes a charge / discharge control device 20 and a battery 11.

[0096] The charge / discharge control device 20 includes a charge / discharge control circuit 30, a field-effect transistor (FET) 21 for discharge control, and a FET 22 for charge control.

[0097] in addition, Figure 1A The diagram shows a short-circuit load 13 (RLOAD), a switch 14, and a charger 40.

[0098] Furthermore, for ease of illustration, the battery device is divided into 10 parts. Figure 1A and Figure 1B They are used to represent things, but they are a single, integrated device.

[0099] Figure 1A The lines of symbols a1 to a5 shown are... Figure 1B The lines connecting symbols a1 to a5 are shown.

[0100] The charge and discharge control device 20 controls the charging and discharging of the battery 11.

[0101] Discharge control is achieved using FET 21.

[0102] Charging is controlled using FET 22.

[0103] In this embodiment, the charge / discharge control circuit 30 includes a multi-stage charge / discharge control circuit.

[0104] In this embodiment, the charge / discharge control circuit 30 includes three or more levels of charge / discharge control circuitry, but... Figure 1A and Figure 1B In the example, for the sake of simplicity, the lowest-level charge / discharge control circuit 30B and its upper-level charge / discharge control circuit 30A are shown.

[0105] The charge and discharge control circuit (not shown) that is higher up than the charge and discharge control circuit 30A has the same circuit structure as the charge and discharge control circuit 30A, but the highest charge and discharge control circuit (not shown) does not include the discharge control signal detection circuit and the charging control signal detection circuit (i.e., the communication circuit with its higher-level circuit).

[0106] However, the charge / discharge control circuit 30 can also be a two-stage charge / discharge control circuit including charge / discharge control circuit 30A and charge / discharge control circuit 30B.

[0107] In this embodiment, regarding the battery 11, the portion corresponding to the charge / discharge control circuit 30A is shown as battery section 11A, and the portion corresponding to the charge / discharge control circuit 30B is shown as battery section 11B.

[0108] In this embodiment, for ease of explanation, the charge / discharge control circuit 30A is referred to as the upper-level IC, and the charge / discharge control circuit 30B is referred to as the lower-level IC.

[0109] In this embodiment, these ICs are an example of multiple protection ICs.

[0110] The charge / discharge control circuit 30A includes: over-discharge detection trapezoidal resistors 51A to 53A, switch 71A, over-charge detection trapezoidal resistors 54A to 56A, switch 72A, over-discharge detection comparator 81A, over-charge detection comparator 82A, first logic circuit 62A, discharge control signal detection circuit 91A, charge control signal detection circuit 92A, discharge control signal output circuit 93A, and charge control signal output circuit 94A.

[0111] The battery section 11A has multiple cells connected in series.

[0112] exist Figure 1A In the example, to simplify the illustration, for the first cell 111A among the multiple cells of the battery section 11A, the following circuits are shown: over-discharge detection trapezoidal resistors 51A to 53A, switch 71A, over-charge detection trapezoidal resistors 54A to 56A, switch 72A, over-discharge detection comparator 81A, and over-charge detection comparator 82A. However, the same circuitry is included for the other cells of the battery section 11A.

[0113] Here, in this embodiment, the operation of the first logic circuit 62A is described with reference to a first battery cell 111A, but the same circuit structure can be used for other battery cells, and control based on the first logic circuit 62A can be performed.

[0114] The charge / discharge control circuit 30A includes: a power input terminal C1A as a terminal for voltage VDD, a power input terminal C2A as a terminal for voltage VSS, a voltage connection terminal C11A as a terminal for voltage VC(n), a voltage connection terminal C12A as a terminal for voltage VC(n+1), a FET gate connection terminal C5A as a terminal for voltage VDO, a FET gate connection terminal C6A as a terminal for voltage VCO, a discharge output (DO) terminal output control terminal C7A as a terminal for voltage VCTLD, and a charge output (CO) terminal output control terminal C8A as a terminal for voltage VCTLC.

[0115] Here, in the charge / discharge control circuit 30A, voltage VC(n) represents the cell at the nth stage (n is an integer greater than or equal to 1) (in Figure 1A and Figure 1B In the example, the positive voltage of the first cell (111A) is represented by , and the negative voltage of the cell in the (n-1)th stage is represented by .

[0116] Additionally, voltage VC(n+1) represents the positive terminal voltage of the (n+1)th stage cell, and represents the voltage of the nth stage cell (in... Figure 1A In the example, the negative voltage of the first cell (111A) is shown.

[0117] Furthermore, for the first-stage cell (when n=1) and the final-stage cell (when n is at its maximum), there are no adjacent cells for either one.

[0118] The charge / discharge control circuit 30B includes: over-discharge detection trapezoidal resistors 51B to 53B, switch 71B, over-charge detection trapezoidal resistors 54B to 56B, switch 72B, over-discharge detection comparator 81B, over-charge detection comparator 82B, second logic circuit 62B, discharge control signal detection circuit 91B, charging control signal detection circuit 92B, discharge control signal output circuit 93B, charging control signal output circuit 94B, and charger connection detection circuit 95B.

[0119] Battery section 11B has multiple cells connected in series.

[0120] exist Figure 1B In the example, to simplify the illustration, for the second cell 111B, one of the multiple cells in the battery section 11B, the following circuits are shown: over-discharge detection trapezoidal resistors 51B to 53B, switch 71B, over-charge detection trapezoidal resistors 54B to 56B, switch 72B, over-discharge detection comparator 81B, and over-charge detection comparator 82B. However, the same circuitry is included for the other cells in the battery section 11B.

[0121] Here, in this embodiment, the operation of the second logic circuit 62B is described with reference to a second battery cell 111B. However, the same circuit structure can be used for other battery cells, and control based on the second logic circuit 62B can be performed.

[0122] The charge / discharge control circuit 30B includes: a power input terminal C1B as a terminal for voltage VDD, a power input terminal C2B as a terminal for voltage VSS, a voltage connection terminal C11B as a terminal for voltage VC(n), a voltage connection terminal C12B as a terminal for voltage VC(n+1), a discharge control FET gate connection terminal C5B as a terminal for voltage VDO, a charge control FET gate connection terminal C6B as a terminal for voltage VCO, a DO terminal output control terminal C7B as a terminal for voltage VCTLD, a CO terminal output control terminal C8B as a terminal for voltage VCTLC, and an external voltage input terminal C4B as a terminal for voltage VM.

[0123] Here, in the charge / discharge control circuit 30B, voltage VC(n) represents the cell at the nth (n is an integer greater than or equal to 1) level (in... Figure 1B In the example, the positive voltage of the second cell (111B) is represented, and the negative voltage of the cell of the (n-1)th stage is represented.

[0124] Additionally, voltage VC(n+1) represents the positive terminal voltage of the (n+1)th stage cell, and represents the voltage of the nth stage cell (in... Figure 1B In the example, the negative voltage of the second cell (111B) is shown.

[0125] Furthermore, for the first-stage cell (when n=1) and the final-stage cell (when n is at its maximum), there are no adjacent cells for either one.

[0126] <Circuit connection relationships, etc.>

[0127] Between the positive and negative sides of the battery 11, a switch 14, a charger 40, a charging control FET 22, and a discharging control FET 21 are connected in order from the positive side to the negative side.

[0128] In addition, a short-circuit load 13 (RLOAD) is connected in parallel between the positive and negative terminals of the battery 11 and the switch 14 and the charger 40 as a short-circuit resistor.

[0129] Here, the source (S) of the charging control FET 22 is connected to the negative terminal of the charger 40, the drain (D) of the charging control FET 22 is connected to the drain (D) of the discharging control FET 21, and the source (S) of the discharging control FET 21 is connected to the negative terminal of the battery 11.

[0130] The gate (G) of the discharge control FET 21 is connected to the gate connection terminal C5B of the discharge control FET.

[0131] The gate (G) of the FET 22 for charging control is connected to the gate connection terminal C6B of the FET for charging control.

[0132] The point between the charger 40 and the charging control FET 22 is connected to the external voltage input terminal C4B.

[0133] The connection relationships of the circuits related to the charge and discharge control circuit 30A are explained.

[0134] Between the voltage connection terminal C11A on the power input terminal C1A side and the voltage connection terminal C12A on the power input terminal C2A side, in order from the positive side to the negative side, over-discharge detection trapezoidal resistors 51A, 52A, and 53A are connected, and over-charge detection trapezoidal resistors 54A, 55A, and 56A are connected in parallel with them.

[0135] The over-discharge detection trapezoidal resistor 52A is connected in parallel with the switch 71A.

[0136] An overcharge detection trapezoidal resistor of 55A is connected in parallel with a switch of 72A.

[0137] The first logic circuit 62A controls switches 71A and 72A.

[0138] The point between the over-discharge detection trapezoidal resistor 52A and the over-discharge detection trapezoidal resistor 53A is connected to the input terminal of the over-discharge detection comparator 81A.

[0139] The output of the over-discharge detection comparator 81A is connected to one input of the first logic circuit 62A.

[0140] The point between the overcharge detection trapezoidal resistor 55A and the overcharge detection trapezoidal resistor 56A is connected to the input terminal of the overcharge detection comparator 82A.

[0141] The output of the overcharge detection comparator 82A is connected to one input of the first logic circuit 62A.

[0142] The DO terminal output control terminal C7A is connected to the input terminal of the discharge control signal detection circuit 91A.

[0143] The output of the discharge control signal detection circuit 91A is connected to one input of the first logic circuit 62A.

[0144] The CO terminal output control terminal C8A is connected to the input terminal of the charging control signal detection circuit 92A.

[0145] The output of the charging control signal detection circuit 92A is connected to one input of the first logic circuit 62A.

[0146] The input terminal of the discharge control signal output circuit 93A is connected to one output terminal of the first logic circuit 62A.

[0147] The output terminal of the discharge control signal output circuit 93A is connected to the gate connection terminal C5A of the FET for discharge control.

[0148] The input terminal of the charging control signal output circuit 94A is connected to one output terminal of the first logic circuit 62A.

[0149] The output terminal of the charging control signal output circuit 94A is connected to the gate connection terminal C6A of the FET for charging control.

[0150] The connection relationship between the charge / discharge control circuit 30A and the charge / discharge control circuit 30B is explained.

[0151] The discharge control FET gate connection terminal C5A of the charge / discharge control circuit 30A is connected to the DO terminal output control terminal C7B of the charge / discharge control circuit 30B.

[0152] The charging control FET gate connection terminal C6A of the charging control circuit 30A is connected to the CO terminal output control terminal C8B of the charging control circuit 30B.

[0153] The connection relationships of the circuits related to the charge and discharge control circuit 30B are explained.

[0154] Between the voltage connection terminal C11B on the power input terminal C1B side and the voltage connection terminal C12B on the power input terminal C2B side, in order from the positive side to the negative side, there are over-discharge detection trapezoidal resistors 51B, 52B, and 53B, and in parallel thereare over-charge detection trapezoidal resistors 54B, 55B, and 56B.

[0155] The over-discharge detection trapezoidal resistor 52B is connected in parallel with the switch 71B.

[0156] The overcharge detection trapezoidal resistor 55B is connected in parallel with the switch 72B.

[0157] The second logic circuit 62B controls switches 71B and 72B.

[0158] The point between the over-discharge detection trapezoidal resistor 52B and the over-discharge detection trapezoidal resistor 53B is connected to the input terminal of the over-discharge detection comparator 81B.

[0159] The output of the over-discharge detection comparator 81B is connected to one input of the second logic circuit 62B.

[0160] The point between the overcharge detection trapezoidal resistor 55B and the overcharge detection trapezoidal resistor 56B is connected to the input terminal of the overcharge detection comparator 82B.

[0161] The output of the overcharge detection comparator 82B is connected to one input of the second logic circuit 62B.

[0162] The DO terminal output control terminal C7B is connected to the input terminal of the discharge control signal detection circuit 91B.

[0163] The output of the discharge control signal detection circuit 91B is connected to one input of the second logic circuit 62B.

[0164] The CO terminal output control terminal C8B is connected to the input terminal of the charging control signal detection circuit 92B.

[0165] The output of the charging control signal detection circuit 92B is connected to one input of the second logic circuit 62B.

[0166] The input terminal of the discharge control signal output circuit 93B is connected to one output terminal of the second logic circuit 62B.

[0167] The output terminal of the discharge control signal output circuit 93B is connected to the gate connection terminal C5B of the FET for discharge control.

[0168] The input terminal of the charging control signal output circuit 94B is connected to one output terminal of the second logic circuit 62B.

[0169] The output terminal of the charging control signal output circuit 94B is connected to the gate connection terminal C6B of the FET for charging control.

[0170] The input terminal of the charger connection detection circuit 95B is connected to the external voltage input terminal C4B.

[0171] The output of the charger connection detection circuit 95B is connected to one input of the second logic circuit 62B.

[0172] <First State: Explanation of Overcharge State Removal During Cascaded Communication>

[0173] Figure 1A and Figure 1B The first state of the battery device 10 is shown.

[0174] Switch 14 is controlled to be in a closed (short circuit) state. Thus, battery device 10 is connected to charger 40.

[0175] The state of the 30A charge / discharge control circuit is explained.

[0176] Under normal conditions, the voltage VBATn of the first cell 111A is higher than the overcharge release voltage VCL and lower than the overcharge detection voltage VCU.

[0177] Here, when the voltage VBATn of the first cell 111A exceeds the overcharge detection voltage VCU, the first logic circuit 62A is in an overcharge state.

[0178] The output of the over-discharge detection comparator 81A is in the deactivated state.

[0179] The output of the overcharge detection comparator 82A is in the deactivated state.

[0180] The output of the discharge control signal detection circuit 91A is in the off state.

[0181] The output of the charging control signal detection circuit 92A is in the off state.

[0182] The first logic circuit 62A controls the switch 71A to be in the on state by using the over-discharge state release signal.

[0183] The first logic circuit 62A controls the switch 72A to be in the on state by using the overcharge state release signal.

[0184] The output terminal of the discharge control signal output circuit 93A is in a deactivated state through the first logic circuit 62A.

[0185] The output terminal of the charging control signal output circuit 94A is in a detection state through the first logic circuit 62A and outputs a charging control signal.

[0186] The state of the charge / discharge control circuit 30B is explained.

[0187] The voltage VM is below 0 [V] (VM < 0). Therefore, the output of the charger connection detection circuit 95B is in a detection state.

[0188] The voltage VBATn of the second cell 111B is higher than the over-discharge detection voltage VDL and lower than the overcharge release voltage VCL.

[0189] The output of the over-discharge detection comparator 81B is in the deactivated state.

[0190] The output of the overcharge detection comparator 82B is in the off state.

[0191] The output of the discharge control signal detection circuit 91B is in the off state.

[0192] The output of the charging control signal detection circuit 92B is in a detection state.

[0193] Therefore, the second logic circuit 62B is in the charging control state.

[0194] The second logic circuit 62B controls the switch 71B to be in the on state by using the over-discharge state release signal.

[0195] The second logic circuit 62B controls the switch 72B to be in the off state by using the overcharge state release signal.

[0196] The output terminal of the discharge control signal output circuit 93B is in a deactivated state through the second logic circuit 62B.

[0197] Therefore, the discharge control FET 21 is controlled to be in the on state.

[0198] The output terminal of the charging control signal output circuit 94B is in a detection state through the second logic circuit 62B and outputs a charging control signal.

[0199] Therefore, the charging control FET 22 is controlled to be in the off state.

[0200] Thus, when the voltage VBATn of the first cell 111A connected to the upper IC exceeds the overcharge detection voltage VCU, the upper IC (charge and discharge control circuit 30A) switches to an overcharge state.

[0201] In the lower-level IC (charge / discharge control circuit 30B), the detection signal is input to the CO terminal of the lower-level IC to output the control terminal C8B, and the second logic circuit 62B switches to the charging control state. Thus, the charging control FET 22 is turned off through the second logic circuit 62B.

[0202] By stopping charging, the voltage VBATn of the first cell 111A drops slightly and becomes less than the overcharge detection voltage VCU.

[0203] <Second State: Explanation of Overcharge State Removal during Cascaded Communication>

[0204] Figure 2A and Figure 2B This is a diagram showing the second state of the battery device 10 according to the embodiment.

[0205] The changes relative to the first state are explained.

[0206] Switch 14 is controlled to be in the open (OPEN) state. Thus, the charger 40 is not connected to the battery device 10 (disconnected state).

[0207] The voltage VM is higher than 0 [V] (VM>0). Therefore, the output of the charger connection detection circuit 95B is in a deactivated state.

[0208] The second logic circuit 62B is in its normal state.

[0209] The output terminal of the charging control signal output circuit 94B is in a deactivated state through the second logic circuit 62B.

[0210] Therefore, the FET 22 for charging control is controlled to be turned on.

[0211] Thus, by removing the charger 40, the voltage VM increases.

[0212] Therefore, the charger connection detection circuit 95B of the lower-level IC outputs a release signal. Simultaneously, the second logic circuit 62B blocks the detection signal from the output of the charging control signal detection circuit 92B and returns to its normal state. Then, the second logic circuit 62B turns on the charging control FET 22.

[0213] Here, the second logic circuit 62B maintains the detection signal of the shielded CO terminal output control terminal C8B when the voltage VM is higher than 0 [V] (when the charger 40 is open).

[0214] In addition, the overcharge state of the first logic circuit 62A is maintained in the upper-level IC.

[0215] That is, in the examples of the first state and the second state, the overcharge state is detected in the upper-level IC, for example, after the power is turned on, and the overcharge state is maintained after the power is notified to the lower-level IC.

[0216] In this embodiment, since the shielding is performed by software in the lower-level IC, complex circuitry may not be required.

[0217] <Third State: Explanation of Over-Discharge State Removal during Cascaded Communication>

[0218] Figure 3A and Figure 3B This is a diagram showing the third state of the battery device 10 according to the embodiment.

[0219] Switch 14 is controlled to be in the OPEN state. Thus, the charger 40 is not connected to the battery device 10 (disconnected state).

[0220] The state of the 30A charge / discharge control circuit is explained.

[0221] Under normal conditions, the voltage VBATn of the first cell 111A is higher than the over-discharge detection voltage VDL and lower than the over-discharge release voltage VDU.

[0222] Here, when the voltage VBATn of the first cell 111A is less than the over-discharge detection voltage VDL, the first logic circuit 62A is in an over-discharge state.

[0223] The output of the over-discharge detection comparator 81A is in the detection state.

[0224] The output of the overcharge detection comparator 82A is in the deactivated state.

[0225] The output of the discharge control signal detection circuit 91A is in the off state.

[0226] The output of the charging control signal detection circuit 92A is in the off state.

[0227] The first logic circuit 62A controls the switch 71A to be in the off state through the over-discharge state release signal.

[0228] The first logic circuit 62A controls the switch 72A to be in the on state by using the overcharge state release signal.

[0229] The output terminal of the discharge control signal output circuit 93A is in a detection state through the first logic circuit 62A and outputs a discharge control signal.

[0230] The output terminal of the charging control signal output circuit 94A is in a deactivated state through the first logic circuit 62A.

[0231] The state of the charge / discharge control circuit 30B is explained.

[0232] The voltage VM is higher than 0 [V] (VM>0). Therefore, the output of the charger connection detection circuit 95B is in a deactivated state.

[0233] The voltage VBATn of the second cell 111B is higher than the over-discharge detection voltage VDL and lower than the overcharge release voltage VCL.

[0234] The output of the over-discharge detection comparator 81B is in the deactivated state.

[0235] The output of the overcharge detection comparator 82B is in the off state.

[0236] The output of the discharge control signal detection circuit 91B is in a detection state.

[0237] The output of the charging control signal detection circuit 92B is in the off state.

[0238] The second logic circuit 62B is in discharge control mode.

[0239] The second logic circuit 62B controls the switch 71B to be in the on state by using the over-discharge state release signal.

[0240] The second logic circuit 62B controls the switch 72B to be in the off state by using the overcharge state release signal.

[0241] The output terminal of the discharge control signal output circuit 93B is in a detection state through the second logic circuit 62B and outputs a discharge control signal.

[0242] Therefore, the discharge control FET 21 is controlled to be in the off state.

[0243] The output terminal of the charging control signal output circuit 94B is in a deactivated state through the second logic circuit 62B.

[0244] Therefore, the FET 22 for charging control is controlled to be turned on.

[0245] Thus, when the first cell 111A connected to the host IC is lower than the over-discharge detection voltage VDL, the first logic circuit 62A switches to an over-discharge state.

[0246] The detection signal is input to the DO terminal of the lower-level IC, which outputs the control terminal C7B. The second logic circuit 62B then switches to the discharge control state. Consequently, the discharge control FET 21 is turned off via the second logic circuit 62B.

[0247] By stopping the discharge, the voltage VBATn of the first cell 111A rises slightly, exceeding the over-discharge release voltage VDU.

[0248] <Fourth State: Explanation of Over-Discharge State Removal during Cascaded Communication>

[0249] Figure 4A and Figure 4B This is a diagram showing the fourth state of the battery device 10 according to the embodiment.

[0250] The changes relative to the third state are explained.

[0251] Switch 14 is controlled to be in the closed (SHORT) state. Thus, battery device 10 is connected to charger 40.

[0252] The voltage VM is below 0 [V] (VM < 0). Therefore, the output of the charger connection detection circuit 95B is in a detection state.

[0253] The second logic circuit 62B is in its normal state.

[0254] The output terminal of the discharge control signal output circuit 93B is in a deactivated state through the second logic circuit 62B.

[0255] Therefore, the discharge control FET 21 is controlled to be in the on state.

[0256] Thus, by connecting the charger 40, the voltage VM is reduced.

[0257] Therefore, the charger connection detection circuit 95B of the lower-level IC outputs a detection signal. Simultaneously, the second logic circuit 62B shields the detection signal from the output of the discharge control signal detection circuit 91B and transitions to a normal state. Then, the second logic circuit 62B turns on the discharge control FET 21.

[0258] Here, the second logic circuit 62B maintains the detection signal of the control terminal C7B at the shielded DO terminal when the voltage VM is below 0 [V] (when the charger 40 is connected).

[0259] In addition, the over-discharge state of the first logic circuit 62A is maintained in the upper-level IC.

[0260] That is, in the examples of the third and fourth states, the over-discharge state is detected in the upper-level IC, for example, after the power is turned on, and then the over-discharge state is maintained after the power is notified to the lower-level IC.

[0261] In this embodiment, since the shielding is performed by software in the lower-level IC, complex circuitry may not be required.

[0262] <An example of a timing diagram for overcharging>

[0263] Figure 5 (A) to Figure 5 (H) is a diagram representing an example of a timing diagram related to overcharging in an implementation.

[0264] exist Figure 5 (A) to Figure 5 Five charts are shown in (H).

[0265] In the five charts, each horizontal axis represents time, and they all represent the same time period. Time periods t1 to t6 are shown.

[0266] In the five charts, each vertical axis represents voltage.

[0267] In addition, Figure 5 (A) to Figure 5 In the example of (H), (above) represents the state of the upper-side charge-discharge control circuit 30A, and (below) represents the state of the lower-side charge-discharge control circuit 30B.

[0268] Figure 5 The graph (A) shows the voltage VBATn characteristic 1011 of the first cell 111A of the host IC.

[0269] In the graph, the vertical axis shows the overcharge detection voltage VCU and the overcharge release voltage VCL.

[0270] Figure 5 The graph in (B) shows the voltage VCO characteristic 1012 of the FET gate connection terminal C6A for the charging control of the host IC.

[0271] In the graph, the vertical axis shows the voltage VCOH, which is the CO terminal voltage H, and the voltage VDD of the lower IC.

[0272] Additionally, the overcharge detection delay time tCU is schematically shown in the graph.

[0273] Figure 5 The graph (C) shows the voltage VM characteristic of the lower IC 1013.

[0274] In the graph, the vertical axis shows the charger detection voltage VCHG versus the voltage VEB-.

[0275] Figure 5 The diagram (D) shows the characteristic of the voltage VCTLC of the CO terminal output control terminal C8B of the lower IC 1014.

[0276] In the chart, the vertical axis shows the sum of voltage VDD and voltage VCOH (VDD+VCOH), the charge control (CTLC) terminal detection voltage VCTLCDET, and voltage VDD.

[0277] Figure 5 The graph (E) shows the characteristic of the voltage VCO at the FET gate connection terminal C6B of the lower-level IC for charging control 1015.

[0278] In the graph, the vertical axis represents the voltage VCOH.

[0279] Additionally, the diagram schematically illustrates the CTLC terminal detection delay time tCTLC and the CTLC terminal release delay time tRCTLC.

[0280] exist Figure 5 The presence or absence of a charger connection is indicated in (F).

[0281] exist Figure 5 The (G) indicates whether the state of the host IC is normal or overcharged.

[0282] exist Figure 5 The (H) indicates whether the lower-level IC is in a normal state or a charging control state.

[0283] Here, time t1 is the time when the charger 40 is connected to the battery device 10.

[0284] Time t2 is the time when the voltage VBATn of the first cell 111A of the host IC exceeds the overcharge detection voltage VCU.

[0285] Time t3 is the time it takes for the host IC to transition from the normal state to the overcharge state.

[0286] Time t4 is the time it takes for the lower-level IC to transition from the normal state to the charging control state.

[0287] Time t5 is the time when the charger is removed from the battery device 10 at time 40.

[0288] Time t6 is the time it takes for the lower-level IC to return from the charging control state to the normal state.

[0289] <Examples of timing diagrams related to over-discharge>

[0290] Figure 6 (A) to Figure 6 (H) is a diagram representing an example of a timing diagram related to over-discharge in an implementation.

[0291] exist Figure 6 (A) to Figure 6 Five charts are shown in (H).

[0292] In the five charts, each horizontal axis represents time, and they all represent common times. Time t11 to time t16 are shown.

[0293] In the five charts, each vertical axis represents voltage.

[0294] In addition, Figure 6 (A) to Figure 6 In the example of (H), (above) represents the state of the upper-side charge-discharge control circuit 30A, and (below) represents the state of the lower-side charge-discharge control circuit 30B.

[0295] Figure 6 The graph (A) shows the voltage VBATn characteristic of the first cell 111A of the host IC.

[0296] In the graph, the vertical axis shows the over-discharge release voltage VDU and the over-discharge detection voltage VDL.

[0297] Figure 6 The graph in (B) shows the characteristics of the voltage VDO at the gate connection terminal C5A of the FET for discharge control of the host IC 1112.

[0298] In the graph, the vertical axis shows the voltage VDOH, which is the voltage H of the DO terminal, and the voltage VDD of the lower IC.

[0299] Additionally, the over-discharge detection delay time tDL is schematically shown in the graph.

[0300] Figure 6 The graph (C) shows the voltage VM characteristic of the lower IC 1113.

[0301] In the graph, the vertical axis shows the charger detection voltage VCHG versus the voltage VEB-.

[0302] Figure 6 The diagram (D) shows the characteristic of the voltage VCTLD of the output control terminal C7B of the lower IC's DO terminal 1114.

[0303] In the chart, the vertical axis shows the sum of voltage VDD and voltage VDOH (VDD+VDOH), the discharge control (CTLD) terminal detection voltage VCTLDDET, and voltage VDD.

[0304] Figure 6 The graph (E) shows the characteristic of the voltage VDO at the FET gate connection terminal C5B for the discharge control of the lower IC 1115.

[0305] In the graph, the vertical axis represents the voltage VDOH.

[0306] Additionally, the diagram schematically illustrates the CTLD terminal detection delay time tCTLD and the CTLD terminal release delay time tRCTLD.

[0307] exist Figure 6 The presence or absence of a charger connection is indicated in (F).

[0308] exist Figure 6 The (G) indicates whether the state of the higher-level IC is normal or over-discharged.

[0309] exist Figure 6 The (H) indicates whether the state of the lower-level IC is normal or in discharge control state.

[0310] Here, time t11 is the time when the charger 40 is removed from the battery device 10.

[0311] Time t12 is the time when the voltage VBATn of the first cell 111A of the host IC is lower than the over-discharge detection voltage VDL.

[0312] Time t13 is the time it takes for the host IC to transition from the normal state to the over-discharge state.

[0313] Time t14 is the time it takes for the lower-level IC to transition from the normal state to the discharge control state.

[0314] Time t15 is the time when the charger 40 is connected to the battery device 10.

[0315] Time t16 is the time it takes for the lower-level IC to recover from the discharge control state to the normal state.

[0316] [Regarding the implementation method]

[0317] As described above, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 of this embodiment, the lower-level IC (charge / discharge control circuit 30B) shields the cascaded communication signals (charge control signal, discharge control signal) from the upper-level IC (charge / discharge control circuit 30A) based on the voltage VM of the external voltage input terminal C4B, thereby simulating the removal of the overcharge state and the removal of the over-discharge state.

[0318] For example, when in an overcharged state, the lower-level IC determines that the charger 40 is not connected when the voltage VM > 0 [V], and blocks the charging control signal (the signal that prohibits charging) from the upper-level IC, so that the charging control FET 22 is turned on.

[0319] For example, when in an over-discharge state, the lower-level IC determines that a charger 40 is connected when the voltage VM < 0 [V], and blocks the discharge control signal (discharge prohibition signal) from the upper-level IC, so that the discharge control FET21 is turned on.

[0320] Thus, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 of this embodiment, by shielding the cascaded communication signal according to the voltage VM, the state can be deactivated for overcharge and over-discharge without adding a dedicated terminal for the cascaded communication signal.

[0321] Therefore, in the charge / discharge control circuit 30, charge / discharge control device 20, and battery device 10 of this embodiment, the circuit size can be suppressed when multiple protection ICs are cascaded.

[0322] In this embodiment, for example, since no dedicated terminals for cascaded communication signals are required, the chip size and the number of pins in the package can be reduced compared to existing circuits. In this embodiment, for example, since no additional solder pads are added, the chip size can be reduced.

[0323] Furthermore, in this embodiment, since the lower-level IC does not rely on communication signals from the upper-level IC but controls the output based on the voltage VM, the FET (FET 22 for charging control or FET 21 for discharging control) can be turned on quickly compared to existing circuits, for example, when the overcharged or over-discharged state is resolved. This reduces the damage to the body diode (not shown) caused by the FET.

[0324] Here, a structural example of the charge / discharge control circuit 30, the charge / discharge control device 20, and the battery device 10 of this embodiment is shown.

[0325] The first logic circuit 62A performs first control based on the detection result of the first specified state detection unit.

[0326] The first specified condition detection unit detects the first specified condition of the first cell 111A.

[0327] The first specified state detection unit includes a first trapezoidal resistor, a first switch connected in parallel with the first trapezoidal resistor, and a first comparator connected to one end of the first trapezoidal resistor. With this structure, the first specified state detection unit can perform operations related to overcharging or over-discharging.

[0328] The first logic circuit 62A performs control such as controlling the on / off state of the first switch based on the output from the first comparator.

[0329] The second logic circuit 62B performs second control based on the detection results of the second specified state detection unit, the detection results of the charger connection detection unit, and the cascaded communication signal (containing the first notification of the first specified state) from the first logic circuit 62A.

[0330] The charger connection detection unit (charger connection detection circuit 95B) detects whether the battery 11 is connected to the charger 40.

[0331] The second specified condition detection unit detects the second specified condition of the second cell 111B.

[0332] The second specified state detection unit includes a second trapezoidal resistor, a second switch connected in parallel with the second trapezoidal resistor, and a second comparator connected to one end of the second trapezoidal resistor. With this structure, the second specified state detection unit can perform operations related to overcharging or over-discharging.

[0333] The second logic circuit 62B performs control such as controlling the on / off state of the second switch based on the output from the second comparator.

[0334] When the detection result of the charger connection detection unit meets the specified conditions, the second logic circuit 62B shields (invalidates) the first notification from the first logic circuit 62A and performs the second control.

[0335] By using the second logic circuit 62B to shield the first notification, for example, it is possible to avoid the need for dedicated terminals for additional cascaded communication signals.

[0336] As an example, the first defined state is the overcharge state.

[0337] In this case, the specified conditions include the condition of removing the charger 40 from the battery 11.

[0338] The second control based on the second logic circuit 62B includes control to turn on the FET 22 for charging control.

[0339] Additionally, on the first logic circuit 62A side, regarding the overcharge state, the first trapezoidal resistor is an overcharge detection trapezoidal resistor 54A to an overcharge detection trapezoidal resistor 56A, the first switch is a switch 72A, and the first comparator is an overcharge detection comparator 82A.

[0340] Additionally, on the second logic circuit 62B side, regarding the overcharge state, the second trapezoidal resistor is the overcharge detection trapezoidal resistor 54B to the overcharge detection trapezoidal resistor 56B, the second switch is the switch 72B, and the second comparator is the overcharge detection comparator 82B.

[0341] This structure enables the removal of the overcharged state.

[0342] Furthermore, the state release related to the overcharge state in this embodiment (the state release of the overcharge state performed by the second logic circuit 62B using shielding) can be called by any name, such as VCU release, etc.

[0343] As another example, the first defined state is the over-discharge state.

[0344] In this case, the specified conditions include the condition that the charger 40 is connected to the battery 11.

[0345] The second control based on the second logic circuit 62B includes control to turn on the FET 21 for discharge control.

[0346] Additionally, on the first logic circuit 62A side, regarding the over-discharge state, the first trapezoidal resistor is an over-discharge detection trapezoidal resistor 51A to an over-discharge detection trapezoidal resistor 53A, the first switch is a switch 71A, and the first comparator is an over-discharge detection comparator 81A.

[0347] Additionally, on the second logic circuit 62B side, regarding the over-discharge state, the second trapezoidal resistor is the over-discharge detection trapezoidal resistor 51B to the over-discharge detection trapezoidal resistor 53B, the second switch is the switch 71B, and the second comparator is the over-discharge detection comparator 81B.

[0348] This structure enables the removal of the over-discharge state.

[0349] Furthermore, the state release related to the over-discharge state in this embodiment (the state release of the over-discharge state performed by the second logic circuit 62B using shielding) can be called by any name, for example, it can also be called VDL release, etc.

[0350] Here, structural examples for when the first defined state is an overcharged state and structural examples for when the first defined state is an over-discharged state are described. However, structures corresponding to the overcharged state and the over-discharged state can also be used as in this embodiment.

[0351] Alternatively, a structure corresponding to either the structure example when the first specified state is an overcharged state or the structure example when the first specified state is an over-discharged state may be used.

[0352] [Explanation of the comparative examples]

[0353] Reference Figure 7A and Figures 7B to 12A and Figure 12B , Figure 13 (A) ~ Figure 14 (I) will explain the comparative examples.

[0354] Furthermore, for ease of explanation, in Figure 7A and Figures 7B to 12A and Figure 12B In the middle, to and Figure 1A and Figures 1B to 4A and Figure 4B The same components are labeled with the same symbols for explanation.

[0355] Figure 7A and Figure 7B This is a diagram showing the structural example of the charge / discharge control circuit 330, the charge / discharge control device 320, and the battery device 310 of the comparative example, as well as the first state of the battery device 310 (the first state of the comparative example).

[0356] With the battery device 10 of the embodiment ( Figure 1A and Figure 1B Compared to the example, the battery device 310 of the comparative example differs in that it includes charge / discharge control circuits 330A and 330B instead of the charge / discharge control circuits 30A and 30B of the battery device 10 of the embodiment.

[0357] Furthermore, for ease of illustration, the battery device 310 is divided into... Figure 7A and Figure 7B They are used to represent things, but they are a single, integrated device.

[0358] Figure 7A The lines shown, from symbols a1 to a6, are... Figure 7B The lines connecting symbols a1 to a6 are shown.

[0359] Compared to the charge / discharge control circuit 30B of the battery device 10 in the embodiment, the charge / discharge control circuit 330B differs in that it includes a charger connection detection signal output circuit 511B and a charger connection signal output terminal C31B, and includes a second logic circuit 562B instead of the second logic circuit 62B in the embodiment.

[0360] Compared to the charge / discharge control circuit 30A of the battery device 10 in the embodiment, the charge / discharge control circuit 330A differs in that it includes a charger connection detection circuit 95A and an external voltage input terminal C4A, as well as a charger connection detection signal output circuit 511A, and includes a first logic circuit 562A instead of the first logic circuit 62A in the embodiment.

[0361] The input terminal of the charger connection detection signal output circuit 511B is connected to one output terminal of the second logic circuit 562B.

[0362] The output terminal of the charger connection detection signal output circuit 511B is connected to the charger connection signal output terminal C31B.

[0363] The charger connection signal output terminal C31B of the lower-level IC (charge and discharge control circuit 330B) is connected to the external voltage input terminal C4A of the upper-level IC (charger connection signal output terminal C31A).

[0364] The external voltage input terminal C4A is connected to the input terminal of the charger connection detection circuit 95A.

[0365] The output of the charger connection detection circuit 95A is connected to one input of the first logic circuit 562A.

[0366] The input terminal of the charger connection detection signal output circuit 511A is connected to one output terminal of the first logic circuit 562A.

[0367] The output terminal of the charger connection detection signal output circuit 511A is connected to the charger connection signal output terminal C31A.

[0368] <Comparative Example, First State: Explanation of Overcharge State Removal During Cascaded Communication>

[0369] exist Figure 7A and Figure 7B The first state of the battery device 310 is shown in the figure.

[0370] In the first state of the comparative example, compared with this embodiment... Figure 1A and Figure 1B Compared to the first state of the battery device 10 shown, the charger connection detection signal output circuit 511B is in the detection state, the charger connection detection circuit 95A is in the detection state, the charger connection detection signal output circuit 511A is in the deactivated state, and the overcharge detection comparator 82A is in the detection state.

[0371] Here, when the first cell 111A connected to the host IC exceeds the overcharge detection voltage VCU, the first logic circuit 562A switches to an overcharge state.

[0372] The first logic circuit 562A controls the charging control signal output circuit 94A to a detection state and inputs the detection signal to the charging control signal detection circuit 92B of the lower-level IC. The second logic circuit 562B then switches to a charging control state. Consequently, the charging control FET 22 is controlled to be turned off via the second logic circuit 562B.

[0373] By stopping charging, the voltage VBATn of the first cell 111A drops slightly and becomes less than the overcharge detection voltage VCU.

[0374] <Comparative Example, Second State: Explanation of Overcharge State Removal During Cascaded Communication>

[0375] Figure 8A and Figure 8B This is a diagram showing the second state of the battery device 310 in the comparative example.

[0376] The changes relative to the first state are explained.

[0377] Switch 14 is controlled to be in the OPEN state. Thus, the battery device 310 and charger 40 are not connected (disconnected state).

[0378] The voltage VM is higher than 0 [V] (VM>0). Therefore, the output of the charger connection detection circuit 95B is in a deactivated state.

[0379] The charger connection detection signal output circuit 511B is deactivated via the second logic circuit 562B. Consequently, the charger connection detection circuit 95A is deactivated.

[0380] The first logic circuit 562A controls the switch 72A to be off.

[0381] Thus, by removing the charger 40, the voltage VM increases.

[0382] Therefore, the charger connection detection circuit 95B of the lower-level IC outputs a release signal. Simultaneously, the second logic circuit 562B puts the charger connection detection signal output circuit 511B in a released state, and outputs a release signal from the charger connection detection signal output circuit 511B.

[0383] The host IC cancels the overcharge state by turning off the switch 72A of the overcharge detection trapezoidal resistor 55A.

[0384] The overcharge detection comparator 82A is in the deactivated state and outputs a deactivation signal.

[0385] <Comparative Example, Third State: Explanation of Overcharge State Removal During Cascaded Communication>

[0386] Figure 9A and Figure 9B This is a diagram showing the third state of the battery device 310 in the comparative example.

[0387] The changes relative to the second state are explained.

[0388] The first logic circuit 562A is in normal state.

[0389] The output of the charging control signal output circuit 94A is deactivated via the first logic circuit 562A. Consequently, the output of the charging control signal detection circuit 92B is deactivated.

[0390] The second logic circuit 562B is in its normal state.

[0391] The output of the charging control signal output circuit 94B is deactivated via the second logic circuit 562B. Consequently, the charging control FET 22 is turned on.

[0392] Thus, after the overcharge detection comparator 82A outputs a cancellation signal, the host IC transitions to the normal state.

[0393] Therefore, a release signal is output from the charging control signal output circuit 94A and a release signal is output from the charging control signal detection circuit 92B.

[0394] The lower-level IC switches to the normal state, and the charging control is turned on by FET 22.

[0395] <Comparative Example, Fourth State: Explanation of Over-Discharge State Removal During Cascaded Communication>

[0396] Figure 10A and Figure 10B This is a diagram showing the fourth state of the battery device 310 in the comparative example.

[0397] In this example, compared with this embodiment Figure 3A and Figure 3B Compared to the third state of the battery device 10 shown, the charger connection detection signal output circuit 511B is in a deactivated state, the charger connection detection circuit 95A is in a deactivated state, and the charger connection detection signal output circuit 511A is in a deactivated state.

[0398] Here, when the first cell 111A connected to the host IC is lower than the over-discharge detection voltage VDL, the first logic circuit 562A switches to an over-discharge state.

[0399] The first logic circuit 562A controls the discharge control signal output circuit 93A to a detection state, and inputs the detection signal to the discharge control signal detection circuit 91B of the lower-level IC. The second logic circuit 562B then switches to a discharge control state. Thus, the second logic circuit 562B controls the discharge control FET 21 to a turned-off state.

[0400] By stopping the discharge, the voltage VBATn of the first cell 111A rises slightly and is higher than the over-discharge release voltage VDU.

[0401] <Comparative Example, Fifth State: Explanation of Over-Discharge State Removal During Cascaded Communication>

[0402] Figure 11A and Figure 11B This is a diagram showing the fifth state of the battery device 310 in the comparative example.

[0403] The changes relative to the fourth state are explained.

[0404] Switch 14 is controlled to be in the closed (SHORT) state. Thus, battery device 10 is connected to charger 40.

[0405] The voltage VM is below 0 [V] (VM < 0). Therefore, the output of the charger connection detection circuit 95B is in a detection state.

[0406] The charger connection detection signal output circuit 511B is controlled to a detection state by the second logic circuit 562B. Therefore, the charger connection detection circuit 95A is in a detection state.

[0407] The first logic circuit 562A controls the switch 71A to be turned on.

[0408] Thus, by connecting the charger 40, the voltage VM is reduced.

[0409] Therefore, the charger connection detection circuit 95B of the lower-level IC outputs a detection signal. Simultaneously, the second logic circuit 562B puts the charger connection detection signal output circuit 511B into a detection state, outputting a detection signal from the charger connection detection signal output circuit 511B.

[0410] The host IC cancels the over-discharge state by setting the switch 71A of the over-discharge detection trapezoidal resistor 52A to conduct.

[0411] The over-discharge detection comparator 81A is in the deactivated state and outputs a deactivated signal.

[0412] <Comparative Example, Sixth State: Explanation of Over-Discharge State Removal During Cascaded Communication>

[0413] The changes relative to the fifth state are explained.

[0414] Figure 12A and Figure 12B This is a diagram showing the sixth state of the battery device 310 in the comparative example.

[0415] The first logic circuit 562A is in normal state.

[0416] The output of the discharge control signal output circuit 93A is controlled to be in a deactivated state by the first logic circuit 562A. Consequently, the output of the discharge control signal detection circuit 91B is in a deactivated state.

[0417] The second logic circuit 562B is in its normal state.

[0418] The output of the discharge control signal output circuit 93B is deactivated via the second logic circuit 562B. This, in turn, activates the discharge control via FET 21.

[0419] Thus, after the over-discharge detection comparator 81A outputs a release signal, the host IC transitions to the normal state.

[0420] Therefore, a release signal is output from the discharge control signal output circuit 93A, and a release signal is output from the discharge control signal detection circuit 91B.

[0421] The lower-level IC switches to the normal state and controls the discharge control using FET 21 to be in the on state.

[0422] <Examples of timing diagrams related to overcharge in comparative examples>

[0423] Figure 13 (A) to Figure 13 (I) is a diagram representing an example of a timing diagram related to overcharge for a comparative example.

[0424] exist Figure 13 (A) to Figure 13 Six charts are shown in (I).

[0425] In the six charts, each horizontal axis represents time, and they all represent common times. Time t21 to time t27 are shown.

[0426] In the six charts, each vertical axis represents voltage.

[0427] In addition, Figure 13 (A) to Figure 13 In example (I), (above) represents the state of the upper-side charge-discharge control circuit 330A, and (below) represents the state of the lower-side charge-discharge control circuit 330B.

[0428] Figure 13 The graph (A) shows the voltage VBATn characteristic 1211 of the first cell 111A of the host IC.

[0429] In the graph, the vertical axis shows the overcharge detection voltage VCU and the overcharge release voltage VCL.

[0430] Figure 13 The graph in (B) shows the characteristic of the voltage VCO at the FET gate connection terminal C6A of the upper IC for charging control 1212.

[0431] In the graph, the vertical axis shows the voltage VCOH, which is the CO terminal voltage H, and the voltage VDD of the lower IC.

[0432] Additionally, the overcharge detection delay time tCU and the overcharge release delay time tCL are schematically shown in the diagram.

[0433] Figure 13 The graph (C) shows the voltage VM characteristic of the lower IC 1213.

[0434] In the graph, the vertical axis shows the charger detection voltage VCHG versus the voltage VEB-.

[0435] Figure 13 The graph (D) shows the voltage VMO characteristic of the charger connection signal output terminal C31B of the lower IC 1216.

[0436] In the graph, the vertical axis shows the voltage VDD and the voltage VMOL, which is the terminal voltage L of the charger connection signal output terminal C31B.

[0437] The diagram shows the output inversion (VM < VCHG).

[0438] Figure 13 The graph (E) shows the characteristic of the voltage VCTLC of the CO terminal output control terminal C8B of the lower IC 1214.

[0439] In the chart, the vertical axis shows the sum of voltage VDD and voltage VCOH (VDD+VCOH), the CTLC terminal detection voltage VCTLCDET, and voltage VDD.

[0440] Figure 13 The graph (F) shows the characteristic of the voltage VCO at the FET gate connection terminal C6B of the lower-level IC for charging control 1215.

[0441] In the graph, the vertical axis represents the voltage VCOH.

[0442] Additionally, the diagram schematically illustrates the CTLC terminal detection delay time tCTLC and the CTLC terminal release delay time tRCTLC.

[0443] exist Figure 13 The presence or absence of a charger connection is indicated in (G).

[0444] exist Figure 13 The (H) indicates whether the state of the host IC is normal or overcharged.

[0445] exist Figure 13 (I) shows whether the state of the lower-level IC is normal or charging control state.

[0446] Here, time t21 is the time when the charger 40 is connected to the battery device 310.

[0447] Time t22 is the time when the voltage VBATn of the first cell 111A of the host IC exceeds the overcharge detection voltage VCU.

[0448] Time t23 is the time it takes for the host IC to transition from the normal state to the overcharge state.

[0449] Time t24 is the time it takes for the lower-level IC to transition from the normal state to the charging control state.

[0450] Time t25 is the time when the charger is removed from the battery device 310 at time 40.

[0451] Time t26 is the time it takes for the host IC to recover from the overcharged state to the normal state.

[0452] Time t27 is the time it takes for the lower-level IC to return from the charging control state to the normal state.

[0453] <Examples of timing diagrams related to over-discharge in comparative examples>

[0454] Figure 14 (A) to Figure 14 (I) is a diagram representing an example of a timing diagram related to over-discharge in a comparative example.

[0455] exist Figure 14 (A) to Figure 14 Six charts are shown in (I).

[0456] In the six charts, each horizontal axis represents time, and they all represent common times. Time t31 to time t37 are shown.

[0457] In the six charts, each vertical axis represents voltage.

[0458] In addition, Figure 14 (A) to Figure 14 In example (I), (above) represents the state of the upper-side charge-discharge control circuit 330A, and (below) represents the state of the lower-side charge-discharge control circuit 330B.

[0459] Figure 14 The graph (A) shows the voltage VBATn characteristic 1311 of the first cell 111A of the host IC.

[0460] In the graph, the vertical axis shows the over-discharge release voltage VDU and the over-discharge detection voltage VDL.

[0461] Figure 14 The graph in (B) shows the characteristic of the voltage VDO at the gate connection terminal C5A of the FET for discharge control of the host IC 1312.

[0462] In the graph, the vertical axis shows the voltage VDOH, which is the voltage H of the DO terminal, and the voltage VDD of the lower IC.

[0463] Additionally, the graph schematically illustrates the over-discharge detection delay time tDL and the over-discharge release delay time tDU.

[0464] Figure 14 The graph (C) shows the voltage VM characteristic of the lower IC 1313.

[0465] In the graph, the vertical axis shows the voltage VEB- and the charger detection voltage VCHG.

[0466] Figure 14 The graph (D) shows the voltage VMO characteristic of the charger connection signal output terminal C31B of the lower IC 1316.

[0467] In the graph, the vertical axis shows the voltage VDD and the voltage VMOL, which is the terminal voltage L of the charger connection signal output terminal C31B.

[0468] The graph shows the output (VM > VCHG).

[0469] Figure 14 The graph (E) shows the characteristic of the voltage VCTLD of the output control terminal C7B of the lower IC DO terminal 1314.

[0470] In the chart, the vertical axis shows the sum of voltage VDD and voltage VDOH (VDD+VDOH), the CTLD terminal detection voltage VCTLDDET, and voltage VDD.

[0471] Figure 14 The graph (F) shows the characteristic of the voltage VDO at the FET gate connection terminal C5B of the lower IC for discharge control 1315.

[0472] In the graph, the vertical axis represents the voltage VDOH.

[0473] Additionally, the diagram schematically illustrates the CTLD terminal detection delay time tCTLD and the CTLD terminal release delay time tRCTLD.

[0474] exist Figure 14 The presence or absence of a charger connection is indicated in (G).

[0475] exist Figure 14 The (H) indicates whether the state of the higher-level IC is normal or over-discharged.

[0476] exist Figure 14 (I) shows whether the state of the lower IC is normal or discharge control state.

[0477] Here, time t31 is the time when the charger is removed from the battery device 310 at time 40.

[0478] Time t32 is the time when the voltage VBATn of the first cell 111A of the host IC is lower than the over-discharge detection voltage VDL.

[0479] Time t33 is the time it takes for the host IC to transition from the normal state to the over-discharge state.

[0480] Time t34 is the time it takes for the lower-level IC to transition from the normal state to the discharge control state.

[0481] Time t35 is the time when the charger 40 is connected to the battery device 310.

[0482] Time t36 is the time it takes for the host IC to recover from the over-discharge state to the normal state.

[0483] Time t37 is the time it takes for the lower-level IC to recover from the discharge control state to the normal state.

[0484] As described above, in the comparative example battery device 310, a dedicated terminal is required for the cascaded communication signal between the upper IC and the lower IC (in this example, the charger connection signal output terminal C31B of the lower IC, the charger connection detection circuit 95A of the upper IC, and the charger connection signal output terminal C31A).

[0485] In contrast, in the battery device 10 of this embodiment, such a dedicated terminal is not required.

[0486] (See the example of how to resolve overcharge and over-discharge conditions)

[0487] Figure 15 (A) to Figure 15 (H) is a diagram representing the removal of the overcharge and over-discharge states in the reference example.

[0488] Here, the reference example is given in a general way, and detailed explanations are omitted.

[0489] exist Figure 15 (A) to Figure 15 In the graphs shown in (E), the horizontal axis represents time and the vertical axis represents the respective voltage.

[0490] exist Figure 15 The characteristics of the battery voltage are shown in (A) 2011.

[0491] exist Figure 15 The characteristics of the DO terminal voltage are shown in (B) 2012.

[0492] exist Figure 15 The characteristics of the CO terminal voltage are shown in (C) 2013.

[0493] exist Figure 15 The characteristics of VM voltage are shown in (D) 2014.

[0494] exist Figure 15 The characteristics of the VINI terminal voltage are shown in (E) 2015. The VINI terminal (not shown) is the terminal used to detect overcurrent conditions.

[0495] exist Figure 15(F) indicates whether the charger is connected or not. When the charger is connected, the voltage at the VINI terminal starts to drop from the voltage VSS. When the voltage at the VINI terminal is lower than the charging overcurrent detection voltage VCIOV, a charging overcurrent condition is detected (not shown).

[0496] exist Figure 15 (G) indicates whether a load is connected. When a load is connected, the VINI terminal voltage starts to rise from the voltage VSS. When the VINI terminal voltage exceeds the discharge overcurrent detection voltage VDIOV, a discharge overcurrent condition is detected (not shown).

[0497] exist Figure 15 The state of the IC is shown in (H) as (1) normal state, (2) overcharge state, or (3) over-discharge state.

[0498] exist Figure 15 (A) to Figure 15 The overcharge state release 2111 and the over-discharge state release 2112 are schematically shown in (H).

[0499] <Regarding overcharge state and state deactivation>

[0500] If, during charging, the battery voltage, normally in operation, exceeds the overcharge detection voltage VCU, and this state remains above the overcharge detection delay time tCU, the charging control FET is turned off to stop charging. This state is an overcharge state.

[0501] Moreover, as one of the ways to remove the overcharged state, there is Figure 15 (A) to Figure 15 The overcharged state shown in (H) is released 2111.

[0502] In this overcharge state release 2111, when the voltage VM is above a specified value, the overcharge state is released when the battery voltage drops below the overcharge release voltage VCL.

[0503] <Regarding over-discharge state and state deactivation>

[0504] If, under normal conditions, the battery voltage falls below the over-discharge detection voltage VDL during discharge, and this state is maintained for a period exceeding the over-discharge detection delay time tDL, the discharge control FET is turned off to stop the discharge. This state is an over-discharge state.

[0505] Furthermore, if the voltage VM becomes above a specified value under over-discharge conditions, the power-down function is activated, reducing the current consumption to the level consumed during power-down. The power-down function is deactivated by connecting a charger and bringing the voltage VM below the specified value.

[0506] As one of the ways to relieve the over-discharge state, there is Figure 15 (A) to Figure 15 The over-discharge state shown in (H) is removed 2112.

[0507] In this over-discharge state release 2112, when the charger is connected and the voltage VM is below a specified value, the over-discharge state is released if the battery voltage is above the over-discharge release voltage VDU.

[0508] The overcharge state release process in this embodiment can, for example, replace... Figure 15 (A) to Figure 15 The overcharge state shown in (H) is removed by application 2111.

[0509] Similarly, the over-discharge state removal process in this embodiment can, for example, replace... Figure 15 (A) to Figure 15 The over-discharge state shown in (H) is removed by application 2112.

[0510] Furthermore, not limited to this, the overcharge state removal process and the over-discharge state removal process of this embodiment can also be applied to any circuit or any device.

[0511] The disclosed embodiments have been described in detail above with reference to the accompanying drawings. However, the specific structure is not limited to the described embodiments and may include designs that do not depart from the scope of the disclosure. For example, the discharge control FET 21, the charge control FET 22, the external voltage input terminal C4B, the discharge control FET gate connection terminal C5B, and the charge control FET gate connection terminal C6B may all be configured on the low side (the negative electrode side of the battery), but this is not a limitation and they may also be configured on the high side (the positive electrode side of the battery).

Claims

1. A charging and discharging control circuit, comprising: The battery has multiple cells connected in series, including a first cell and a second cell. The first specified state detection unit detects a first specified state for the first battery cell; The first logic circuit performs first control based on the detection result of the first specified state detection unit; The second specified state detection unit detects the second specified state of the second cell; The charger connection detection unit detects whether the battery is connected to the charger. as well as The second logic circuit performs a second control based on the detection result of the second predetermined state detection unit, the detection result of the charger connection detection unit, and a first notification from the first logic circuit that the content is the first predetermined state. The first specified state and the second specified state are either overcharged or over-discharged states. If the detection result of the charger connection detection unit meets the specified conditions, the second logic circuit blocks the first notification from the first logic circuit and performs the second control.

2. The charge / discharge control circuit according to claim 1, wherein, The first specified state detection unit includes: a first trapezoidal resistor; a first switch connected in parallel with the first trapezoidal resistor; and a first comparator connected to one end of the first trapezoidal resistor. The first logic circuit controls the on / off state of the first switch based on the output from the first comparator. The second specified state detection unit includes: a second trapezoidal resistor; a second switch connected in parallel with the second trapezoidal resistor; and a second comparator connected to one end of the second trapezoidal resistor. The second logic circuit controls the on / off state of the second switch based on the output from the second comparator.

3. The charge / discharge control circuit according to claim 1, wherein, The first specified state is an overcharge state. The specified conditions include the condition of removing the charger from the battery.

4. The charge / discharge control circuit according to claim 1, wherein, The first specified state is an over-discharge state. The specified conditions include the conditions under which the battery is connected to the charger.

5. The charge / discharge control circuit according to claim 1, wherein, The first specified state is an overcharge state. The second control includes a control that turns on a charging control field-effect transistor to control the charging process.

6. The charge / discharge control circuit according to claim 1, wherein, The first specified state is an over-discharge state. The second control includes control that turns on the discharge control field-effect transistor to control the discharge process.

7. A charge / discharge control device, comprising: A field-effect transistor is used for discharge control; A field-effect transistor is used for charging control. as well as The charge / discharge control circuit as described in claim 1.

8. A battery device, comprising: Battery; as well as The charge / discharge control device as described in claim 7 controls the charging and discharging of the battery.

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