A charge pump circuit, memory and storage system

Abstract

This invention provides a charge pump circuit, a memory, and a storage system. The pump circuit includes a multi-stage pump circuit and multiple drive circuits. The multi-stage pump circuit includes multiple pump circuits connected in series or parallel. Each drive circuit is configured to drive one of the pump circuits, with each pump circuit corresponding to one of the drive circuits. Each drive circuit includes a second output terminal and a third output terminal, which output a pump drive clock signal. The pump drive clock signal is provided to at least one pump circuit corresponding to the drive circuit.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on September 27, 2022, with application number 202211185291.7 and title "A charge pump circuit, memory and storage system". Technical Field

[0002] This invention relates to the field of memory technology, and in particular to a charge pump circuit, a memory, and a storage system. Background Technology

[0003] With the development of technology, charge pump circuits have been widely used in memory, for example, in programmable read-only memory for data writing and erasing. Currently, the performance and structure of charge pump circuits remain a crucial research area. Summary of the Invention

[0004] In view of this, the present invention provides a multi-stage charge pump circuit, a memory, and a storage system, which reduces the power consumption of the multi-stage charge pump circuit and reduces the area occupied on the integrated circuit board by providing a driving circuit for each stage of the pump circuit.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: In a first aspect, embodiments of the present invention provide a charge pump circuit, comprising: a multi-stage pump circuit and multiple drive circuits, wherein; The multi-stage pump circuit includes multiple pump circuits connected in series; Each of the plurality of drive circuits is configured to drive at least one of the plurality of pump circuits; the at least one pump circuit includes fewer pump circuits than the plurality of pump circuits; and the first output terminals of each drive circuit are connected together to power the primary pump circuit in the plurality of pump circuits.

[0006] In a second aspect, embodiments of the present invention also provide a memory, comprising: a memory array, the memory array comprising memory cells; and peripheral circuitry coupled to the memory array and configured to control the memory array; The peripheral circuitry includes any of the charge pump circuits described above.

[0007] Thirdly, embodiments of the present invention also provide a storage system, including: one or more memories as described in any of the preceding claims; and a memory controller coupled to the memories; the memory controller being configured to: send various operation commands to the memories.

[0008] This invention provides a charge pump circuit, a memory, and a storage system. The multi-stage charge pump circuit includes a multi-stage pump circuit and multiple driving circuits. The multi-stage pump circuit includes multiple pump circuits connected in series. Each of the multiple driving circuits is configured to drive at least one pump circuit among the multiple pump circuits. The number of pump circuits included in the at least one pump circuit is less than the number of pump circuits included in the multiple pump circuits. The first output terminals of each driving circuit are connected together to power the first-stage pump circuit among the multiple pump circuits. The charge pump circuit provided by this invention, by utilizing multiple driving circuits to drive the multi-stage charge pump circuit, allows each driving circuit to drive at least one stage of the pump circuit, thereby reducing the power consumption generated during the operation of the multi-stage charge pump circuit and reducing the area occupied on the integrated circuit board. Attached Figure Description

[0009] When read in conjunction with the accompanying drawings, aspects of the invention can be best understood from the following specific embodiments. Note that, according to standard practice in industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0010] Figure 1 A block diagram of an exemplary system with memory in the related art is shown; Figure 2 A schematic diagram of an exemplary memory card with memory is shown; Figure 3 A schematic diagram showing an exemplary solid-state drive (SSD) with memory is shown; Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown; Figure 5 A schematic diagram showing the organizational structure of the memory array contained in the memory; Figure 6 A side view showing a cross-section of an exemplary memory array containing NAND memory strings; Figure 7 A block diagram of an exemplary memory including a storage array and peripheral circuitry is shown. Figure 8 This diagram illustrates the structure of a series-connected multi-stage charge pump circuit provided in an embodiment of the present invention. Figure 9 This diagram illustrates the structure of a parallel multi-stage charge pump circuit provided in an embodiment of the present invention. Figure 10 A simplified structural diagram of a multi-stage charge pump circuit employing a single driving method, provided in an embodiment of the present invention, is shown. Figure 11 This diagram illustrates the structure of a multi-stage charge pump circuit provided in an embodiment of the present invention. Figure 12 A simplified structural diagram of a three-stage charge pump circuit provided in an embodiment of the present invention is shown. Figure 13 This invention provides an embodiment of the invention. Figure 12 The diagram shows the specific structure of the three-stage charge pump circuit. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0012] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (or more) other elements or features as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0013] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0014] Figure 1 A block diagram of an exemplary system with memory in the related art is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1As shown, system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this invention, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0015] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones in low duty cycle environments. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0016] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for connecting the memory card to a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 1 The SSD connector 304 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 can also be configured to control erase, read, and write operations of the memory 104.

[0017] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate pump-stage transistor, or a charge-trapping type memory cell including a charge-trapping pump-stage transistor.

[0018] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 406 is a multi-level cell (MLC) capable of storing a single bit of data in multiple four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that memory cell. A fourth nominal storage value may be used for the erase state.

[0019] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate a selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the pump stage transistor with DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the pump stage transistor with SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0020] like Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0021] The organization structure of the memory array 401 inside the memory is as follows: Figure 5 As shown. The storage array 401 can be divided into several DIEs (or LUNs), each DIE has several planes, each plane has several blocks, each block has several pages, and each page corresponds to a wordline. Wordlines connect thousands upon thousands of storage units 406. The DIE / LUN is the basic unit for receiving and executing operation commands. For example... Figure 5As shown, LUN0 and LUN1 can simultaneously receive and execute different commands (but there are still certain limitations, which vary depending on the manufacturer's flash memory). Within a single LUN, only one command can be executed independently at a time; it's not possible to write to one page while simultaneously reading from other pages. A LUN is further divided into several Planes. Commonly available LUNs have one or two Planes, but there are also flash memory modules with four Planes, and some even have more than four Planes, such as those with six Planes. It should be understood that the number of Planes in a LUN may increase with technological advancements, and this invention does not impose any limitations. Each Plane has its own independent cache register and page register, the size of which is equal to the size of a page. When writing to a page, the memory controller first transfers the data from the memory controller to the cache register of the corresponding Plane, and then writes the entire cache register to the memory cell. Reading is the reverse: the data for that page is first read from the memory cell into the cache register, and then transmitted to the memory controller as needed. The "on-demand" aspect means that when we read data, it's unnecessary to send the entire page of data to the memory controller; instead, data is transferred selectively as needed. However, it's important to remember that whether reading data from a memory cell into the cache register or writing data from the cache register into a memory cell, this can be done on a page-by-page basis.

[0022] Figure 6 A side view of a cross-section of an exemplary memory array 401 including NAND memory cell strings 408, according to some aspects of the present invention, is shown. Figure 6 As shown, the NAND memory cell string 408 can extend vertically through the memory stack layer 602 above the substrate 601. The substrate 601 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0023] The memory stack 602 may include alternating gate conductive layers 603 and gate-to-gate dielectric layers 604. The number of pairs of gate conductive layers 603 and gate-to-gate dielectric layers 604 in the memory stack 602 determines the number of memory cells 406 in the memory array 401. The gate conductive layers 603 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 603 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 603 includes a doped polysilicon layer. Each gate conductive layer 603 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 602 as a DSG line 413, at the bottom of the memory stack 602 as an SSG line 415, or between DSG lines 413 and SSG lines 415 as a word line 418.

[0024] like Figure 6 As shown, the NAND memory cell string 408 includes a channel structure 605 extending vertically through the memory stack layer 602. In some embodiments, the channel structure 605 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 605 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0025] Return to reference Figure 4Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface 716, and a data bus 718. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 7 Additional peripheral circuitry not shown.

[0026] Page buffer / sensor amplifier 704 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 712. In one example, page buffer / sensor amplifier 704 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 706 can be configured to be controlled by control logic unit 712 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 710.

[0027] The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and to select / deselect block 404 of the memory array 401 and to select / deselect word line 418 of block 404. The row decoder / word line driver 708 can also be configured to drive word line 418 using word line voltages generated from the voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG line 415 and DSG line 413. As described in detail below, the row decoder / word line driver 708 is configured to perform an erase operation on memory cell 406 coupled to one or more selected word lines 418. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0028] Control logic unit 712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 714 can be coupled to control logic unit 712 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 716 can be coupled to control logic unit 712 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 712, as well as to buffer status information received from control logic unit 712 and relay it to the host. Interface 716 can also be coupled to column decoder / bit line driver 706 via data bus 718 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0029] The voltage generator 710 is typically implemented using a charge pump circuit composed of transistors and capacitors. The input of this charge pump circuit is connected to the power supply, and its output is connected to the memory array. This charge pump circuit can boost the lower power supply voltage received at its input to provide a higher programming, erasing, or reading voltage for the memory array. Furthermore, when the voltage to be applied to the memory array needs to be lowered, the charge pump circuit can discharge its input and output terminals separately to reduce the output voltage.

[0030] Currently, the charge pump circuits used in memory include... Figure 8 and Figure 9The circuit is divided into series multi-stage charge pump circuits and parallel multi-stage charge pump circuits. The series multi-stage charge pump circuit can include N charge pumps connected in series. The input terminal VIN of the first charge pump is the input terminal of the charge pump circuit. The input terminals of the second to Nth charge pumps are connected to the output terminal of the preceding charge pump. The output terminal VOUT of the last charge pump is the output terminal of the charge pump circuit. By connecting multiple charge pumps in series, the power supply voltage can be amplified step by step, thereby effectively increasing the voltage boost. For example, assuming the voltage boost of each charge pump is Vck, the final output voltage of the charge pump circuit after connecting N charge pumps in series can reach N×Vck. The parallel multi-stage charge pump circuit can include N charge pumps connected in parallel, from CP1 to CPN. N is an integer greater than 1. The input terminals VIN of these N charge pumps are connected together to form the input terminal of the charge pump circuit, and the output terminals VOUT of these N charge pumps are connected together to form the input terminal of the charge pump circuit. By connecting multiple charge pumps in parallel, the output current of the charge pump circuit can be effectively increased while boosting the power supply voltage. For driving a series-connected multi-stage charge pump circuit, such as... Figure 10 As shown, a single drive circuit drives each stage of the multi-stage charge pump circuit. According to Kirchhoff's current law, the current I0 flowing from the drive circuit CLKBST should satisfy the sum of I1 and I2; I1 is the sum of I3 and I4. Therefore, the drive circuit CLKBST needs to output a large current to drive each stage of the pump circuit, resulting in significant power dissipation across the parasitic resistance between the drive circuit CLKBST and each stage of the pump circuit. This leads to a decrease in the efficiency of the charge pump and a reduction in the driving capability of the drive circuit. It should be noted that... Figure 10 R1, R2, and R3 are the parasitic resistances between the drive circuit CLKBST and the first-stage pump circuit PMPSTG_0, the intermediate-stage pump circuit PMPSTG_1, and the last-stage pump circuit PMPSTG_2, respectively.

[0031] To address the aforementioned technical problems, embodiments of the present invention provide a charge pump circuit, as detailed below. Figure 11 As shown, the charge pump circuit 110 may include: a multi-stage pump circuit 1101 and multiple drive circuits 1102, wherein; The multi-stage pump circuit 1101 includes multiple pump circuits connected in series; Each of the plurality of drive circuits is configured to drive at least one of the plurality of pump circuits; the at least one pump circuit includes fewer pump circuits than the plurality of pump circuits; and the first output terminals of each drive circuit are connected together to power the primary pump circuit in the plurality of pump circuits.

[0032] like Figure 11 As shown, the plurality of pump circuits may include a first-stage pump circuit, a plurality of intermediate-stage pump circuits, and a last-stage pump circuit; wherein, The input and output terminals of the first-stage pump circuit, the multiple intermediate-stage pump circuits, and the last-stage pump circuit are sequentially electrically connected to form a series multi-stage pump circuit 1101; the input terminal of the first-stage pump circuit is connected to the input terminal of the multiple drive circuits; the output terminal of the last-stage pump circuit outputs the target voltage that meets the requirements. The second output terminal of each of the plurality of drive circuits is connected to the controlled terminal of at least one of the plurality of pump circuits, for driving the at least one pump circuit.

[0033] In other words, the multi-stage pump circuit 1101 here can be as follows: Figure 7 The illustrated series multi-stage charge pump circuit includes a first-stage pump circuit, N intermediate-stage pump circuits, and a last-stage pump circuit. The output and input terminals of each pump circuit are electrically connected sequentially. Only the input terminal of the first-stage pump circuit is connected to the input voltage provided by the driving circuit, and only the output terminal of the last-stage pump circuit outputs the target voltage that meets the requirements. The charge pump circuit provided in this embodiment includes a series multi-stage pump circuit and multiple driving circuits, wherein each of the multiple driving circuits drives at least one stage of the multi-stage pump circuit. In other words, at least one stage of the charge pump circuit provided in this embodiment is driven by one driving circuit, and the number of stages in the at least one stage is less than the number of stages in the multi-stage pump circuit. Thus, the driving of the multi-stage pump circuit is not a single driving method, thereby reducing the power consumption on the parasitic resistance between the driving circuit CLKBST and each stage pump circuit, improving the working efficiency of the charge pump and the driving capability of the driving circuit.

[0034] In some embodiments, each of the plurality of drive circuits drives one of the plurality of pump circuits, and the drive circuits and pump circuits correspond one-to-one.

[0035] In other words, one drive circuit drives one pump circuit, one by one, so that the drive circuit and the pump circuit correspond one-to-one. In this way, the power consumption on the parasitic resistance between the drive circuit CLKBST and each pump circuit is reduced to the minimum, thereby improving the working efficiency of the charge pump and the driving capability of the drive circuit.

[0036] In some embodiments, the number of drive circuits in the plurality of drive circuits is less than the number of pump circuits.

[0037] In other words, each drive circuit drives at least one pump circuit. It should be noted that when a drive circuit drives more than one pump circuit, the connection relationship between the drive circuit and these multiple pump circuits can be similar to... Figure 10 As shown.

[0038] In some embodiments, each drive circuit is configured to receive an external control clock signal and an initial input voltage, and generate a pump drive clock signal and a pump input voltage based on the external control clock signal and the initial input voltage; the pump drive clock signal is provided to the at least one-stage pump circuit corresponding to the drive circuit; and the pump input voltage is provided to the first-stage pump circuit of the at least two-stage pump circuits connected in series.

[0039] This defines a drive circuit that receives an external control clock signal and an initial input voltage, and generates a pump drive clock signal and a pump input voltage based on the external control clock signal and the initial input voltage. Here, the pump drive clock signal is provided to the at least one pump circuit corresponding to the drive circuit; the pump input voltage is provided to the first-stage pump circuit among the plurality of pump circuits. In other words, the drive circuit's function is to generate the pump drive clock signal and the pump input voltage using the external control clock signal and the initial input voltage, and to provide the pump drive clock signal to the corresponding at least one pump circuit and the pump input voltage to the first-stage pump circuit. The first-stage pump circuit is the first pump circuit among the plurality of pump circuits.

[0040] In some embodiments, the input terminal and the controlled terminal of the first-stage pump circuit in the plurality of pump circuits are respectively connected to the pump input voltage and the pump drive clock signal provided by the corresponding drive circuit; the input terminal of the intermediate-stage pump circuit in the plurality of pump circuits is connected to the output terminal of the first-stage pump circuit or the output terminal of the previous-stage pump circuit; the input terminal of the tail-stage pump circuit in the plurality of pump circuits is connected to the output terminal of the previous-stage pump circuit; the output terminal of the tail-stage pump circuit is used to output the target voltage that meets the requirements.

[0041] It should be noted that this function defines the connection relationship and input / output signals between multiple pump circuits. The input terminal of the first-stage pump circuit is connected to the pump input voltage, and the controlled terminal is connected to the pump drive clock signal. The input terminal of the intermediate-stage pump circuit is connected to the output terminal of the first-stage pump circuit or the output terminal of the preceding-stage pump circuit; the controlled terminal is connected to the pump drive clock signal, and the output terminal is connected to the input terminal of the subsequent-stage pump circuit or the input terminal of the last-stage pump circuit. The input terminal of the last-stage pump circuit is connected to the output terminal of the preceding-stage pump circuit. The output terminal of the last-stage pump circuit is used to output a target voltage that meets the requirements. Here, the target voltage that meets the requirements is the higher programming voltage, erase voltage, or read voltage required by the storage array, etc.

[0042] In some embodiments, the structure of each stage of the multi-stage pump circuit may be identical.

[0043] In some embodiments, each of the plurality of driving circuits may have the same structure.

[0044] With the above-described structure, the driving method provided by the embodiments of the present invention has more obvious advantages.

[0045] When a one-to-one connection between the drive circuit and the pump circuit is adopted, in some embodiments, each of the plurality of pump circuits may include: The first group of pump-stage transistors includes two transistors connected in series at the first node. One end of the first group of pump-stage transistors serves as the input terminal of the pump circuit and is connected to the output terminal of each driving circuit or the input terminal of the preceding pump circuit. The other end of the first group of pump-stage transistors serves as the output terminal of the pump circuit and is connected to the input terminal of the next pump circuit or outputs the target voltage. The first pump capacitor has one end connected to the first node, and the other end of the first pump capacitor is connected as the first controlled terminal of the pump circuit to the second output terminal of the corresponding drive circuit. The second output terminal outputs the first sub-drive clock signal.

[0046] This describes the structure of any stage of a multi-stage pump circuit. Specifically, the structure may include a pump capacitor and a set of pump-stage transistors, namely: a first pump capacitor and a first set of pump-stage transistors. The first set of pump-stage transistors includes two transistors connected in series at a first node; that is, the connection point of the two transistors is the first node. One end of the first set of pump-stage transistors serves as the input terminal of the pump circuit and is connected to the output terminal of each driving circuit or the input terminal of the preceding stage pump circuit. For example, if the pump circuit is a first-stage pump circuit, one end of the first set of pump-stage transistors serves as the input terminal of the pump circuit and is connected to the output terminal of each driving circuit. The pump circuit is configured such that, if it is an intermediate-stage pump circuit or a tail-stage pump circuit, one end of the first set of pump-stage transistors serves as the input terminal of the pump circuit and is connected to the output terminal of the preceding pump circuit; the other end of the first set of pump-stage transistors serves as the output terminal of the pump circuit and is connected to the input terminal of the next-stage pump circuit or outputs the target voltage. If the pump circuit is a first-stage pump circuit or an intermediate-stage pump circuit, the other end of the first set of pump-stage transistors serves as the output terminal of the pump circuit and is connected to the input terminal of the next-stage pump circuit. If the pump circuit is a tail-stage pump circuit, the other end of the first set of pump-stage transistors serves as the output terminal of the pump circuit and outputs the target voltage. The first pump capacitor has two ends, one end connected to the first node and the other end connected to the driving clock signal. The first pump circuit boosts the input pump input voltage according to the connected driving clock signal.

[0047] In some embodiments, each pump circuit further includes: The second group of pump stage transistors includes two transistors connected in series at the second node. One end of the second group of pump stage transistors is connected together with one end of the first group of pump stage transistors as the input terminal of the pump circuit, which is connected to the output terminal of each drive circuit or the input terminal of the previous stage pump circuit. The other end of the second group of pump stage transistors is connected together with the other end of the first group of pump stage transistors as the input terminal of the pump circuit, which is connected to the input terminal of the next stage pump circuit or outputs the target voltage. The second pump capacitor has one end connected to the second node, and the other end of the second pump circuit is connected to the third output terminal of the corresponding drive circuit as the second controlled terminal of the pump circuit; the third output terminal outputs the second sub-drive clock signal. The first sub-driving clock signal and the second sub-driving clock signal are included in the pump driving clock signal and are 180 degrees out of phase.

[0048] Here, in order to provide a continuous and stable target voltage, each pump circuit further includes: another pump capacitor and another set of pump stage transistors, namely a second pump capacitor and a second set of pump stage transistors. The structure of the second set of pump stage transistors is similar to that of the first set of pump stage transistors, and the connection relationship between the second set of pump stage transistors and the second pump capacitor and the drive circuit is similar to the connection relationship between the first set of pump stage transistors and the first pump capacitor and the drive circuit. Please refer to the foregoing description, which will not be repeated here.

[0049] It should be noted that when the pump circuit includes a first pump capacitor, a second pump capacitor, a first set of pump-stage transistors, and a second set of pump-stage transistors, one end of the first pump capacitor is connected to a first sub-drive clock signal; the second pump capacitor is connected to a second sub-drive clock signal, wherein the first drive clock signal and the second sub-drive clock signal are a set of drive signals with a phase difference of 180° and equal amplitude. Apart from this difference, everything else is the same as described above.

[0050] In some embodiments, each of the plurality of driving circuits may include: The first group of driving transistors includes three transistors connected in series at the third and fourth nodes. One end of the first group of driving transistors serves as an input terminal connected to the initial input voltage; the other end of the first group of driving transistors is grounded. The first group of driving transistors also includes a first transistor connected at one end to the third node; the other end of the first transistor serves as a first output terminal connected to the input terminal of the first-stage pump circuit; the fourth node of the first group of driving transistors serves as a second output terminal connected to the first controlled terminal of each of the at least one corresponding pump circuit; the second output terminal outputs a first sub-driving clock signal. A first driving capacitor, one end of which is connected to a third node; the other end of which is connected to a first sub-control clock signal.

[0051] In some embodiments, each drive circuit further includes: The second group of driving transistors includes three transistors connected in series at the fifth and sixth nodes. One end of the second group of driving transistors is connected to the initial input voltage; the other end of the second group of driving transistors is grounded. The second group of driving transistors also includes a second transistor with one end connected to the fifth node. The other end of the second transistor is connected together with the other end of the first transistor as the first output terminal connected to the input terminal of the first-stage pump circuit. The sixth node of the second group of driving transistors serves as the third output terminal connected to the second controlled terminal of each of the corresponding at least one pump circuit. The third output terminal outputs a second sub-driving clock signal. The second driving capacitor has one end connected to the fifth node and the other end connected to the second sub-control clock signal. The first sub-drive clock signal and the second sub-drive clock signal are included in the pump drive clock signal and are 180 degrees out of phase; the first sub-control clock signal and the second sub-control clock signal are included in the control clock signal and are 180 degrees out of phase.

[0052] In some embodiments, the controlled terminal of the first transistor is connected to the fifth node; the controlled terminal of the second transistor is connected to the third node.

[0053] In some embodiments, two transistors connected in series at the third node are controlled by a second sub-control clock signal; two transistors connected in series at the fifth node are controlled by a first sub-control clock signal.

[0054] It should be noted that, based on the driving method provided in the embodiments of the present invention, the pump circuit and the driving circuit are in one-to-one correspondence. Corresponding to the structure of the pump circuit, when the pump circuit only includes a first pump capacitor and a first group of pump stage transistors, the corresponding driving circuit also only includes a first driving capacitor and a first group of driving transistors; when the pump circuit includes a first pump capacitor, a second pump capacitor, a first group of pump stage transistors, and a second group of pump stage transistors, the corresponding driving circuit includes a first driving capacitor, a second driving capacitor, a first group of driving transistors, and a second group of driving transistors.

[0055] To understand this invention, Figure 12 and Figure 13 The charge pump circuit described above will be used as an example for illustration. Figure 13 This diagram illustrates the structure of a three-stage charge pump circuit provided in an embodiment of the present invention. Figure 12 This invention provides an embodiment of the invention. Figure 13 The diagram shows the connection structure of the drive circuit and pump circuit in the three-stage charge pump circuit.

[0056] like Figure 12As shown, the three-stage charge pump circuit includes three pump circuits and three driver circuits. The three-stage pump circuit includes a first-stage pump circuit PMPSTG_0, an intermediate-stage pump circuit PMPSTG_1, and a final-stage pump circuit PMPSTG_2, with each pump circuit connected in series. The three driver circuits BSTCLK_0, BSTCLK_1, and BSTCLK_2 drive the first-stage pump circuit PMPSTG_0, the intermediate-stage pump circuit PMPSTG_1, and the final-stage pump circuit PMPSTG_2, respectively. Furthermore, the output terminals of the three driver circuits that generate the pump input voltage are connected together, inputting the generated pump input voltage to the first-stage pump circuit PMPSTG_0. It should be noted that R4, R5, and R6 are the parasitic resistances between driver circuit BSTCLK_0 and the first-stage pump circuit PMPSTG_0, between driver circuit BSTCLK_1 and the intermediate-stage pump circuit PMPSTG_1, and between driver circuit BSTCLK_3 and the final-stage pump circuit PMPSTG_3, respectively.

[0057] The three-stage charge pump circuit includes a first-stage pump circuit PMPSTG_0, an intermediate-stage pump circuit PMPSTG_1, and a last-stage pump circuit PMPSTG_2, as well as three drive circuits BSTCLK_0, BSTCLK_1, and BSTCLK_2. The specific connection method of these components is as follows: Figure 13 As shown. It should be noted that, in Figure 13 In the example, C1 is the first driving capacitor; C2 is the second driving capacitor; C3 is the first pump capacitor; C4 is the second pump capacitor; Q1 / Q3 / Q5 / Q7 are the first group of driving transistors; Q2 / Q4 / Q6 / Q8 are the second group of driving transistors; kc_p is the first sub-control clock signal; ck_p is the second sub-control clock signal; Q9 / Q11 are the first group of pump stage transistors; Q10 / Q12 are the second group of pump stage transistors; kc_bst0 is the first sub-driving clock signal output from the second output terminal of the driving circuit; ck_bst0 is the second sub-driving clock signal output from the third output terminal of the driving circuit; VCC is the initial input voltage connected to the input terminal of the driving circuit; VIN is the pump input voltage output from the first output terminal of the driving circuit; VOUT is the target voltage output from the output terminal of the tail pump circuit; V10 is the third node; the area between Q5 / Q7 is the fourth node; V01 is the fifth node; the area between Q6 / Q8 is the sixth node; P01 is the first node; P10 is the second node.

[0058] Combination Figure 8The structure of the three-stage charge pump circuit shown is as follows: Taking the first-stage pump circuit as an example, when ck_p is high and kc_p is low, VCC charges capacitor C1. At this time, the voltage of V10 is VCC, the voltage of V01 is 2VCC, and the voltage of V01 is transmitted to VIN and ck_bst0. The voltage of kc_bst0 is VSS. At the same time, in the pump circuit section, VIN charges capacitor C3. At this time, the voltage of P01 is 2VCC, and the voltage of P10 is 4VCC. When ck_p is low and kc_p is high, VCC charges capacitor C2. At this time, the voltage of V10 is 2VCC, the voltage of V01 is VCC, and the voltage of V10 is transmitted to Vin and kc_bst0. The voltage of ck_bst0 is VSS. At the same time, in the pump circuit section, VIN charges capacitor C4. At this time, the voltage of P10 is 2VCC, and the voltage of P01 is 4VCC. The CLKBST section generates a 2VCC to VSS clock signal and twice the input voltage, while the PMPSTG section generates a stable 4VCC voltage. This configuration, by generating a 2VCC to VSS clock signal and a 2VCC Vin input via CLKBST, reduces the number of charge pump stages required at the same voltage, thus reducing layout area and improving efficiency. One PMPSTG paired with one CLKBST effectively reduces power loss due to parasitic resistance, thereby improving efficiency and current capability.

[0059] The three-stage charge pump circuit provided in this embodiment of the invention utilizes multiple driving circuits to drive the multi-stage charge pump circuit, with each driving circuit capable of driving at least one stage of the pump circuit. Figures 1 to 7 Compared to the driving method shown (single driving circuit), the direct driving or a small number of indirect driving methods are used to drive each stage of the multi-stage charge pump circuit. The aspect ratio of the transistors in each driving circuit is reduced, and the capacitance of the driving capacitor in the driving circuit is also smaller. This saves more board space. Moreover, one PMPSTG is equipped with one CLKBST, which can effectively reduce the power loss on parasitic resistance, thereby improving efficiency and current capability.

[0060] This invention also provides a memory, including: a memory array, the memory array including memory cells; and peripheral circuitry coupled to the memory array and configured to control the memory array; The peripheral circuitry includes the charge pump circuit described in any of the preceding claims.

[0061] It should be noted that the memory provided in this embodiment of the invention includes the aforementioned multi-stage charge pump circuit. Therefore, the multi-stage charge pump circuit has been described in detail above and will not be repeated here. Other structures of the memory array and peripheral circuits can be as described above.​ The example described can also be the structure of other existing applications, and there are no restrictions here.

[0062] This invention also provides a storage system, including: one or more of the aforementioned memories; and a memory controller coupled to the memory; the memory controller is configured to send various operation commands to the memory.

[0063] In some embodiments, the storage system is a solid-state drive (SSD) or a memory card.

[0064] It should be noted that the storage system provided in this embodiment of the invention includes the aforementioned memory. The structure of the memory has been clearly described above and will not be repeated here. The structure of the memory controller can be as described above, or any other structure capable of implementing the functions of a memory controller; no limitations are imposed here.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A charge pump circuit, characterized in that, include: Multistage pump circuit and multiple drive circuits, wherein; The multi-stage pump circuit includes multiple pump circuits connected in series or in parallel; Each of the plurality of driving circuits is configured to drive one of the plurality of pump circuits, and the plurality of pump circuits correspond one-to-one with the plurality of driving circuits; each driving circuit includes a second output terminal and a third output terminal, the second output terminal and the third output terminal being used to output a pump driving clock signal; The pump drive clock signal is provided to the pump circuit corresponding to the drive circuit.

2. The charge pump circuit according to claim 1, characterized in that, The plurality of pump circuits includes a first-stage pump circuit and a last-stage pump circuit; wherein... The output terminal of the first-stage pump circuit and the input terminal of the last-stage pump circuit are connected to form a series multi-stage pump circuit.

3. The charge pump circuit according to claim 2, characterized in that, The plurality of pump circuits also includes a plurality of intermediate-stage pump circuits; wherein... The input and output terminals of the first-stage pump circuit, the multiple intermediate-stage pump circuits, and the last-stage pump circuit are sequentially electrically connected to form a series multi-stage pump circuit; the output terminal of the last-stage pump circuit outputs the target voltage that meets the requirements. The second output terminal of each of the plurality of drive circuits is connected to the controlled terminal of the corresponding pump circuit in the plurality of pump circuits.

4. The charge pump circuit according to claim 1, characterized in that, The plurality of pump circuits includes a first-stage pump circuit and a last-stage pump circuit; wherein... The input terminal of the first-stage pump circuit is connected to the input terminal of the last-stage pump circuit, and the output terminal of the first-stage pump circuit is connected to the output terminal of the last-stage pump circuit, forming a parallel multi-stage pump circuit.

5. The charge pump circuit according to claim 1, characterized in that, Each drive circuit is configured to receive an external control clock signal and generate a pump drive clock signal based on the external control clock signal; the pump drive clock signal is provided to the pump circuit corresponding to the drive circuit.

6. The charge pump circuit according to claim 5, characterized in that, The controlled terminal of the first-stage pump circuit in the plurality of pump circuits is connected to the pump drive clock signal provided by the corresponding drive circuit; the input terminal of the intermediate-stage pump circuit in the plurality of pump circuits is connected to the output terminal of the first-stage pump circuit or the output terminal of the previous-stage pump circuit; the input terminal of the tail-stage pump circuit in the plurality of pump circuits is connected to the output terminal of the previous-stage pump circuit; the output terminal of the tail-stage pump circuit is used to output the target voltage that meets the requirements.

7. The charge pump circuit according to claim 1, characterized in that, Each of the multiple pump circuits has the same structure.

8. The charge pump circuit according to claim 1, characterized in that, Each of the plurality of driving circuits has the same structure.

9. The charge pump circuit according to claim 1, characterized in that, Each of the plurality of pump circuits includes: The first group of pump stage transistors includes two transistors connected in series at the first node. One end of the first group of pump stage transistors serves as the input terminal of the pump circuit, and the other end of the first group of pump stage transistors serves as the output terminal of the pump circuit, connected to the input terminal of the next stage pump circuit or outputting the target voltage. A first pump capacitor, one end of which is connected to a first node, and the other end of which is connected as the first controlled terminal of the pump circuit to the second output terminal of the corresponding drive circuit.

10. The charge pump circuit according to claim 9, characterized in that, Each pump circuit also includes: The second group of pump stage transistors includes two transistors connected in series at the second node. One end of the second group of pump stage transistors is connected to one end of the first group of pump stage transistors as the input terminal of the pump circuit. The other end of the second group of pump stage transistors is connected to the other end of the first group of pump stage transistors as the input terminal of the pump circuit, which is connected to the input terminal of the next stage pump circuit or outputs the target voltage. The second pump capacitor has one end connected to the second node, and the other end of the second pump circuit is connected to the third output terminal of the corresponding drive circuit as the second controlled terminal of the pump circuit.

11. The charge pump circuit according to claim 10, characterized in that, The second output terminal outputs a first sub-drive clock signal, and the third output terminal outputs a second sub-drive clock signal; the pump drive clock signal includes the first sub-drive clock signal and the second sub-drive clock signal. The first sub-driving clock signal and the second sub-driving clock signal are 180 degrees out of phase.

12. The charge pump circuit according to claim 10, characterized in that, The gate of the transistor that serves as the output terminal of the pump circuit in the first group of pump-stage transistors is connected to the second node. The gate of the transistor in the second group of pump stage transistors, which serves as the output terminal of the pump circuit, is connected to the first node.

13. The charge pump circuit according to claim 1, characterized in that, The driving circuit also includes a first output terminal, which is used to output the pump input voltage. The multiple first outputs of the multiple drive circuits are connected together and connected to the input of the primary pump circuit in the multiple pump circuits.

14. The charge pump circuit according to claim 13, characterized in that, Each of the plurality of driving circuits includes: The first group of driving transistors includes three transistors connected in series at the third and fourth nodes. One end of the first group of driving transistors serves as an input terminal connected to the initial input voltage; the other end of the first group of driving transistors is grounded. The first group of driving transistors also includes a first transistor connected at one end to the third node; the other end of the first transistor serves as a first output terminal connected to the input terminal of the first-stage pump circuit; the fourth node of the first group of driving transistors serves as a second output terminal connected to the first controlled terminal of each of the at least one corresponding pump circuit; the second output terminal outputs a first sub-driving clock signal. A first driving capacitor, one end of which is connected to a third node; the other end of which is connected to a first sub-control clock signal.

15. The charge pump circuit according to claim 14, characterized in that, Each of the driving circuits further includes: The second group of driving transistors includes three transistors connected in series at the fifth and sixth nodes. One end of the second group of driving transistors is connected to the initial input voltage; the other end of the second group of driving transistors is grounded. The second group of driving transistors also includes a second transistor with one end connected to the fifth node. The other end of the second transistor is connected together with the other end of the first transistor as the first output terminal connected to the input terminal of the first-stage pump circuit. The sixth node of the second group of driving transistors serves as the third output terminal connected to the second controlled terminal of each of the corresponding at least one pump circuit. The third output terminal outputs a second sub-driving clock signal. The second driving capacitor has one end connected to the fifth node and the other end connected to the second sub-control clock signal. The pump drive clock signal includes the first sub-drive clock signal and the second sub-drive clock signal, and the control clock signal includes the first sub-control clock signal and the second sub-control clock signal.

16. The charge pump circuit according to claim 15, characterized in that, The first sub-driving clock signal and the second sub-driving clock signal are 180 degrees out of phase; the first sub-control clock signal and the second sub-control clock signal are 180 degrees out of phase.

17. The charge pump circuit according to claim 15, characterized in that, The controlled terminal of the first transistor is connected to the fifth node; the controlled terminal of the second transistor is connected to the third node.

18. The charge pump circuit according to claim 15, characterized in that, Two transistors connected in series at the third node are controlled by a second sub-control clock signal; two transistors connected in series at the fifth node are controlled by a first sub-control clock signal.

19. A memory, characterized in that, include: Storage array, the storage array comprising storage units; and peripheral circuitry coupled to the memory array and configured to control the memory array; The peripheral circuit includes the charge pump circuit according to any one of claims 1 to 18.

20. A storage system, characterized in that, include: One or more of the memories described in claim 19; and a memory controller coupled to the memory; The memory controller is used to send various operation commands to the memory.

21. The storage system according to claim 20, characterized in that, The storage system is a solid-state drive (SSD) or a memory card.

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