Wide load high stability boost circuit and control method thereof

Abstract

This invention discloses a high-stability BOOST circuit with wide load range and its control method, comprising a power stage circuit and a mode switching circuit. The mode switching circuit generates control signals ctl1 and ctl2 based on the output signal VOUT and provides them to the power stage circuit. This invention does not sacrifice dynamic performance during ultra-wide load switching. Instead, it adjusts Rcomp by monitoring the load current, enabling the loop bandwidth to vary with the zero point of the right half-plane. This solves the trade-off between transient response and stability under ultra-wide load conditions, improving system performance.

Description

Technical Field

[0001] This invention relates to a BOOST circuit and its control method, particularly a BOOST circuit with wide load and high stability and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] The bypass boost chip, serving as the power supply front-end in a mobile phone, is a crucial component connecting the phone's battery to subsequent chips such as the processor, camera, and power amplifier (PA). Traditional boost chips typically require a trade-off between transient response and stability. To achieve good transient response without any transient enhancement solutions, the only approach is to increase loop bandwidth. However, increasing loop bandwidth leads to instability during the rapid increase in the zero point of the right half-plane of the boost chip as it transitions from light to heavy loads. This causes the provided output voltage to oscillate, impacting system reliability. Especially with today's increasingly powerful mobile phones, where load transitions can easily exceed 20 times, these problems become more severe, widespread, and difficult to resolve.

[0003] Traditional BOOST power management chips become unstable during the transition from light load to heavy load, as the zero point of the right half-plane of the BOOST increases rapidly. This causes the output voltage to oscillate, affecting the reliability of the system. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a BOOST circuit with wide load and high stability and its control method, so as to solve the instability of BOOST chip when switching from light load to heavy load and improve the reliability of the system.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A wide-load, high-stability BOOST circuit includes a power stage circuit and a mode switching circuit. The mode switching circuit generates control signals ctl1 and ctl2 based on the output signal VOUT and provides them to the power stage circuit.

[0007] Further, the mode switching circuit includes an RS flip-flop RS1, an AND gate AND1, a peak comparator PEAK, a valley comparator VALLEY, a pulse frequency modulation counter PFM_TIMER, a voltage-to-current circuit V2I, an adaptive loop compensation adjustment circuit Comp_loop, an error amplifier GM, resistors R3 and R4, an NMOS transistor M3, and a capacitor Ccomp. The non-inverting input of the error amplifier GM is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of the error amplifier GM is connected to the input of the voltage-to-current circuit V2I and one end of the capacitor Ccomp to generate the signal Vcomp. The other end of the capacitor Ccomp is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded. The first output of the voltage-to-current circuit V2I is connected to the input of the adaptive loop compensation adjustment circuit Comp_loop, and the output of the adaptive loop compensation adjustment circuit Comp_loop is connected to... The gate of NMOS transistor M3 is connected to the voltage-to-current circuit V2I. The second output terminal of V2I is connected to the inverting input terminal of peak comparator PEAK and one end of resistor R4, and inputs current i_hys. The other end of resistor R4 is grounded. The non-inverting input terminal of peak comparator PEAK is connected to signal sw. The output terminal of peak comparator PEAK is connected to the R terminal of RS flip-flop RS1. The third output terminal of V2I is connected to the inverting input terminal of valley comparator VALLEY and one end of resistor R3. The fourth output terminal of V2I is connected to the non-inverting input terminal of valley comparator VALLEY and the other end of resistor R3. The output terminal of valley comparator VALLEY is connected to the second input terminal of AND gate AND1. The first input terminal of AND gate AND1 is connected to the output terminal of pulse frequency modulation counter PFM_TIMER. The output terminal of AND gate AND1 is connected to the S terminal of RS flip-flop RS1. The Q terminal of RS flip-flop RS1 outputs control signal ctl1. Output control signal ctl2.

[0008] Furthermore, the adaptive loop compensation adjustment circuit Comp_loop includes an operational amplifier A1, an NMOS transistor M4, an NMOS transistor M5, a diode D1, a current source I1, and a current source I2. The non-inverting input terminal of the operational amplifier A1 is connected to a reference voltage Vref. The output terminal of the operational amplifier A1 is connected to the gates of the NMOS transistors M4 and M5 to generate a signal V_gate. The drain of the NMOS transistor M4 is connected to node B via the inverting input terminal of the operational amplifier A1, the output terminal of the current source I1, and the cathode of the diode D1. The anode of the diode D1 is connected to node A via the input terminal of the current source I2 and serves as the input terminal of the adaptive loop compensation adjustment circuit Comp_loop, providing the input current Iea. The drain of the NMOS transistor M5 is connected to one end of a capacitor C2, and the other end of the capacitor C2 serves as the output terminal of the adaptive loop compensation adjustment circuit Comp_loop. The source of the NMOS transistor M4, the output terminal of the current source I2, and the source of the NMOS transistor M5 are grounded.

[0009] Furthermore, the voltage divider signal fb is provided by a voltage divider circuit, which includes resistors R1 and R2 and capacitor C1. One end of resistor R1 and one end of capacitor C1 are connected to the output signal VOUT. The other end of resistor R1 is connected to the other end of capacitor C1 and one end of resistor R2 to generate the voltage divider signal fb. The other end of resistor R2 is grounded.

[0010] Furthermore, the power stage circuit includes power transistors M1 and M2, an upper transistor pass-through driver HSD&BYPASS_DRIVER, and a lower transistor driver LSD_DRIVER. The input terminal of the upper transistor pass-through driver HSD&BYPASS_DRIVER is connected to the control signal ctl2, and the output terminal of the upper transistor pass-through driver HSD&BYPASS_DRIVER is connected to the gate of power transistor M1. The input terminal of the lower transistor driver LSD_DRIVER is connected to the control signal ctl1, and the output terminal of the lower transistor driver LSD_DRIVER is connected to the gate of power transistor M2. The source terminals of power transistors M1 and M2 are connected to the signal sw. The drain terminal of power transistor M1 generates the output signal VOUT, and the drain terminal of power transistor M2 is grounded.

[0011] A control method for a wide-load, high-stability BOOST circuit includes the following steps: The output voltage of the error amplifier is converted into a current Iea by the voltage-to-current circuit V2I and input to the adaptive loop compensation and adjustment circuit Comp_loop. The current Iea is generated by the voltage divider signal fb of the output signal VOUT, so the current Iea is proportional to the load current. The currents of current sources I1 and I2 are fixed currents Isst. When the current Iea is less than the fixed current Isst, the voltage at node A is pulled down to GND, diode D1 is reverse biased, and the current flowing through NMOS transistor M4 is equal to Isst. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate1, which is a fixed value. The impedance of NMOS transistor M5, which is in the linear region, is inversely proportional to the gate-source voltage VGS. Therefore, the resistance of NMOS transistor M5 is a fixed value Rconst. When the current Iea is greater than the fixed current Isst, diode D1 is forward biased, and the current flowing through NMOS transistor M4 is equal to Iea. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate2, which is a value that varies with the load. This determines that the impedance of NMOS transistor M5, which is in the linear region, changes with the load, thus realizing the adaptive compensation resistor Rcomp adjustment function.

[0012] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a BOOST circuit with high stability under wide load and its control method. When switching between ultra-wide loads, it does not need to sacrifice dynamic performance, but adjusts Rcomp by monitoring the load current to realize the function of the loop bandwidth changing with the zero point of the right half plane, thereby solving the trade-off between transient response and stability under ultra-wide load and improving the performance of the system. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a wide-load, high-stability BOOST circuit according to the present invention.

[0014] Figure 2 This is a schematic diagram of the adaptive loop compensation adjustment circuit Comp_loop of the present invention.

[0015] Figure 3 This is a schematic diagram of the working waveform of a BOOST circuit with wide load and high stability according to the present invention. Detailed Implementation

[0016] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0017] like Figure 1As shown, a wide-load, high-stability BOOST circuit of the present invention includes a power stage circuit and a mode switching circuit. The mode switching circuit generates control signals ctl1 and ctl2 based on the output signal VOUT and provides them to the power stage circuit.

[0018] The mode switching circuit includes an RS flip-flop RS1, an AND gate AND1, a peak comparator PEAK, a valley comparator VALLEY, a pulse frequency modulation counter PFM_TIMER, a voltage-to-current converter V2I, an adaptive loop compensation adjustment circuit Comp_loop, an error amplifier GM, resistors R3 and R4, an NMOS transistor M3, and a capacitor Ccomp. The non-inverting input of the error amplifier GM is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of the error amplifier GM is connected to the input of the voltage-to-current converter V2I and one end of the capacitor Ccomp to generate the signal Vcomp. The other end of the capacitor Ccomp is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded. The first output of the voltage-to-current converter V2I is connected to the input of the adaptive loop compensation adjustment circuit Comp_loop, and the output of the adaptive loop compensation adjustment circuit Comp_loop is connected to the NMOS transistor M3. The gate of transistor M3 is connected to the voltage-to-current circuit V2I. The second output of V2I is connected to the inverting input of the peak comparator PEAK and one end of resistor R4, and the current i_hys is input. The other end of resistor R4 is grounded. The non-inverting input of the peak comparator PEAK is connected to the signal sw. The output of the peak comparator PEAK is connected to the R end of RS flip-flop RS1. The third output of V2I is connected to the inverting input of the valley comparator VALLEY and one end of resistor R3. The fourth output of V2I is connected to the non-inverting input of the valley comparator VALLEY and the other end of resistor R3. The output of the valley comparator VALLEY is connected to the second input of AND gate AND1. The first input of AND gate AND1 is connected to the output of the pulse frequency modulation counter PFM_TIMER. The output of AND gate AND1 is connected to the S end of RS flip-flop RS1. The Q end of RS flip-flop RS1 outputs the control signal ctl1. Output control signal ctl2.

[0019] The adaptive loop compensation circuit Comp_loop includes operational amplifier A1, NMOS transistors M4 and M5, diode D1, current source I1, and current source I2. The non-inverting input of operational amplifier A1 is connected to the reference voltage Vref. The output of operational amplifier A1 is connected to the gates of NMOS transistors M4 and M5 to generate the signal V_gate. The drain of NMOS transistor M4 is connected to node B via the inverting input of operational amplifier A1, the output of current source I1, and the cathode of diode D1. The anode of diode D1 is connected to node A via the input of current source I2 and serves as the input of the adaptive loop compensation circuit Comp_loop, providing the input current Iea. The drain of NMOS transistor M5 is connected to one end of capacitor C2, and the other end of capacitor C2 serves as the output of the adaptive loop compensation circuit Comp_loop. The source of NMOS transistor M4, the output of current source I2, and the source of NMOS transistor M5 are grounded.

[0020] The voltage divider signal fb is provided by a voltage divider circuit, which includes resistors R1 and R2 and capacitor C1. One end of resistor R1 and one end of capacitor C1 are connected to the output signal VOUT. The other end of resistor R1, the other end of capacitor C1, and one end of resistor R2 are connected to generate the voltage divider signal fb. The other end of resistor R2 is grounded.

[0021] The power stage circuit includes power transistors M1 and M2, an upper pass-through transistor driver HSD&BYPASS_DRIVER, and a lower pass-through transistor driver LSD_DRIVER. The input of the upper pass-through transistor driver HSD&BYPASS_DRIVER is connected to the control signal ctl2, and the output of the upper pass-through transistor driver HSD&BYPASS_DRIVER is connected to the gate of power transistor M1. The input of the lower pass-through transistor driver LSD_DRIVER is connected to the control signal ctl1, and the output of the lower pass-through transistor driver LSD_DRIVER is connected to the gate of power transistor M2. The source of power transistor M1 and the source of power transistor M2 are connected to the signal sw. The drain of power transistor M1 generates the output signal VOUT, and the drain of power transistor M2 is grounded.

[0022] This invention is based on a current hysteresis control architecture. The voltage divider signal fb and the reference voltage generate a control voltage Vcomp through the error amplifier EA. The NMOS transistor M3 and capacitor Ccomp form a loop compensation network. The error of the output voltage collected by the error amplifier EA is directly converted into current by the voltage-to-current circuit V2I, and conducted to the peak comparator PEAK and the valley comparator VALLEY. These two comparators generate control signals for the upper and lower transistors. By adding an inductor current hysteresis window, the ripple of the inductor current can be controlled, thereby controlling the ripple of the output voltage. Therefore, the current generated by the voltage-to-current circuit V2I is directly related to the inductor current. When the load current changes, the output voltage of the error amplifier EA will adjust, and the current generated by the voltage-to-current circuit V2I will also change accordingly. This current is converted into a step function voltage by the adaptive loop compensation circuit Comp_loop. This voltage is used to control a voltage-controlled linear resistor, thereby adjusting the compensation resistor Rcomp. According to the formula for the loop bandwidth UGB of BOOST under CCM: UGB=(gm Rc D') / (2pi Rsns By adjusting Rcomp (Co), the bandwidth can be adjusted, thereby ensuring the stability of the system.

[0023] A control method for a wide-load, high-stability BOOST circuit includes the following steps: The output voltage of the error amplifier is converted into a current Iea by the voltage-to-current circuit V2I and input to the adaptive loop compensation and adjustment circuit Comp_loop. The current Iea is generated by the voltage divider signal fb of the output signal VOUT, so the current Iea is proportional to the load current.

[0024] The currents of current sources I1 and I2 are fixed currents Isst. When the current Iea is less than the fixed current Isst, the voltage at node A is pulled down to GND, diode D1 is reverse biased, and the current flowing through NMOS transistor M4 is equal to Isst. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate1, which is a fixed value. The impedance of NMOS transistor M5, which is in the linear region, is inversely proportional to the gate-source voltage VGS. Therefore, the resistance of NMOS transistor M5 is a fixed value Rconst.

[0025] When the current Iea is greater than the fixed current Isst, diode D1 is forward biased, and the current flowing through NMOS transistor M4 is equal to Iea. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate2, which is a value that varies with the load. This determines that the impedance of NMOS transistor M5, which is in the linear region, changes with the load, thus realizing the adaptive compensation resistor Rcomp adjustment function.

[0026] like Figure 3 As shown, when the load current suddenly switches from a light load to a heavy load, the right half-plane zero point Fzrhp suddenly decreases and gradually approaches the bandwidth, causing the system to become unstable. However, the decrease in output voltage causes the output voltage Vcomp of the error amplifier EA to gradually increase, and the current in the voltage-to-current conversion circuit V2I increases. Because of the adaptive loop compensation adjustment circuit Comp_loop control with a step function, changes within a certain load range do not cause changes in the resistance Rcomp. However, when the load changes drastically, the affected voltage-controlled resistor Rcomp will also decrease drastically, reducing the loop bandwidth and thus ensuring loop stability. When the heavy load is removed, Rcomp returns to its previous normal design value, and the loop bandwidth increases again, ensuring good transient performance. This solves the trade-off between transient response and stability under ultra-wide load conditions and improves system performance.

[0027] This invention provides a wide-load, high-stability BOOST circuit and its control method. During ultra-wide load switching, dynamic performance is not sacrificed. Instead, Rcomp is adjusted by monitoring the load current to achieve the function of loop bandwidth changing with the zero point of the right half-plane. This solves the trade-off between transient response and stability under ultra-wide loads and improves system performance.

[0028] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A BOOST circuit with wide load range and high stability, characterized in that: It includes a power stage circuit and a mode switching circuit. The mode switching circuit generates control signals ctl1 and ctl2 based on the output signal VOUT and provides them to the power stage circuit.

2. The BOOST circuit with wide load and high stability according to claim 1, characterized in that: The mode switching circuit includes an RS flip-flop RS1, an AND gate AND1, a peak comparator PEAK, a valley comparator VALLEY, a pulse frequency modulation counter PFM_TIMER, a voltage-to-current converter V2I, an adaptive loop compensation adjustment circuit Comp_loop, an error amplifier GM, resistors R3 and R4, an NMOS transistor M3, and a capacitor Ccomp. The non-inverting input of the error amplifier GM is connected to the reference voltage vref, and the inverting input is connected to the voltage divider signal fb. The output of the error amplifier GM is connected to the input of the voltage-to-current converter V2I and one end of the capacitor Ccomp to generate the signal Vcomp. The other end of the capacitor Ccomp is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded. The first output of the voltage-to-current converter V2I is connected to the input of the adaptive loop compensation adjustment circuit Comp_loop, and the output of the adaptive loop compensation adjustment circuit Comp_loop is connected to the NMOS transistor M3. The gate of S-channel MOSFET M3 is connected to the inverting input of peak comparator PEAK and one end of resistor R4, which is then connected to input current i_hys. The other end of resistor R4 is grounded. The non-inverting input of peak comparator PEAK is connected to signal sw. The output of peak comparator PEAK is connected to the R terminal of RS flip-flop RS1. The third output of voltage-to-current circuit V2I is connected to the inverting input of valley comparator VALLEY and one end of resistor R3. The fourth output of voltage-to-current circuit V2I is connected to the non-inverting input of valley comparator VALLEY and the other end of resistor R3. The output of valley comparator VALLEY is connected to the second input of AND gate AND1. The first input of AND gate AND1 is connected to the output of pulse frequency modulation counter PFM_TIMER. The output of AND gate AND1 is connected to the S terminal of RS flip-flop RS1. The Q terminal of RS flip-flop RS1 outputs control signal ctl1. Output control signal ctl2.

3. The BOOST circuit with wide load and high stability according to claim 2, characterized in that: The adaptive loop compensation and adjustment circuit Comp_loop includes an operational amplifier A1, an NMOS transistor M4, an NMOS transistor M5, a diode D1, a current source I1, and a current source I2. The non-inverting input of operational amplifier A1 is connected to a reference voltage Vref. The output of operational amplifier A1 is connected to the gates of NMOS transistors M4 and M5 to generate a signal V_gate. The drain of NMOS transistor M4 is connected to node B via the inverting input of operational amplifier A1, the output of current source I1, and the cathode of diode D1. The anode of diode D1 is connected to node A via the input of current source I2 and serves as the input of the adaptive loop compensation and adjustment circuit Comp_loop, providing the input current Iea. The drain of NMOS transistor M5 is connected to one end of capacitor C2, and the other end of capacitor C2 serves as the output of the adaptive loop compensation and adjustment circuit Comp_loop. The source of NMOS transistor M4, the output of current source I2, and the source of NMOS transistor M5 are grounded.

4. The BOOST circuit with wide load and high stability according to claim 2, characterized in that: The voltage divider signal fb is provided by a voltage divider circuit, which includes resistors R1 and R2 and capacitor C1. One end of resistor R1 and one end of capacitor C1 are connected to the output signal VOUT. The other end of resistor R1 is connected to the other end of capacitor C1 and one end of resistor R2 to generate the voltage divider signal fb. The other end of resistor R2 is grounded.

5. The BOOST circuit with wide load and high stability according to claim 1, characterized in that: The power stage circuit includes power transistors M1 and M2, an upper pass-through transistor driver HSD&BYPASS_DRIVER, and a lower pass-through transistor driver LSD_DRIVER. The input of the upper pass-through transistor driver HSD&BYPASS_DRIVER is connected to the control signal ctl2, and the output of the upper pass-through transistor driver HSD&BYPASS_DRIVER is connected to the gate of power transistor M1. The input of the lower pass-through transistor driver LSD_DRIVER is connected to the control signal ctl1, and the output of the lower pass-through transistor driver LSD_DRIVER is connected to the gate of power transistor M2. The source of power transistor M1 and the source of power transistor M2 are connected to the signal sw. The drain of power transistor M1 generates the output signal VOUT, and the drain of power transistor M2 is grounded.

6. A control method for a wide-load, high-stability BOOST circuit as described in claim 3, characterized in that... Includes the following steps: The output voltage of the error amplifier is converted into a current Iea by the voltage-to-current circuit V2I and input to the adaptive loop compensation and adjustment circuit Comp_loop. The current Iea is generated by the voltage divider signal fb of the output signal VOUT, so the current Iea is proportional to the load current. The currents of current sources I1 and I2 are fixed currents Isst. When the current Iea is less than the fixed current Isst, the voltage at node A is pulled down to GND, diode D1 is reverse biased, and the current flowing through NMOS transistor M4 is equal to Isst. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate1, which is a fixed value. The impedance of NMOS transistor M5, which is in the linear region, is inversely proportional to the gate-source voltage VGS. Therefore, the resistance of NMOS transistor M5 is a fixed value Rconst. When the current Iea is greater than the fixed current Isst, diode D1 is forward biased, and the current flowing through NMOS transistor M4 is equal to Iea. NMOS transistor M4 is in the saturation region. At this time, the gate-source voltage VGS of NMOS transistor M4 is Vgate2, which is a value that varies with the load. This determines that the impedance of NMOS transistor M5, which is in the linear region, changes with the load, thus realizing the adaptive compensation resistor Rcomp adjustment function.

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