by the device

Abstract

This disclosure relates to a pass device. An apparatus including a pass device is provided. The pass device includes a plurality of transistor slices coupled in parallel. Each of the plurality of transistor slices includes a switching transistor configured to switch between an on state and an off state, and a current source transistor coupled in series with the switching transistor and configured to set a first current flowing in the transistor slice when the switching transistor is in the on state.

Description

[0001] This disclosure relates to a device. background

[0002] Figure 1 This is a schematic diagram of a known digital low-dropout regulator (LDO) 100, used to receive an input voltage Vi and generate an output voltage Vo, which is then supplied to a load 101. The digital LDO 100 includes an error amplifier 102 between a reference voltage Vref and an output voltage Vo, control logic circuitry 104, and a pass device 106.

[0003] Device 106 includes an array of low-power transistors 108 that operate as switches.

[0004] Figure 1 Each transistor 108 in the array is part of a "slice", and the combination of all slices is considered a "total through device". Using power transistors as switches facilitates low VDD power management and process scalability, making digital LDOs a good potential candidate for power management as we move into smaller nodes.

[0005] One of the main drawbacks of digital LDOs is the poor control over the current delivered by each individual segment (slice) of the total pass device when the total pass device is activated. This is due to the fact that the operating regions of the activated transistors can be different due to the voltage drop of the LDO, thus producing different Vds (drain-to-source voltage in the case of NMOS) or Vsd (source-to-drain voltage in the case of PMOS).

[0006] This means that for the same number of active slices, the total delivery current can vary depending on the voltage drop. In other words, the total maximum deliverable current is highly dependent on process, voltage, and temperature variations, as the delivered current can differ significantly with the same number of active slices. Therefore, to have accurate information about the total delivery current, a separate current sensing circuit is required, which increases the circuit's complexity, size, and power requirements.

[0007] Other solutions provide a reference branch, where a known current is applied to a reference transistor so that when other slices are activated, the conditions seen by the reference transistor (i.e., drain and source voltages) are replicated on the activated slice. The drawback of this architecture is that even the reference transistor may experience changes in its operating conditions, depending on the voltage drop across the transistor and saturation region, and the quality of the current replication deteriorates.

[0008] Overview

[0009] It is desirable to provide an improved pass device that mitigates or overcomes one or more of the aforementioned problems.

[0010] According to a first aspect of the present disclosure, an apparatus is provided comprising a through device including a plurality of transistor slices coupled in parallel, wherein each of the plurality of transistor slices includes a switching transistor and a current source transistor, the switching transistor being configured to switch between an on state and an off state, and the current source transistor being coupled in series with the switching transistor and configured to set a first current flowing in the transistor slice when the switching transistor is in the on state.

[0011] Optionally, the first current of each of the plurality of transistor slices is approximately equal to the first current of the other transistor slices.

[0012] Optionally, the device includes a reference circuit configured to control a current source transistor to set a first current for each of a plurality of transistor slices.

[0013] Optionally, the switching transistor of each of the plurality of transistor slices includes a switching metal-oxide-semiconductor field-effect transistor (MOSFET); and / or the current source transistor of each of the plurality of transistor slices includes a current source MOSFET.

[0014] Optionally, the switching MOSFET of each of the plurality of transistor slices includes a first switching terminal and a second switching terminal coupled to the input terminal, and the current source MOSFET of each of the plurality of transistor slices includes a first current source terminal coupled to the second switching terminal, a second current source terminal coupled to the output terminal, and a current source gate terminal.

[0015] Optionally, the switching MOSFET of each of the plurality of transistor slices is configured to operate in its transistor region, and / or the current source MOSFET of each of the plurality of transistor slices is configured to operate in its transistor region.

[0016] Optionally, the current source gate terminals of each of the current source MOSFETs are coupled together, and the second current source terminals of each of the current source MOSFETs are coupled together.

[0017] Optionally, the device includes a reference circuit configured to control a current source transistor to set a first current for each of a plurality of transistor slices, wherein the first current for each of the plurality of transistor slices is approximately equal to the first current for the other transistor slices.

[0018] Optionally, the reference circuit includes a reference slice comprising a switching reference transistor and a current source reference transistor. The switching reference transistor includes a switching reference MOSFET, and the current source reference transistor includes a current source reference MOSFET. The switching reference MOSFET includes a first switching reference terminal and a second switching reference terminal coupled to an input terminal, and the current source reference MOSFET includes a first current source reference terminal coupled to the second switching reference terminal, a second current source reference terminal coupled to an output terminal, and a current source reference gate terminal. The current source gate terminal of each of the current source MOSFETs is coupled to the current source reference gate terminal, and the second current source terminal of each of the current source MOSFETs is coupled to the second current source reference terminal.

[0019] Optionally, the reference circuit includes a reference current controller configured to control a reference slice to set a second current flowing in the reference slice, such that the reference slice controls a current source transistor to set a first current for each of a plurality of transistor slices, the first current for each of the plurality of transistor slices depending on the second current.

[0020] Alternatively, the second current may be approximately equal to the first current of each of the plurality of transistor slices.

[0021] Optionally, the reference current controller is configured to receive a reference current, the second current being dependent on the reference current.

[0022] Optionally, the second current is approximately equal to the reference current.

[0023] Optionally, the reference current controller includes a reference MOSFET, a reference resistor element, a first amplifier, and a second amplifier. The reference MOSFET includes a first reference MOSFET terminal, a second reference MOSFET terminal coupled to an output terminal, and a reference MOSFET gate terminal coupled to a current source reference gate terminal. The first amplifier includes a first amplifier first input terminal coupled to the first reference MOSFET terminal, a first amplifier second input terminal coupled to the output terminal via the reference resistor element, and a first amplifier output node coupled to the reference MOSFET gate terminal. The second amplifier includes a second amplifier first input terminal coupled to the first current source reference terminal, a second amplifier second input terminal coupled to the first amplifier first input terminal, and a second amplifier output terminal coupled to the switching reference MOSFET's switching reference gate terminal.

[0024] Optionally, each of the plurality of transistor slices includes a buffer circuit configured to provide a gate drive voltage to drive the switching MOSFET, the gate drive voltage being approximately equal to the output voltage provided by the second amplifier to the switch reference gate terminal.

[0025] Optionally, a reference current is received at the first input terminal and the second input terminal of the first amplifier.

[0026] Optionally, the device may include electrostatic discharge (ESD) protection circuitry.

[0027] Optionally, each of the plurality of transistor slices includes an ESD protection module of ESD protection circuitry, each of the ESD protection modules being coupled to an input terminal and an output terminal. During a positive ESD event at the output node, each of the ESD protection modules is configured to provide a first discharge path to a first power supply voltage and a second discharge path to a second power supply voltage, and / or during a negative ESD event at the output node, each of the ESD protection modules is configured to provide a third discharge path to the first power supply voltage and a fourth discharge path to the second power supply voltage.

[0028] Optionally, each of the ESD protection modules includes an active clamping circuit and / or a gate-coupled n-type metal-oxide-semiconductor (GCNMOS), a back-to-back diode circuit, and a body diode of a switching transistor.

[0029] Optionally, the first discharge path is provided by an active clamping circuit and / or a gate-coupled n-type metal-oxide-semiconductor (GCNMOS) and back-to-back diode circuit; the second discharge path is provided by the body diode of the switching transistor; the third discharge path is provided by an active clamping circuit and / or a gate-coupled n-type metal-oxide-semiconductor (GCNMOS) and back-to-back diode circuit; and the fourth discharge path is provided by an active clamping circuit and / or a gate-coupled n-type metal-oxide-semiconductor (GCNMOS) and back-to-back diode circuit.

[0030] Optionally, each of the plurality of transistor slices includes an ESD protection module of ESD protection circuitry, and each of the ESD protection modules is coupled to a second current source terminal and configured to discharge the current source gate terminal and / or the first current source terminal.

[0031] Optionally, the device includes a low-dropout regulator (LDO) for receiving an input voltage and for providing an output voltage to an electrical load, the LDO including a pass device.

[0032] Optionally, the low-dropout regulator includes an LDO amplifier and control logic circuitry. The LDO amplifier is configured to receive a reference voltage and an output voltage, and generate a control signal dependent on the reference voltage and the output voltage. The control logic circuitry is configured to drive switching operations of the device dependent on the control signal.

[0033] According to a second aspect of this disclosure, a method of providing a device is provided, the method comprising providing a plurality of transistor slices coupled in parallel, wherein each of the plurality of transistor slices includes a switching transistor and a current source transistor, the switching transistor being configured to switch between an on state and an off state, the current source transistor being coupled in series with the switching transistor and configured to set a first current flowing in the transistor slice when the switching transistor is in the on state.

[0034] It should be recognized that the approach of the second aspect may include the use and / or provision of any features described in the first aspect, and may include other features as set forth herein. Brief description of the attached diagram

[0035] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0036] Figure 1 This is a schematic diagram of a known digital low-dropout regulator (LDO);

[0037] Figure 2A This is a schematic diagram of an apparatus including a device according to a first embodiment of the present disclosure. Figure 2B This is a schematic diagram of an apparatus including a specific embodiment of a device according to a second embodiment of the present disclosure;

[0038] Figure 3 This is a schematic diagram of a specific embodiment of an apparatus including a device and a reference circuit according to a third embodiment of the present disclosure;

[0039] Figure 4A This is a schematic diagram of an apparatus including a passing device and a reference circuit according to a fourth embodiment of the present disclosure. Figure 4B This is a schematic diagram of a transistor slice of a specific embodiment of an ESD protection module, including a specific embodiment of the ESD protection circuit; and

[0040] Figure 5 This is an apparatus according to the fifth embodiment of the present disclosure, including an LDO having a through device. Detailed description

[0041] Figure 2A This is a schematic diagram of an apparatus 200 including a device 202 according to a first embodiment of the present disclosure.

[0042] Device 202 includes a plurality of transistor slices 204a, 204b coupled in parallel. In this example, two transistor slices 204a, 204b are shown. However, it should be appreciated that in other embodiments, device 202 may include more than two transistor slices 204a, 204b.

[0043] Each of the plurality of transistor plates 204a, 204b includes switching transistors 206a, 206b and current source transistors 208a, 208b, the switching transistors 206a, 206b being configured to switch between an on state and an off state, the current source transistors 208a, 208b being coupled in series with the switching transistors 206a, 206b and being configured to allow currents I1a, I1b to flow in the transistor plates 204a, 204b when the switching transistors 206a, 206b are in the on state.

[0044] For example, in this embodiment, transistor slice 204a includes a switching transistor 206a and a current source transistor 208a. The current source transistor 208a is configured to allow current I1a to flow in transistor slice 204a when the switching transistor 206a is in a conducting state. Furthermore, transistor slice 204b includes a switching transistor 206b and a current source transistor 208b. The current source transistor 208b is configured to allow current I1b to flow in transistor slice 204b when the switching transistor 206b is in a conducting state.

[0045] In a particular embodiment, the currents I1a and I1b of all transistor slices 204a and 204b can be approximately equal. For example, current I1a can be approximately equal to current I1b.

[0046] The switching transistors 206a and 206b may each include switching metal-oxide-semiconductor field-effect transistors (MOSFETs) 210a and 210b, which may be, for example, p-type MOSFETs or n-type MOSFETs.

[0047] The current source transistors 208a and 208b may each include current source metal-oxide-semiconductor field-effect transistors (MOSFETs) 212a and 212b, which may be, for example, p-type MOSFETs or n-type MOSFETs.

[0048] Each transistor slice 204a, 204b may include switching MOSFETs 210a, 210b coupled to input terminal 214, and switching terminals T1a, T1b.

[0049] Each of the transistor slices 204a and 204b may include current source MOSFETs 212a and 212b coupled to switch terminals T2a and T2b, current source terminals T4a and T4b coupled to output terminal 215, and current source gate terminals G1a and G1b.

[0050] For example, in this embodiment, the switching transistor 206a includes a switching MOSFET 210a. The switching MOSFET 210a includes a switching terminal T1a and a switching terminal T2a coupled to the input terminal 214.

[0051] For example, in this embodiment, the switching transistor 206b includes a switching MOSFET 210b. The switching MOSFET 210b includes a switching terminal T1b and a switching terminal T2b coupled to the input terminal 214.

[0052] For example, in this embodiment, the current source transistor 208a includes a current source MOSFET 212a. The current source MOSFET 212a includes a current source terminal T3a coupled to the switching terminal T2a, a current source terminal T4a, and a current source gate terminal G1a.

[0053] For example, in this embodiment, the current source transistor 208b includes a current source MOSFET 212b. The current source MOSFET 212b includes a current source terminal T3b coupled to the switching terminal T2b, a current source terminal T4b, and a current source gate terminal G1b.

[0054] Each switching MOSFET 210a, 210b can be configured to operate in its transistor region, and / or each current source MOSFET 212a, 212b can be configured to operate in its transistor region.

[0055] Figure 2B This is a schematic diagram of a device 216 including a specific embodiment of the device 202 according to a second embodiment of the present disclosure.

[0056] In this embodiment, device 216 includes a reference circuit 218 configured to control current source transistors 208a and 208b to set currents I1a and I1b for each of a plurality of transistor slices 204a and 204b. The reference circuit 218 can control the current source transistors 208a and 208b such that currents I1a and I1b are approximately equal to each other.

[0057] The current source gate terminals G1a and G1b of each of the current source MOSFETs 212a and 212b can be coupled together. The current source terminals T4a and T4b of each of the current source MOSFETs 212a and 212b can be coupled together.

[0058] Figure 3 This is a schematic diagram of an apparatus 300 according to a third embodiment of the present disclosure, including a device 202 and a reference circuit 218.

[0059] In this embodiment, the reference circuit 218 includes a reference slice 302, which includes a switching reference transistor 304 and a current source reference transistor 308. The switching reference transistor 304 includes a switching reference MOSFET 306, and the current source reference transistor 308 includes a current source reference MOSFET 310.

[0060] The switching reference MOSFET 306 includes a switching reference terminal T5a coupled to the input terminal 214 and a switching reference terminal T6a. The current source reference MOSFET 310 includes a current source reference terminal T7a coupled to the switching reference terminal T6a, a current source reference terminal T8a coupled to the output terminal 215, and a current source reference gate terminal G2a.

[0061] The current source gate terminals G1a and G1b of each of the current source MOSFETs 212a and 212b are coupled to the current source reference gate terminal G2a, and the current source terminals T4a and T4b of each of the current source MOSFETs 212a and 212b are coupled to the current source reference terminal T8a.

[0062] The reference circuit 218 may include a reference current controller 312 configured to control the reference slice 302 to set the current I2a to flow in the reference slice 302, such that the reference slice 302 controls the current source transistors 208a, 208b to set the currents I1a, I1b.

[0063] The currents I1a and I1b of each of the multiple transistor slices 204a and 204b depend on the current I2a. In a particular embodiment, the current I2a may be approximately equal to the currents I1a and I1b.

[0064] The reference current controller 312 can be configured to receive a reference current Iref. Current I2a depends on the reference current Iref. In a particular embodiment, current I2a may be approximately equal to the reference current Iref. In another particular embodiment, currents I1a, I1b, I2a, and Iref may be approximately equal.

[0065] The reference current controller 312 may include a reference MOSFET 314 (also designated B). REF Reference MOSFET 314 includes reference MOSFET terminal T9a, reference MOSFET terminal T10a coupled to output terminal 215, and reference MOSFET gate terminal G3a coupled to current source reference gate terminal G2a.

[0066] The reference current controller 312 may also include a reference resistor element Rref.

[0067] The reference current controller 312 may also include an amplifier AMP1, which includes an amplifier input terminal T11a coupled to a reference MOSFET terminal T9a, an amplifier input terminal T12a coupled to an output terminal 215 via a reference resistor element Rref, and an amplifier output node T13a coupled to a reference MOSFET gate terminal G3a.

[0068] The reference current controller 312 may also include an amplifier AMP2, which includes an amplifier input terminal T14a coupled to the first current source reference terminal T7a, an amplifier input terminal T15a coupled to the amplifier input terminal T11a, and an amplifier output terminal T16a coupled to the switch reference gate terminal G4a coupled to the switch reference MOSFET 306.

[0069] Each of the plurality of transistor slices 204a, 204b may include buffer circuits 316a, 316b configured to provide a gate drive voltage to drive the switching MOSFETs 210a, 210b. The gate drive voltage may be approximately equal to the output voltage provided by amplifier AMP2 to the switch reference gate terminal G4a.

[0070] The reference current Iref can be received at the amplifier input terminals T11a and T12a. The reference current Iref can be provided from one or more current sources 318 and 320.

[0071] In short, with such Figure 1 Compared to the known transducers presented in the example, a second “bottom” MOSFET is added to each transistor slice, which controls the current flowing through the original “top” MOSFET. In this example, the “bottom” MOSFETs are current source MOSFETs 212a and 212b (also labeled B1 and B). N The "top" MOSFETs are switching MOSFETs 210a and 210b (also labeled T1 and T). N ).

[0072] Compared to known through devices, each slice of through device 300 has been "divided" into two devices in series, one used as a switch ("top" MOSFET, T1...T...). N Another ideal, precise current source (“bottom” MOSFET, B1…B) is used to set the current flowing through each slice. N ).

[0073] In this example, the MOSFETs in transistor slices 204a and 204b are n-type MOSFETs. However, it should be recognized that in other embodiments, one or more of the MOSFETs may be p-type MOSFETs.

[0074] In this example, the gates of the bottom MOSFETs 212a and 212b are shorted together, and the sources of the bottom MOSFETs 212a and 212b are shorted together.

[0075] Reference slice 302 also includes a top MOSFET T0 (switching reference MOSFET 306) and a bottom MOSFET B0 (current source reference MOSFET 310).

[0076] The source of each bottom MOSFET 212a, 212b is coupled to the output terminal 215 of slices 204a, 204b, while the gates of all bottom MOSFETs 212a, 212b are directly coupled to the gate of the bottom MOSFET 310 of reference slice 302. Therefore, for each slice, all bottom MOSFETs, i.e., B1…B N The gate-source voltage Vgs is mirrored by the gate-source voltage Vgs of the bottom MOSFET B0 on ​​the reference branch.

[0077] In this embodiment, where currents Iref, I2a, I1a, and I1b are approximately equal, during operation, the reference current controller 312 ensures that the current I2a flowing through the bottom MOSFET 310 is approximately equal to the reference current Iref.

[0078] In this embodiment, during operation, reference circuit 218 ensures that the MOSFETs in each slice 204a, 204b are always in the same operating region, i.e., the transistor region, with precise current control for each individual slice (each active slice provides a current equal to Iref).

[0079] In this embodiment, reference circuit 218 ensures that the correct drain-source voltage Vds is provided to MOSFETs 310, 212a, and 212b so that a predefined reference current Iref flows through them when they conduct. In this example, this is achieved by ensuring that reference MOSFET 314 has the same size and characteristics as MOSFETs 310, 212a, and 212b, wherein reference MOSFET 314 is as follows: Figure 3 As shown in the figure, it is coupled to amplifier Amp1 and reference resistor element Rref.

[0080] During operation, the reference current Iref flows through the reference resistor element Rref, which generates a voltage drop Vds_1 that is replicated to the drain-source voltage Vds of the reference MOSFET 314. Therefore, the reference circuit 218 can be considered to have "determined" what drain-source voltage Vds needs to be applied to the bottom MOSFETs 310, 204a, 204b to act as the current source providing the current Iref, i.e., Vds_1.

[0081] During operation, amplifier AMP2 supplies Vds_1, i.e., Vds_2, to the current source reference MOSFET 310. Since the reference MOSFET 314 and the current source reference MOSFET 310 have the same voltage at their respective terminals, the current flowing through reference slice 302 is equal to the reference current Iref. The gates of the bottom MOSFETs 204a and 204b can be directly coupled to the gate of the reference MOSFET 310, and / or the sources of the bottom MOSFETs 204a and 204b can be directly coupled to the source of the reference MOSFET 310.

[0082] Buffer circuits 316a and 316b can be digital buffers. During operation, buffer circuits 316a and 316b drive the gate of the upper high-voltage (HV) MOS switch (MOSFET 210a, 210b) to the same gate level as the HV MOS (switch reference MOSFET 306). Figure 3 (VGH is denoted as VGH in the diagram). The switching MOSFETs 210a and 210b can be matched in layout such that when the subsequent snubber circuits 316a and 316b each supply a gate voltage Vg to their respective switching MOSFETs 210a and 210b to turn on their MOSFETs, each of the MOSFETs 210a and 210b that is turned on is expected to have the same Vds_2 as the switching reference MOSFET 306. Therefore, the operating points of all transistors 210a, 210b, 212a, and 212b in each slice 204a and 204b of device 202 are known and controlled to match the operating points of the corresponding transistors 306 and 310 on the reference slice 302.

[0083] In this example, the top MOSFET is a high-voltage (HV) MOSFET and the bottom MOSFET is a low-voltage (LV) MOSFET. Using a high-voltage MOSFET at the top and a low-voltage MOSFET at the bottom maximizes the dropout and mismatch performance. However, it should be recognized that in other embodiments, one or more of the top MOSFETs may be implemented using either an HV MOSFET or an LV MOSFET, and one or more of the bottom MOSFETs may also be implemented using either an HV MOSFET or an LV MOSFET.

[0084] This example includes two transistor slices 204a and 204b. However, as will be understood by those skilled in the art, other embodiments may include more than two transistor slices having top and bottom MOSFETs arranged as described for this example.

[0085] Embodiments of this disclosure provide a precise way to know the exact amount of current that each transistor slice of a through device can deliver under all operating conditions. This allows for more precise management of the output (e.g., by being able to reconstruct the total delivered current simply by knowing the number of active slices) and reduces the need for current sensing circuitry, thereby providing an improved through device compared to known systems.

[0086] Figure 4A This is a schematic diagram of an apparatus 400 including a through device 202 and a reference circuit 218 according to a fourth embodiment of the present disclosure. The through device 202 and / or the reference circuit 218 can be implemented using any of the specific embodiments described herein, as can be known to those skilled in the art. In this embodiment, the through device 202 further includes an electrostatic discharge (ESD) protection circuit 402 for protecting the through device 202 from ESD.

[0087] Using the shunting device architecture and design method of this disclosure, issues may arise regarding the cascode (intermediate) network (the common series connection node between the LV MOS drain and HV MOS source) of the corresponding slice. Transient charge buildup / voltage distribution on these cascode (intermediate) networks can lead to damage to the core LV NMOS gate oxide (GOX). To mitigate the possibility of ESD-related damage, embodiments of this disclosure may include ESD protection circuitry 402.

[0088] Figure 4B This is a schematic diagram of a specific embodiment of a transistor slice 204a of an ESD protection module 404 including a specific embodiment of an ESD protection circuit 402.

[0089] It should be understood that the ESD protection circuit 402 may include a plurality of ESD protection modules 404, wherein the ESD protection module is implemented in each of the transistor slices 204a and 204b. As will be understood by those skilled in the art, the ESD protection module of each slice may be implemented as described for the ESD protection module 404 of this embodiment. Additionally, other ESD protection modules, which may be implemented as described for the ESD protection module 402, may also be included as part of the reference slice 302 to provide ESD protection to the reference slice 302.

[0090] ESD protection module 404 is coupled to input terminal 214 and output terminal 215.

[0091] During a positive ESD event at output terminal 215, ESD protection module 404 can be configured to provide discharge path D1 to power supply voltage VSSA and discharge path D2 to power supply voltage VDD.

[0092] During negative ESD events at output terminal 215, ESD protection module 404 is configured to provide discharge path D3 to power supply voltage VSSA and discharge path D4 to power supply voltage VDD.

[0093] The ESD protection module 404 in this embodiment includes an active clamping circuit 406. In another embodiment, the ESD protection module may additionally or alternatively include a gate-coupled n-type metal-oxide-semiconductor (GCNMOS).

[0094] The ESD protection module 404 in this embodiment also includes a back-to-back diode circuit 408 and a body diode 410 of the switching transistor 206a.

[0095] Discharge path D1 can be provided by active clamping circuit 406 and back-to-back diode circuit 408. In another embodiment, discharge path D1 can be provided by GCNMOS and back-to-back circuit 408. Discharge path D1 to VSSA can eventually be grounded.

[0096] like Figure 4B As shown, the ESD discharge path D1 to the VSSA, which ultimately grounds (GND), can be provided by one of the back-to-back (B2B) diodes of the active clamping circuit 406 and the back-to-back diode circuit 408.

[0097] The discharge path D2 can be provided by the body diode 410.

[0098] Discharge path D3 can be provided by active clamping circuit 406 and back-to-back diode circuit 408. In another embodiment, discharge path D3 can be provided by GCNMOS and back-to-back circuit 408. Discharge path D3 to VSSA can ultimately be grounded.

[0099] The ESD discharge path D3 to VSSA, which ultimately leads to VSS_ESD (GND), can be provided by one of the built-in body diode in the BigFET embedded in the active clamping circuit 406 and the B2B (back-to-back) diode in the back-to-back diode circuit 408.

[0100] Discharge path D4 can be provided by active clamping circuit 406 and back-to-back diode circuit 408. In another embodiment, discharge path D4 can be provided by GCNMOS and back-to-back circuit 408.

[0101] The ESD discharge path D4 to VDD can be provided by the built-in body diode in the BigFET that is embedded in the active clamping circuit 406 (or, in another embodiment including GCNMOS, GCNMOS).

[0102] The discharge paths D1, D2, D3, and D4 are provided using an active clamping circuit 406 (or GCNMOS), a back-to-back diode circuit 408, and a body diode 410, providing primary human model (HBM) ESD protection for the digital LDO output when implemented in an LDO. HBM ESD protection is achieved through the implementation of active clamping (or GCNMOS) and by utilizing the self-protection capability of the built-in body diodes of NMOS transistors 210a and 212a.

[0103] MOSFET 210a can be referred to as I / O NMOS or I / O HV NMOS. MOSFET 212a can be referred to as core LV NMOS.

[0104] ESD protection module 404 can be coupled to current source terminal T4a and configured to discharge current source gate terminal G1a and / or current source terminal T3a. ESD protection module 404 may include secondary charge device module (CDN) clamping circuit 412 coupled to gate terminal G1a and terminal T4a; secondary CDM clamping circuit 414 coupled to terminal T3a; and secondary CDM clamping circuit 416 coupled to CDM clamping circuits 412, 414.

[0105] The secondary CDM clamping circuit ESD protection scheme is implemented between the gate and source of MOSFET 212a and between the common-source gate (intermediate) node and source of the corresponding MOSFET 212a (which is also the output node 215 of the digital LDO when implemented as part of a digital LDO), which can be provided by an active clamping circuit or an ESD diode (not shown).

[0106] During operation, CDM clamping circuits 412, 414, and 416 can rapidly discharge the gate and intermediate cascode nodes of the core NMOS (MOSFET 212a), thereby preventing excessive charge accumulation at these nodes to avoid any potential gate oxide (GOX) damage. It should be recognized that CDM clamping circuitry can be present in all slices of device 202 and reference slice 302.

[0107] It should be recognized that, further, the ESD protection module 404 may only provide information about Figure 4B This describes one type of ESD protection method. For example, one embodiment can provide HBM ESD protection by implementing an active clamping circuit (or GCNMOS) and utilizing the self-protection capability of the built-in body diodes of NMOS transistors 210a, 212a. Another embodiment can provide secondary CDM protection by using one or more of CDM clamping circuits 412, 414, 416. Further embodiments can provide both HBM ESD protection and secondary CDM ESD protection, as is the case in this embodiment.

[0108] Figure 5 The device 500 according to the fifth embodiment of this disclosure includes an LDO 502 having a through device 202. The LDO 502 is used to receive an input voltage Vi and to provide an output voltage Vo to a load 503.

[0109] LDO 502 includes an amplifier 504 configured to receive a reference voltage Vref and an output voltage Vo. Amplifier 504 is also configured to generate a control signal 506 dependent on the reference voltage Vref and the output voltage Vo. LDO 502 also includes control logic circuitry 508 configured to drive switching operations through device 202 dependent on the control signal 506.

[0110] It should be recognized that some reference figures in this figure have been omitted for the sake of clarity.

[0111] The pass device 202 in this embodiment includes reference slices 509a and 509b. Reference slice 509a includes a switching MOSFET 510a and a current source MOSFET 512a. Reference slice 509b includes a switching MOSFET 510b and a current source MOSFET 512b. It should be appreciated that, in another embodiment, as understood by those skilled in the art, the pass device 202 can be implemented as any of the pass device embodiments described herein. Additionally, the device 500 may also include a reference circuit 218 and / or an ESD protection circuit 402. The reference circuit 218 can be implemented as any of the reference circuit embodiments described herein, and the ESD protection circuit 402 can be implemented as any of the ESD protection circuit embodiments described herein.

[0112] Common reference figures and variables in the accompanying figures represent common features.

[0113] Various improvements and modifications can be made to the above content without departing from the scope of this disclosure.

[0114] This application includes, but is not limited to, the following terms:

[0115] Clause 1. An apparatus comprising:

[0116] The device comprises a plurality of transistor slices coupled in parallel; wherein each of the plurality of transistor slices includes:

[0117] A switching transistor, configured to switch between an on state and an off state; and

[0118] A current source transistor is coupled in series with a switching transistor and configured to set a first current to flow in the transistor slice when the switching transistor is in the on state.

[0119] Clause 2. The apparatus according to Clause 1, wherein the first current of each of the plurality of transistor slices is approximately equal to the first current of the other transistor slices.

[0120] Clause 3. The apparatus according to Clause 2 includes a reference circuit configured to control a current source transistor to set a first current for each of a plurality of transistor slices.

[0121] Clause 4. The apparatus according to Clause 1, wherein:

[0122] Each of the plurality of transistor slices comprises a switching transistor including a switching metal-oxide-semiconductor field-effect transistor (MOSFET); and / or

[0123] Each of the multiple transistor slices contains a current source transistor, which includes a current source MOSFET.

[0124] Clause 5. The apparatus according to Clause 4, wherein:

[0125] Each of the plurality of transistor slices includes a switching MOSFET comprising: a first switching terminal coupled to an input terminal; and a second switching terminal; and

[0126] Each of the plurality of transistor slices comprises a current source MOSFET including: a first current source terminal coupled to a second switching terminal; a second current source terminal coupled to an output terminal; and a current source gate terminal.

[0127] Clause 6. The apparatus according to Clause 5, wherein the switching MOSFET of each of the plurality of transistor slices is configured to operate in its transistor region, and / or the current source MOSFET of each of the plurality of transistor slices is configured to operate in its transistor region.

[0128] Clause 7. The apparatus according to Clause 5, wherein:

[0129] The current source gate terminals of the first current source MOSFET are coupled together, and the second current source terminals of each of the current source MOSFETs are coupled together.

[0130] Clause 8. The apparatus according to Clause 7 further includes:

[0131] A reference circuit configured to control a current source transistor to set a first current for each of a plurality of transistor slices;

[0132] In this context, the first current of each of the multiple transistor slices is approximately equal to the first current of the other transistor slices.

[0133] Clause 9. The apparatus according to Clause 8, wherein:

[0134] The reference circuit includes a reference slice, which includes: a switching reference transistor including a switching reference MOSFET; and a current source reference transistor including a current source reference MOSFET.

[0135] in:

[0136] The switching reference MOSFET includes: a first switching reference terminal coupled to the input terminal; and a second switching reference terminal; and

[0137] The current source reference MOSFET includes: a first current source reference terminal coupled to a second switch reference terminal; a second current source reference terminal coupled to an output terminal; and a current source reference gate terminal;

[0138] In each current-source MOSFET, the current-source gate terminal is coupled to the current-source reference gate terminal; and

[0139] The second current source terminal of each current source MOSFET is coupled to the second current source reference terminal.

[0140] Clause 10. The apparatus of Clause 9, wherein the reference circuit includes a reference current controller configured to control a reference slice to set a second current flowing in the reference slice, such that the reference slice controls current source transistors to set a first current for each of a plurality of transistor slices, the first current of each of the plurality of transistor slices depending on the second current.

[0141] Clause 11. The apparatus according to Clause 10, wherein the reference current controller is configured to receive a reference current, the second current depending on the reference current.

[0142] Clause 12. The apparatus according to Clause 11, wherein the reference current controller comprises:

[0143] The reference MOSFET includes:

[0144] First reference MOSFET terminal;

[0145] A second reference MOSFET terminal coupled to the output terminal; and a reference MOSFET gate terminal coupled to the current source reference gate terminal;

[0146] Reference resistor element;

[0147] A first amplifier, the first amplifier comprising:

[0148] A first amplifier has a first input terminal coupled to a first reference MOSFET terminal.

[0149] The second input terminal of the first amplifier is coupled to the output terminal via a reference resistor element;

[0150] A first amplifier output node, which is coupled to a reference MOSFET gate terminal;

[0151] A second amplifier, comprising:

[0152] The first input terminal of the second amplifier is coupled to the first current source reference terminal.

[0153] The second input terminal of the second amplifier is coupled to the first input terminal of the first amplifier; and

[0154] The second amplifier output terminal is coupled to the switch reference gate terminal of the switch reference MOSFET.

[0155] Clause 13. The apparatus of Clause 12, wherein each of the plurality of transistor slices includes a buffer circuit configured to provide a gate drive voltage to drive switching of a switching MOSFET, the gate drive voltage being approximately equal to the output voltage provided by a second amplifier to the switch reference gate terminal.

[0156] Clause 14. The apparatus according to Clause 12, wherein a reference current is received at a first input terminal and a second input terminal of the first amplifier.

[0157] Clause 15. The apparatus according to Clause 7, wherein the device includes an electrostatic discharge (ESD) protection circuit.

[0158] Clause 16. The apparatus according to Clause 15, wherein:

[0159] Each of the multiple transistor slices includes an ESD protection module with ESD protection circuitry.

[0160] Each of the ESD protection modules is coupled to both the input and output terminals;

[0161] During a positive ESD event at the output node, each of the ESD protection modules is configured as follows:

[0162] A first discharge path is provided to a first power supply voltage; and a second discharge path is provided to a second power supply voltage; and / or

[0163] During negative ESD events at the output node, each of the ESD protection modules is configured as follows:

[0164] A third discharge path is provided to the first power supply voltage; and a fourth discharge path is provided to the second power supply voltage.

[0165] Clause 17. The apparatus according to Clause 16, wherein each of the ESD protection modules comprises:

[0166] Active clamping circuitry and / or gate-coupled n-type metal-oxide-semiconductor (GCNMOS);

[0167] Back-to-back diode circuit; and

[0168] The body diode of a switching transistor.

[0169] Clause 18. The apparatus according to Clause 17, wherein:

[0170] The first discharge path is provided through the following:

[0171] Active clamping circuits and / or gate-coupled n-type metal-oxide-semiconductor (GCNMOS), and back-to-back diode circuits;

[0172] The second discharge path is provided through the following:

[0173] The body diode of a switching transistor;

[0174] The third discharge path is provided through the following:

[0175] Active clamping circuitry and / or gate-coupled n-type metal-oxide-semiconductor (GCNMOS), and back-to-back diode circuitry; and

[0176] The fourth discharge path is provided through the following:

[0177] Active clamping circuitry and / or gate-coupled n-type metal-oxide-semiconductor (GCNMOS), and back-to-back diode circuitry.

[0178] Clause 19. The apparatus according to Clause 15, wherein:

[0179] Each of the multiple transistor slices includes an ESD protection module with ESD protection circuitry; and

[0180] Each of the ESD protection modules is coupled to a second current source terminal and configured to discharge the current source gate terminal and / or the first current source terminal.

[0181] Clause 20. The apparatus according to Clause 1 further includes a low-dropout regulator (LDO) for receiving an input voltage and for providing an output voltage to an electrical load, the LDO including a pass device.

[0182] Clause 21. The apparatus according to Clause 20, wherein the low differential pressure regulator comprises:

[0183] An LDO amplifier, which is configured to:

[0184] Receive reference voltage and output voltage;

[0185] Generate control signals that depend on the reference voltage and the output voltage; and

[0186] A control logic circuit configured to drive switching operations of the device that depend on a control signal.

[0187] Clause 22. A method of providing a device, the method comprising providing a plurality of transistor slices coupled in parallel;

[0188] Each of the multiple transistor slices includes:

[0189] A switching transistor, configured to switch between an on state and an off state; and

[0190] A current source transistor, which is coupled in series with a switching transistor, is configured to set a first current flowing in the transistor slice when the switching transistor is in the on state.

Claims

1. An apparatus comprising: The device comprises a plurality of transistor slices coupled in parallel; Each of the plurality of transistor slices includes: A switching transistor, the switching transistor being configured to switch between an on state and an off state; and A current source transistor, which is coupled in series with the switching transistor and configured to set a first current to flow in the transistor slice when the switching transistor is in the on state.

2. The apparatus according to claim 1, wherein: The switching transistor in each of the plurality of transistor slices includes a switching metal-oxide-semiconductor field-effect transistor (MOSFET); and / or The current source transistor of each of the plurality of transistor slices includes a current source MOSFET.

3. The apparatus according to claim 2, wherein: Each of the plurality of transistor slices includes a switching MOSFET comprising: A first switching terminal, the first switching terminal being coupled to an input terminal; and Second switch terminal; and The current source MOSFET for each of the plurality of transistor slices includes: A first current source terminal is coupled to a second switch terminal; The second current source terminal is coupled to the output terminal; and Current source gate terminal.

4. The apparatus according to claim 3, wherein: The current source gate terminals of each of the current source MOSFETs are coupled together; and The second current source terminals of each of the current source MOSFETs are coupled together.

5. The apparatus according to claim 4, further comprising: A reference circuit configured to control the current source transistor to set a first current for each of the plurality of transistor slices; In this context, the first current of each of the plurality of transistor slices is approximately equal to the first current of the other transistor slices.

6. The apparatus according to claim 5, wherein: The reference circuit includes a reference slice, which includes: A switching reference transistor, comprising a switching reference MOSFET; and A current source reference transistor, wherein the current source reference transistor includes a current source reference MOSFET; in: The switching reference MOSFET includes: A first switch reference terminal, the first switch reference terminal being coupled to the input terminal; and Second switch reference terminal; and The current source reference MOSFET includes: A first current source reference terminal is coupled to a second switch reference terminal; A second current source reference terminal, which is coupled to the output terminal; and Current source reference gate terminal; The current source gate terminal of each of the current source MOSFETs is coupled to the current source reference gate terminal; and The second current source terminal of each of the current source MOSFETs is coupled to the second current source reference terminal.

7. The apparatus according to claim 6, wherein: The reference circuit includes a reference current controller configured to control the reference slice to set a second current flowing in the reference slice, such that the reference slice controls the current source transistor to set a first current for each of the plurality of transistor slices, the first current of each of the plurality of transistor slices depending on the second current. and The reference current controller is configured to receive a reference current, the second current being dependent on the reference current.

8. The apparatus of claim 7, wherein, The reference current controller includes: Reference MOSFET, the reference MOSFET comprising: First reference MOSFET terminal; A second reference MOSFET terminal, the second reference MOSFET terminal being coupled to the output terminal; and The reference MOSFET gate terminal is coupled to the current source reference gate terminal; Reference resistor element; A first amplifier, the first amplifier comprising: The first input terminal of the first amplifier is coupled to the first reference MOSFET terminal. The second input terminal of the first amplifier is coupled to the output terminal via the reference resistor element; A first amplifier output node, the first amplifier output node being coupled to the gate terminal of the reference MOSFET; a second amplifier, the second amplifier comprising: The first input terminal of the second amplifier is coupled to the first current source reference terminal. The second input terminal of the second amplifier is coupled to the first input terminal of the first amplifier; and The second amplifier output terminal is coupled to the switch reference gate terminal of the switch reference MOSFET.

9. The apparatus of claim 4, wherein, The device includes an electrostatic discharge (ESD) protection circuit.

10. The apparatus according to claim 9, wherein: Each of the plurality of transistor slices includes an ESD protection module of the ESD protection circuit. Each of the ESD protection modules is coupled to the input terminal and the output terminal; During a positive ESD event at the output node, each of the ESD protection modules is configured as follows: A first discharge path is provided to the first power supply voltage; and A second discharge path is provided to the second power supply voltage; and / or During negative ESD at the output node, each of the ESD protection modules is configured as follows: Provides a third discharge path to the first power supply voltage; and A fourth discharge path is provided to the second power supply voltage.

11. The apparatus according to claim 9, wherein: Each of the plurality of transistor slices includes an ESD protection module of the ESD protection circuit. as well as Each of the ESD protection modules is coupled to the second current source terminal and configured to discharge the current source gate terminal and / or the first current source terminal.

12. The apparatus according to any one of claims 1 to 11, further comprising a low-dropout regulator (LDO) for receiving an input voltage and for providing an output voltage to an electrical load, the LDO including the passing device.

13. A method of providing a device, the method comprising providing a plurality of transistor slices coupled in parallel; wherein Each of the plurality of transistor slices includes: A switching transistor, configured to switch between an on state and an off state; and A current source transistor, which is coupled in series with the switching transistor and configured to set a first current to flow in the transistor slice when the switching transistor is in the on state.

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