Shift register

Abstract

To improve characteristics of a CMOS circuit.SOLUTION: While a first P-type thin-film transistor is ON, an N-type thin-film transistor and a second P-type thin-film transistor are OFF, and a signal of first output signal supply wiring is supplied to an output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and a signal of second output signal supply wiring is supplied to the output line.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a circuit and a shift register that output an output signal.

Background Art

[0002] As display devices, liquid crystal display devices (LCDs) and OLED (Organic Light-Emitting Diode) display devices are widely used. These display devices include a shift register for driving (selecting) scanning lines. In addition, an OLED display device is known that measures the characteristics of elements (driving transistors and OLEDs) of a display device and corrects a data signal based on the measurement result. Such an OLED display device that performs external compensation of a data signal includes a shift register that outputs a control signal for measurement.

[0003] Devices using LTPO technology in which a low-temperature poly-silicon (LTPS) thin film transistor (TFT) and an oxide semiconductor TFT, for example, an IGZO TFT, are integrated on the same substrate have been applied to display panels, and furthermore, the scope of its application is expanding.

[0004] These products can be designed according to device characteristics such that, for example, IGZO is applied to a location where leakage current is a problem and LTPS is applied to a location where driving ability is required. In addition, the possibility of realizing a CMOS (Complementary metal-oxide-semiconductor) device by combining a PMOS type LTPS TFT and an NMOS type IGZO TFT has also been studied.

[0005] Between the time data is input to the shift register and the time it is output, the node to which the gate of the output transistor is connected is changed to a high (or low) potential. To always electrically connect to either a high-potential or low-potential power supply, a CMOS circuit using both N-channel and P-channel transistors is used to connect to the power supply complementaryly. Compared to a single-conductivity TFT circuit, the CMOS circuit can be made smaller and is more reliable. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent Application No. 2010 / 0176395 [Patent Document 2] U.S. Patent Application No. 2003 / 0173995 [Patent Document 3] U.S. Patent Application No. 2019 / 0204968 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, CMOS circuits combining LTPSTFTs and oxide semiconductor TFTs have several challenges stemming from the characteristics of these TFTs. One is that the large difference in mobility between LTPS and oxide semiconductors increases the area occupied by the oxide semiconductor TFTs in the CMOS circuit. For example, the mobility of IGZO is nearly an order of magnitude lower than that of LTPS. Another challenge is that, as a trade-off for the low leakage characteristics of oxide semiconductor TFTs, residual charge on the output lines is difficult to dissipate. This can lead to malfunctions and reduced reliability. [Means for solving the problem]

[0008] One aspect of the present disclosure is a circuit that outputs an output signal from an output line, comprising: a first output signal supply wiring; a second output signal supply wiring; an output line; a first P-type thin-film transistor that switches ON / OFF between the first output signal supply wiring and the output line; an N-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line; and a second P-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line. While the first P-type thin-film transistor is ON, the N-type thin-film transistor and the second P-type thin-film transistor are OFF, and the signal from the first output signal supply wiring is supplied to the output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and the signal from the second output signal supply wiring is supplied to the output line. [Effects of the Invention]

[0009] According to one aspect of this disclosure, the characteristics of a CMOS circuit can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic example of the configuration of an OLED display device is shown. [Figure 2A] This shows an example of the pixel circuit configuration for an OLED display device. [Figure 2B] This shows an example of the pixel circuit configuration for a liquid crystal display device. [Figure 2C] This shows an example of the pixel circuit configuration for a liquid crystal display device. [Figure 3A] The configuration of a CMOS circuit according to one embodiment of this specification is shown. [Figure 3B] A schematic example of the device layout of the CMOS circuit shown in Figure 3A is illustrated. [Figure 3C] A schematic example of the device layout of the CMOS circuit shown in Figure 3A is illustrated. [Figure 4] This diagram schematically shows the circuit configuration for each shift register that can be included in the shift register of a scan driver. [Figure 5]Shows the timing chart of the circuit shown in FIG. 4. [Figure 6] Shows a part of the shift register that can be implemented in the scan driver. [Figure 7] Shows the timing chart of the signals of the shift register shown in FIG. 6. [Figure 8] Shows a circuit configuration example of a shift register unit that can be implemented in the scan driver. [Figure 9] Shows the timing chart of the circuit shown in FIG. 8. [Figure 10] Shows the timing chart of the signals of the shift register of the scan driver. [Figure 11] Shows another configuration example of the shift register unit. [Figure 12] Shows the timing chart of the circuit shown in FIG. 11. [Figure 13] Shows a partial configuration of a shift register including the shift register unit described with reference to FIGS. 11 and 12. [Figure 14] Shows another configuration example of the shift register unit. [Figure 15] Shows the timing chart of the circuit shown in FIG. 14. [Figure 16] Shows a partial configuration of a shift register including the shift register unit described with reference to FIGS. 14 and 15.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure.

[0012] <Overview> Hereinafter, a circuit configuration applicable to a shift register of a liquid crystal display device (LCD), an OLED (Organic Light-Emitting Diode) display device, etc. will be described. The circuits disclosed below can be applied to devices different from display devices.

[0013] A circuit according to one embodiment of this specification utilizes LTPO technology, which integrates low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with oxide semiconductor TFTs, such as IGZOTFTs. The circuit includes a CMOS (Complementary metal-oxide-semiconductor) circuit configured by combining a PMOS type (also simply called P-type) LTPSTFT and an NMOS type (also simply called N-type) IGZOTFT.

[0014] CMOS circuits can be made smaller in size compared to circuits composed of single-conductivity TFTs. Single-conductivity TFT circuits generate high-voltage output signals, requiring bootstrapping to lower the gate potential of the pull-down TFT. To perform bootstrapping, a capacitance must be provided between the gate and source of the pull-down TFT.

[0015] Furthermore, isolation TFTs are implemented to prevent high voltage from being applied between the drain and source of a specific control TFT due to the high voltage during bootstrapping. These measures increase the size of the single-conductor circuit. Additionally, the reliability may decrease due to the electrical stress applied to the TFTs.

[0016] CMOS circuits do not require bootstrapping in single-type circuits, and the circuit size can be reduced by omitting the circuit elements necessary for bootstrapping. However, conventional CMOS circuits that combine LTPS TFTs and oxide semiconductor TFTs have several challenges. One is the large area occupied by oxide semiconductor TFTs in the CMOS circuit. This is due to the large difference in mobility between LTPS and oxide semiconductors. For example, the mobility of IGZO is about 1 / 10th that of LTPS.

[0017] Another issue is that residual charge on the output lines of conventional CMOS circuits is difficult to dissipate, which can lead to malfunctions and reduced reliability. This is due to the low leakage characteristics of oxide semiconductor TFTs. For example, in automotive display devices, a fail-safe function is required that switches to a black display to prevent abnormal displays when the input signal supplied to the CMOS circuit becomes unstable due to unexpected fluctuations in the power supply voltage during operation. Because oxide semiconductor TFTs have low off-leakage, display malfunctions due to residual charge can occur.

[0018] A CMOS circuit according to one embodiment of this specification includes a pull-up P-type TFT for supplying a high potential to the output line, a pull-down N-type TFT for supplying a low potential to the output line, and a pull-down P-type TFT. The P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT, such as an IGZOTFT. This configuration is particularly effective in a CMOS circuit where the mobility of the P-type TFT is higher than that of the N-type TFT, and the leakage current of the N-type TFT is smaller than that of the P-type TFT. The semiconductor of the P-type TFT may be a material other than polysilicon, and the semiconductor of the N-type TFT may be a material other than an oxide semiconductor.

[0019] As described above, the operation of pulling up the output line potential to a predetermined high potential level (VH) is handled by the pull-up P-type TFT. The pull-down P-type TFT can pull down the output line potential from a predetermined low potential (VL) to a potential that is a predetermined voltage higher, specifically a potential that is effectively only the threshold voltage of the pull-down P-type TFT higher (VL+Vth). The pull-down N-type TFT continuously pulls down the output line potential from the potential (VL+Vth) to a predetermined potential level VL.

[0020] Since the pull-down P-type TFT reduces the output line potential to (VL ​​+ Vth), the operation of the pull-down N-type TFT does not require a large driving capability to pull down the output line potential. Therefore, the increase in circuit area can be suppressed compared to a CMOS configuration.

[0021] The embodiments will be described in detail below with reference to the drawings. Common components in each drawing are denoted by the same reference numerals. For the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0022] <Embodiment 1> [Overall structure] Figure 1 schematically shows an example configuration of the OLED display device 10. In the following description, the OLED display device will be described as an example of a device to which the shift register of this disclosure is applied, but it can be applied to other display devices or devices different from display devices. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements are formed, and a sealing structure 200 that encapsulates the OLED elements.

[0023] Scanning drivers 131, 132, driver IC 134, and demultiplexer 136 are arranged around the cathode electrode formation region 114 outside the display area 125 of the TFT substrate 100. The first scanning driver 131 drives, for example, the scan lines of the TFT substrate 100. The second scanning driver 132 drives, for example, the measurement control lines to measure the characteristics of elements such as organic light-emitting devices and TFTs.

[0024] The driver IC 134 is connected to external equipment via an FPC (Flexible Printed Circuit) 135. The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF).

[0025] The driver IC 134 supplies power and timing signals (control signals) to the scanning drivers 131 and 132. Furthermore, the driver IC 134 supplies power and data signals to the demultiplexer 136. The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (where d is an integer greater than or equal to 2). The demultiplexer 136 drives d times the number of output pins of the driver IC 134 by switching the data line to which the data signal from the driver IC 134 is output d times during the scanning period.

[0026] [Pixel circuit configuration] Multiple pixel circuits are formed on the TFT substrate 100 to control the current supplied to the anode electrodes of multiple subpixels. Figure 2A shows an example of the configuration of a pixel circuit. Each pixel circuit includes a driving transistor 21, a selection transistor 22, a measurement transistor 24, and a holding capacitor C. The pixel circuit controls the light emission of the OLED element E1. The transistors are field-effect transistors, and more specifically, TFTs.

[0027] The selection transistor 22 is a switch that selects sub-pixels. In the configuration example shown in Figure 2A, the selection transistor 22 is an N-type TFT, and its gate terminal is connected to the scan line 106. One source / drain terminal is connected to the data line 105. The other source / drain terminal is connected to the gate terminal of the drive transistor 21.

[0028] The drive transistor 21 is a drive transistor (driver TFT) for driving the OLED element E1. The drive transistor 21 is a P-type TFT, and its gate terminal is connected to the source / drain terminals of the selection transistor 22. The source terminal of the drive transistor 21 is connected to the power line 108 (Vdd). The drain terminal is connected to the anode of the OLED element E1. A retaining capacitance C is formed between the gate terminal and the source terminal of the drive transistor 21.

[0029] The measurement transistor 24 is a P-type TFT and controls the electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is performed by supplying a control signal from the measurement control line 109 to the gate of the measurement transistor 24. The measurement transistor 24 is used to measure the characteristics of the drive transistor 21 and the OLED element E1.

[0030] Next, the operation of the pixel circuit will be explained. The scanning driver 131 outputs a selection pulse to the scanning line 106, turning on the selection transistor 22. The data voltage supplied from the driver IC 134 via the data line 105 is stored in the retention capacitor C. The retention capacitor C holds the stored voltage throughout one frame period. The retention voltage causes the conductance of the drive transistor 21 to change analogously, and the drive transistor 21 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0031] The measurement transistor 24 can be used to measure the characteristics of the drive transistor 21. For example, by selecting bias conditions so that the drive transistor 21 operates in the saturation region and the measurement transistor 24 operates in the linear region, and measuring the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref), the voltage-current conversion characteristics of the drive transistor 21 can be accurately measured. By generating a data signal in an external circuit that compensates for the differences in the voltage-current conversion characteristics of the drive transistor 21 between sub-pixels, a highly uniform display image can be achieved.

[0032] Alternatively, by turning off the drive transistor 21 and operating the measurement transistor 24 in the linear region, and applying a voltage that causes the OLED element E1 to emit light from the reference voltage supply line 110, the voltage-current characteristics of the OLED element E1 can be accurately measured. For example, even if the OLED element E1 deteriorates due to prolonged use, its lifespan can be extended by generating a data signal in an external circuit that compensates for the amount of deterioration.

[0033] The pixel circuit of the OLED display device 10 shown in Figure 2A is an example, and the pixel circuit may have other circuit configurations. The number of TFTs and capacitive elements constituting the pixel circuit, as well as the conductivity type of each TFT, are determined according to the design of the TFT substrate.

[0034] Next, an example of a pixel circuit for a liquid crystal display device will be described. Figures 2B and 2C show examples of pixel circuits for liquid crystal display devices, respectively. The pixel circuit example in Figure 2B includes an N-type switch thin-film transistor 202, a retaining capacitor Cst, and liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is applied to the common electrode. A scanning driver outputs a selection pulse to the scanning line 206, turning on the N-type switch thin-film transistor 202. The data line 205 supplies a data signal to the pixel electrode and retaining capacitor Cst via the ON-state N-type switch thin-film transistor 202.

[0035] The pixel circuit example in Figure 2C includes a P-type switch thin-film transistor 212, a retaining capacitor Cst, and a liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is applied to the common electrode. A scanning driver outputs a selection pulse to the scanning line 206, turning on the P-type switch thin-film transistor 212. The data line 205 supplies the data signal to the pixel electrode and retaining capacitor Cst via the ON-state P-type switch thin-film transistor 212.

[0036] Scanning drivers 131 and 132 each include a shift register for sequentially selecting the scan line 106 and the measurement control line 109. The shift registers described below can be applied to either or both of the scanning drivers 131 and 132.

[0037] [CMOS circuit configuration] Figure 3A shows the configuration of a CMOS circuit according to one embodiment of this specification. The CMOS circuit can be included, for example, in both or one of the scanning drivers 131 and 132. The CMOS circuit includes a first P-type TFT 311, a second P-type TFT 312, and an N-type TFT 315. The first P-type TFT 311 is a pull-up TFT, and the second P-type TFT 312 and the N-type TFT 315 are pull-down TFTs. In the configuration example of Figure 3A, the P-type TFTs 311 and 312 are LTPSTFTs, and the N-type TFT 315 is an oxide semiconductor TFT, for example, an IGZOTFT.

[0038] The pull-up P-type TFT 311 is located between the high-potential line 331, which supplies a high potential VH, and the output line 321, which outputs the output signal OUT. The two source / drain pins of the pull-up P-type TFT 131 are connected to the high-potential line 331 and the output line 321, respectively. The high-potential line 331 is included in the first output signal supply wiring.

[0039] The pull-down P-type TFT312 is located between the low-potential line 333, which provides a low-potential VL lower than the high-potential VH, and the output line 321. The two source / drain terminals of the pull-down P-type TFT312 are connected to the low-potential line 333 and the output line 321, respectively. The low-potential line 333 is included in the second output signal supply wiring.

[0040] The pull-down N-type TFT 315 is located between the low-potential line 331, which provides a low potential VL, and the output line 321. The two source / drain pins of the pull-down N-type TFT 315 are connected to the low-potential line 332 and the output line 321, respectively. The low-potential line 332, like the low-potential line 333, provides a low potential VL and is included in the second output signal supply wiring. The low-potential line 332 may be connected to the low-potential line 333. The potential of the intermediate node between the source / drain pins of the pull-up P-type TFT 311 and the source / drain pins of the pull-down TFTs 312 and 315 is the potential of the signal OUT on the output line 321.

[0041] The gates of the pull-up P-type TFT311 and the pull-down N-type TFT315 are input to the same control signal (first gate signal) IN1. The gate of the pull-down P-type TFT312 is input to a control signal (second gate signal) IN2 that is different from control signal IN1. As described later, while the pull-up P-type TFT311 is ON, the pull-down TFTs 312 and 315 are OFF. Conversely, while the pull-down TFTs 312 and 315 are ON, the pull-up P-type TFT311 is OFF.

[0042] In the example in Figure 3A, control signals IN1 and IN2 exhibit opposite time changes. In the example in Figure 3A, the same control signal IN1 is input. In other configuration examples, different control signals exhibiting the same change, transmitted via separate wiring, may be input to the gates of the pull-up P-type TFT311 and the pull-down N-type TFT315.

[0043] The pull-up P-type TFT 311 is responsible for pulling up output line 321 to a high potential VH. When the pull-up P-type TFT 311 is ON, it supplies the high potential VH of high potential line 331 to output line 321.

[0044] The drive capability of the pull-down type P-type TFT312 is higher than that of the pull-down type N-type TFT315. The pull-down type P-type TFT312 pulls down the potential of the output line to a potential that is a predetermined voltage higher than the low potential VL. The predetermined voltage substantially coincides with the threshold voltage Vth of the pull-down type P-type TFT312. In other words, the pull-down type P-type TFT312 pulls down the potential of the output line 321 to a potential (VL + Vth). Continuously, the pull-down type N-type TFT315 pulls down the potential of the output line 321 to the low potential VL.

[0045] Oxide semiconductor TFTs have a smaller off-leak current compared to LTPSTFTs. In the configuration shown in Figure 3A, a pull-down P-type TFT 312 is located between the output line 321 and the low-potential line 333. In other words, a leak path exists between the output line 321 and the low-potential line 333 through the LTPSTFT 312. Therefore, when in OFF operation, it is possible to suppress malfunctions and reliability degradation caused by residual charge 341 on the output line 321.

[0046] Since the pull-down N-type TFT315 does not require a large driving force, its size can be reduced. For example, the channel width of the pull-down N-type TFT315 may be less than or equal to the channel width of the pull-up P-type TFT311. The channel widths of the two P-type TFTs 311 and 312 may be the same, for example, and they may have the same structure. In another example, the channel width of the pull-up P-type TFT311 may be larger than the channel width of the pull-down P-type TFT312.

[0047] Figures 3B and 3C schematically show an example of the device layout of the CMOS circuit shown in Figure 3A. In the device layouts shown in Figures 3B and 3C, the size (channel width) of the pull-down N-type TFT315, which is an oxide semiconductor TFT, is smaller than in a conventional configuration that does not include a pull-down P-type TFT312.

[0048] In Figure 3B, the pull-up P-type TFT 311 and the pull-down P-type TFT 312 have a top-gate structure, while the pull-down N-type TFT 315 has a bottom-gate structure. The channels of the P-type TFTs 311 and 312 are formed in the LTPS films 351 and 352, respectively. The channel of the N-type TFT 315 is formed in the oxide semiconductor film 353. In the configuration example in Figure 3B, the channel width of the pull-up P-type TFT 311 is greater than the channel width of the pull-down P-type TFT 312.

[0049] In Figure 3C, the channels of P-type TFTs 311 and 312 are formed in LTPS films 361 and 362, respectively. The channel of N-type TFT 315 is formed in oxide semiconductor film 363. In the configuration example in Figure 3C, the channel width of the pull-up P-type TFT 311 may be the same as the channel width of the pull-down P-type TFT 312.

[0050] <Embodiment 2> The following describes a configuration for outputting the gate signal of a P-type TFT within a pixel circuit. Figure 4 schematically shows the circuit configuration of a single-stage shift register (also called a flip-flop or shift register unit). The shift register unit shown in Figure 4 includes the CMOS circuit shown in Figure 3A. The shift register unit shown in Figure 4 can be included, for example, in the scan driver 132 of an OLED display device or in the shift register of a scan driver for a liquid crystal pixel circuit shown in Figure 2C.

[0051] The shift register unit outputs the gate signal of, for example, the P-type TFT 24 shown in Figure 2A or the P-type TFT 212 shown in Figure 2C. The shift register unit applies a low-potential output signal pulse to the gate of the P-type TFT 24 or 212. In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFT in the shift register unit operates in ON / OFF mode.

[0052] The inputs to each shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN from the previous shift register unit, and the clock signals CLK_DRV and CLK_RST, which periodically change in time between the high and low potentials. The input signal IN and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from output line 321 is the signal to the next stage shift register unit.

[0053] The shift register unit includes a pull-up P-type TFT 311, a pull-down P-type TFT 312, and a pull-down N-type TFT 315, as described with reference to Figure 3A. The gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 are connected via node N2. These gates are given the same potential. The shift register unit further includes P-type TFTs 411 through 415.

[0054] One of the P-type TFTs 412 and 415 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. P-type TFT 414 is an example of a third control switch TFT, and P-type TFT 413 is an example of a fourth control switch TFT.

[0055] A constant high power supply potential VGH is applied to one of the source / drain terminals of the pull-up P-type TFT311. The clock signal CLK_DRV is applied to one of the source / drain terminals of each of the pull-down TFTs 312 and 315. As will be described later, when the pull-down TFTs 312 and 315 are ON, the clock signal CLK_DRV is at a low potential level lower than the high power supply potential VGH. This potential is the same as the low power supply potential VGL.

[0056] The gate of the P-type TFT411 is connected to output line 321, and they are at the same potential. One source / drain of the P-type TFT411 is connected to the gate of the pull-up P-type TFT311, and they are at the same potential. The other source / drain of the P-type TFT411 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant. The P-type TFT411 prevents node N2 from becoming floating and causing circuit instability. The P-type TFT411 may be omitted.

[0057] The gate of the P-type TFT412 is supplied with the signal IN. One source / drain of the P-type TFT412 is connected to the gate of a pull-up P-type TFT311, and they are at the same potential. The other source / drain of the P-type TFT412 is supplied with a high power supply potential VGH.

[0058] The source of the P-type TFT413 is connected to the gate of the pull-up P-type TFT311, and they are at the same potential. The gate of the P-type TFT413 is connected to the drain, creating a diode connection. The drain is supplied with the clock signal CLK_RST.

[0059] The gate of the P-type TFT414 is connected to the gate of the pull-up P-type TFT311, and their gate potentials are identical. One source / drain of the P-type TFT414 is connected to the gate of the pull-down P-type TFT312 via node N1, and they are at the same potential. The other source / drain of the P-type TFT414 is supplied with a high power supply potential VGH.

[0060] The gate of the P-type TFT415 is supplied with the signal IN. One source / drain of the P-type TFT415 is connected to the gate of a pull-down P-type TFT312 via node N1, and they are at the same potential. The other source / drain of the P-type TFT415 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0061] The operation of the circuit shown in Figure 4 will be explained below. Figure 5 shows the timing chart of the circuit shown in Figure 4. In the following, a high potential level of a signal is represented as H, and a low potential level as L. All high potential levels of signals are at the high power supply potential VGH, and low potential levels are at the low power supply potential VGL. In Figure 5, all signals are synchronized.

[0062] First, let's describe the state immediately before time T1. The input signal IN is H, the clock signal CLK_DRV is H, and the clock signal CLK_RST is L. The potential at node N1 is H, and the potential at node N2 is L. P-type TFTs 415 and 412 are OFF. The diode-connected P-type TFT 413 is in a forward bias state. The pull-down P-type TFT 312 is OFF. The pull-down N-type TFT 315 is OFF, and the pull-up P-type TFTs 311 and 414 are ON. P-type TFT 411 is OFF. The output signal OUT is H.

[0063] Next, we will explain the operation of the components at time T1. The input signal IN changes from H to L. Between time T1 and time T2, a transfer pulse (low potential level L for input signal IN) is input from the preceding shift register unit. Also, the clock signal CLK_RST changes from L to H.

[0064] In response to the above change in the input signal IN, P-type TFTs 415 and 412 turn ON. In response to the above change in the clock signal CLK_RST, P-type TFT 413 enters a reverse bias state. The potential of node N1 changes from H to L, and the potential of node N2 changes from L to H.

[0065] As the potential of node N1 changes from H to L, the pull-down P-type TFT312 turns ON. As the potential of node N2 changes from L to H, the pull-down N-type TFT315 turns ON. The clock signal CLK_DRV remains H, and the output signal OUT remains H. The output signal OUT remains H, and the P-type TFT411 remains OFF.

[0066] Next, we will describe the operation of the components at time T2. The input signal IN changes from L to H. P-type TFTs 415 and 412 turn OFF. The clock signal CLK_RST remains H. The potential of node N1 is L and it is in a floating state.

[0067] The clock signal CLK_DRV changes from high to low. As a result, the output signal OUT changes from high to low. Furthermore, the P-type TFT411 turns ON. The potential of node N2 remains high. During the period from time T2 to T3, the shift register unit outputs the pulse to be transferred to the control line of the display area 125 and to the next stage shift register unit.

[0068] Next, we will describe the operation of the components at time T3. The input signal IN remains high, and P-type TFTs 415 and 412 remain OFF. The clock signal CLK_DRV changes from low to high. Also, the clock signal CLK_RST changes from high to low. P-type TFT 413 enters a forward-biased state.

[0069] A clock signal CLK_RST is applied to node N2, and the potential of node N2 changes from H to L. The P-type TFT414 turns ON, and the potential of node N1 changes from L to H.

[0070] When the potential of node N2 changes from H to L, the pull-down N-type TFT315 turns OFF and the pull-up P-type TFT311 turns ON. When the potential of node N1 changes from L to H, the pull-down P-type TFT312 turns OFF. The output signal OUT changes from L to H. The P-type TFT411 turns OFF. The period from time T2 to time T3 is the output period during which the signal pulse is output.

[0071] After time T3, the clock signals CLK_DRV and CLK_RST change periodically. Since the potential of node N2 is L, the change in the clock signal CLK_RST does not change the potential of node N2. The potentials of nodes N1 and N2 are maintained. TFTs 312 and 315 are OFF, so the change in the clock signal CLK_DRV does not change the potential of the output signal OUT. Thus, the output signal OUT is maintained at H. In response to the next change in the input signal IN, the node potentials within the shift register unit change.

[0072] As explained with reference to Figure 5, the shift register operation shown in Figure 4 does not require bootstrapping. Therefore, the circuit area can be reduced because there is no need to add the capacitance required for bootstrapping.

[0073] Figure 6 shows a portion of the shift registers that can be implemented in the scan driver 132. Specifically, Figure 6 shows the first-stage shift register unit SR1, the second-stage shift register unit SR2, and the third-stage shift register unit SR3. Each of the shift register units SR1, SR2, and SR3 can have the circuit configuration described with reference to Figures 4 and 5. Depending on the design, the shift register can be configured as a unit of n connected shift registers (where n is a positive integer).

[0074] Each shift register unit includes multiple signal terminals. Specifically, these are the VGH terminal 611, IN terminal 612, VGL terminal 613, CLK_RST terminal 614, OUT terminal 615, and CLK_DRV terminal 616. In Figure 6, the terminals of the first-stage shift register unit SR1 are indicated by symbols as an example.

[0075] The OUT terminal 615 outputs the output signal OUT shown in Figure 5. A constant high power supply potential VGH is supplied to the VGH terminal 611, as explained with reference to Figure 4. A constant low power supply potential VGL is supplied to the VGL terminal 613, as explained with reference to Figure 4. The signal from the IN terminal 612 is the input signal IN in Figure 5. The signal input to the CLK_RST terminal 614 is the clock signal CLK_RST shown in Figure 5. The signal input to the CLK_DRV terminal 616 is the clock signal CLK_DRV shown in Figure 5. Some input signals to the shift registers are supplied from the driver IC 134.

[0076] The shift register units SR1, SR2, and SR3 each output output signals OUT1, OUT2, and OUT3 from the OUT terminal 615, respectively. These output signals are supplied to the gate of the TFT24 in the pixel circuit, and further supplied to the IN terminal 612 of the next stage shift register unit. The IN terminal 612 of the first stage shift register unit SR1 receives a start signal ST.

[0077] The CLK_RST terminal 614 of the (3k-2) stage is supplied with the clock signal C2, where k is a positive integer. The CLK_DRV terminal 616 of the (3k-2) stage is supplied with the clock signal C1. The CLK_RST terminal 614 of the (3k-1) stage is supplied with the clock signal C3. The CLK_DRV terminal 616 of the (3k-1) stage is supplied with the clock signal C2. The CLK_RST terminal 614 of the 3k stage is supplied with the clock signal C1. The CLK_DRV terminal 616 of the 3k stage is supplied with the clock signal C3.

[0078] Figure 7 shows the timing chart of the shift register signals shown in Figure 6. The start signal ST provides a low-potential pulse with a frame period. Clock signals C1, C2, and C3 each provide a low-potential pulse at a constant period within a frame period. The pulse widths of clock signals C1, C2, and C3 are the same, and are also the same as the pulse width of the start signal ST.

[0079] The pulses of clock signals C1, C2, and C3 have the same period, but their phases are different. Clock signals C1, C2, and C3 are phase-shifted by one pulse width each. In other words, the pulse of clock signal C2 is generated in conjunction with the end of the pulse of clock signal C1. The pulse of clock signal C3 is generated in conjunction with the end of the pulse of clock signal C2. The pulse of clock signal C1 is generated in conjunction with the end of the pulse of clock signal C3. The start and end times of each pulse of the start signal ST coincide with the start and end times of one pulse of clock signal C3.

[0080] Figure 7 shows the time evolution of the output signals OUT1 to OUTn for each of the n-stage shift register units. Output signals OUT1 to OUTn sequentially generate low-potential pulses. The pulse width of output signals OUT1 to OUTn is the same as the pulse width of the other signals. The output signal pulse for each shift register unit is generated in conjunction with the end of the output signal pulse for the preceding shift register unit.

[0081] <Embodiment 3> The following describes a configuration for outputting the gate signal of an N-type TFT within a pixel circuit. Figure 8 schematically shows the circuit configuration of a single-stage shift register (also called a flip-flop or shift register unit). The shift register unit shown in Figure 8 includes the CMOS circuit shown in Figure 3A. The shift register unit shown in Figure 8 can be included, for example, in the shift register of the scanning driver 131 of an OLED display device or the scanning driver for the liquid crystal pixel circuit shown in Figure 2B.

[0082] As explained with reference to Figure 2A, the scanning driver 131 outputs the gate signal for the N-type TFT 22 in the pixel circuit. The pixel circuit shown in Figure 2B also includes an N-type TFT 202 as a controlled switch transistor. The shift register unit applies a high-potential level output signal pulse to the gate of the N-type TFT 22 or 202.

[0083] In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFTs in the shift register operate in ON / OFF mode.

[0084] The inputs to each shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN from the previous shift register unit, and the clock signals CLK_DRV and CLK_RST. The input signal IN and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from output line 321 is the signal to the next stage shift register unit.

[0085] The shift register unit includes a pull-up P-type TFT 311, a pull-down P-type TFT 312, and a pull-down N-type TFT 315, as described with reference to Figure 3A. The gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 are connected via node N4. These gates are given the same potential. The shift register unit further includes P-type TFTs 513 and 514 and N-type TFTs 511, 512, and 515.

[0086] One of the N-type TFTs 512 and 515 is an example of a first control switch TFT, and the other is an example of a second control switch TFT. The P-type TFT 514 is an example of a third control switch TFT, and the P-type TFT 513 is an example of a fourth control switch TFT.

[0087] A clock signal CLK_DRV is supplied to one of the source / drain terminals of the pull-up P-type TFT311. A constant low power supply potential VGL is supplied to one of the source / drain terminals of each of the pull-down TFTs 312 and 315. As will be described later, when the pull-up P-type TFT311 is ON, the clock signal CLK_DRV is at a high potential level. This potential is the same as the high power supply potential VGH.

[0088] The gate of the N-type TFT511 is connected to output line 321, and they are at the same potential. One source / drain of the N-type TFT511 is connected to the gate of the pull-down P-type TFT312 via node N3, and they are at the same potential. The other source / drain of the N-type TFT511 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant. The N-type TFT511 prevents node N3 from becoming floating and causing circuit instability. The N-type TFT511 may be omitted.

[0089] The gate of the N-type TFT512 is supplied with the signal IN. One source / drain of the N-type TFT512 is connected to the gate of the pull-down P-type TFT312, and they are at the same potential. The other source / drain of the N-type TFT512 is supplied with a high power supply potential VGH.

[0090] The source of the P-type TFT513 is connected to the gate of the pull-down P-type TFT312, and they are at the same potential. The gate of the P-type TFT513 is connected to the drain, creating a diode connection. The drain is supplied with the clock signal CLK_RST.

[0091] The gate of the P-type TFT514 is connected to the gate of the pull-down P-type TFT312, and their gate potentials are identical. One source / drain of the P-type TFT514 is connected via node N4 to the gates of the pull-up P-type TFT311 and the pull-down N-type TFT315, and these are at the same potential. The other source / drain of the P-type TFT514 is supplied with a high power supply potential VGH.

[0092] The gate of the N-type TFT515 is supplied with the signal IN. One source / drain of the N-type TFT515 is connected via node N4 to the gates of the pull-up P-type TFT311 and the pull-down N-type TFT315, and they are at the same potential. The other source / drain of the N-type TFT515 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0093] In the circuit shown in Figure 8, the potential of node N3 is the same as the gate potential of the pull-down P-type TFT312. Also, the potential of node N4 is the same as the gate potentials of the pull-up P-type TFT311 and the pull-down N-type TFT315.

[0094] The operation of the circuit shown in Figure 8 will be explained below. Figure 9 shows the timing chart of the circuit shown in Figure 8. In the following, a high potential level of a signal is represented as H, and a low potential level as L. All high potential levels of signals are at the high power supply potential VGH, and low potential levels are at the low power supply potential VGL. In Figure 9, all signals are synchronized.

[0095] First, let's describe the state immediately before time T1. The input signal IN is L, the clock signal CLK_DRV is H, and the clock signal CLK_RST is L. The potential at node N3 is L, and the potential at node N4 is H. N-type TFTs 515 and 512 are OFF. The diode-connected P-type TFT 513 is in a forward bias state. The pull-down P-type TFT 312 is ON. The pull-down N-type TFT 315 is ON, and the pull-up P-type TFTs 311 and 514 are OFF. The N-type TFT 511 is OFF. The output signal OUT is L.

[0096] Next, we will explain the operation of the components at time T1. The input signal IN changes from L to H. Between time T1 and time T2, a transfer pulse (high potential level H in the input signal IN) is input from the preceding shift register unit. Also, the clock signal CLK_DRV changes from H to L, and the clock signal CLK_RST changes from L to H.

[0097] In response to the above change in the input signal IN, N-type TFTs 515 and 512 turn ON. In response to the above change in the clock signal CLK_RST, P-type TFT 513 enters a reverse bias state. The potential of node N3 changes from L to H, and the potential of node N4 changes from H to L. Because the potential of node N3 changes from L to H, the pull-down P-type TFT 312 turns OFF, and P-type TFT 514 also turns OFF.

[0098] As the potential of node N4 changes from H to L, the pull-down N-type TFT315 turns OFF and the pull-up P-type TFT311 turns ON. Since the clock signal CLK_DRV is L, the output signal OUT remains L. Because the output signal OUT remains L, the N-type TFT511 remains OFF.

[0099] Next, we will describe the operation of the components at time T2. The input signal IN changes from H to L. The clock signal CLK_RST remains H. The clock signal CLK_DRV changes from L to H.

[0100] In response to a change in the input signal IN, the N-type TFTs 515 and 512 turn OFF. The potential at node N3 is maintained at H, and the potential at node N4 is maintained at L. The pull-down TFTs 312 and 315 remain OFF, while the pull-up P-type TFT 311 remains ON.

[0101] The clock signal CLK_DRV changes from L to H. As a result, the output signal OUT changes from L to H. Furthermore, the N-type TFT511 turns ON. The potential of node N3 remains H. During the period from time T2 to T3, the shift register unit outputs the pulse to be transferred to the control line of the display area 125 and to the next stage shift register unit.

[0102] Next, we will explain the operation of the components at time T3. The input signal IN remains low. The clock signal CLK_DRV remains high. The clock signal CLK_RST changes from high to low. Since the input signal IN remains low, the N-type TFTs 515 and 512 remain off.

[0103] In response to the change in the clock signal CLK_RST, the P-type TFT513 enters a forward-biased state. As a result, the clock signal CLK_RST is applied to node N3, and its potential changes from H to L. The P-type TFT514 turns ON, and the potential at node N4 changes from L to H.

[0104] When the potential of node N4 changes from L to H, the pull-down N-type TFT315 turns ON and the pull-up P-type TFT311 turns OFF. When the potential of node N3 changes from H to L, the pull-down P-type TFT312 turns ON. The output signal OUT changes from H to L. The period from time T2 to time T3 is the output period during which the signal pulse is output.

[0105] After time T3, the clock signals CLK_DRV and CLK_RST change periodically. The potential of node N3 is L, and the change in the clock signal CLK_RST does not change the potential of node N3. Since the N-type TFT515 is OFF and the P-type TFT514 is ON, the potential of node N4 is maintained at H. In this way, the potentials of nodes N3 and N4 are maintained.

[0106] The pull-up P-type TFT311 is OFF, so changes in the clock signal CLK_DRV do not change the potential of the output signal OUT. Therefore, the output signal OUT remains L. In response to the next change in the input signal IN, the node potential within the shift register unit changes.

[0107] As explained with reference to Figure 9, the shift register operation shown in Figure 8 does not require bootstrapping. Therefore, the circuit area can be reduced.

[0108] The shift register of the scanning driver 131 can have the same configuration as shown in Figure 6. Each shift register unit has the circuit configuration shown in Figure 8 and operates according to the signals described with reference to Figure 9.

[0109] Figure 10 shows the timing chart of the shift register signals of the scan driver 131. The start signal ST provides a high-potential pulse with a frame period. Clock signals C1, C2, and C3 each provide a low-potential pulse at a constant period within a frame period. The pulse widths of clock signals C1, C2, and C3 are the same, and are also the same as the pulse width of the start signal ST.

[0110] The pulses of clock signals C1, C2, and C3 have the same period, but their phases are different. Clock signals C1, C2, and C3 are phase-shifted by one pulse width each. In other words, the pulse of clock signal C2 is generated in conjunction with the end of the pulse of clock signal C1. The pulse of clock signal C3 is generated in conjunction with the end of the pulse of clock signal C2. The pulse of clock signal C1 is generated in conjunction with the end of the pulse of clock signal C3. The start and end times of each pulse of the start signal ST coincide with the start and end times of one pulse of clock signal C3.

[0111] Figure 10 shows the time evolution of the output signals OUT1 to OUTn for each of the n-stage shift register units. Output signals OUT1 to OUTn sequentially generate high-potential pulses. The pulse width of output signals OUT1 to OUTn is the same as the pulse width of the other signals. The output signal pulse for each shift register unit is generated in conjunction with the end of the output signal pulse for the preceding shift register unit.

[0112] <Embodiment 4> Figure 11 shows another example of a shift register unit configuration. The shift register unit shown in Figure 11 can be included, for example, in the shift register of the scanning driver 132 of an OLED display device or the scanning driver for the liquid crystal pixel circuit shown in Figure 2C.

[0113] The shift register unit outputs the gate signal of, for example, the P-type TFT 24 shown in Figure 2A or the P-type TFT 212 shown in Figure 2C. The shift register unit applies a low-potential output signal pulse to the gate of the P-type TFT 24 or 212. In the circuit described below, the P-type TFT may be an LTPSTFT, and the N-type TFT may be an oxide semiconductor TFT. The TFT in the shift register unit operates in ON / OFF mode.

[0114] The inputs to each shift register unit are the high power supply potential VGH, the low power supply potential VGL, the input signal IN1 from the previous shift register unit, the input signal IN2 from the next shift register unit, and the clock signals CLK_DRV and CLK_RST, which periodically change in time between high and low potentials. The input signals IN1 and IN2 and the clock signals CLK_DRV and CLK_RST switch between a high potential (high level) equal to the high power supply potential VGH and a low potential (low level) equal to the low power supply potential VGL. The output from output line 321 is the signal to the previous and next shift register units.

[0115] The shift register unit includes a pull-up P-type TFT 311, a pull-down P-type TFT 312, and a pull-down N-type TFT 315, as described with reference to Figure 3A. The gates of the pull-up P-type TFT 311 and the pull-down N-type TFT 315 are connected via node N6. These gates are given the same potential. The shift register unit further includes P-type TFTs 552 through 555 and a capacitor 559. P-type TFT 554 is an example of a third control switch TFT.

[0116] A constant high power supply potential VGH is applied to one of the source / drain terminals of the pull-up type P-TFT311. A clock signal CLK_DRV is applied to one of the source / drain terminals of each of the pull-down TFTs 312 and 315. When the pull-down TFTs 312 and 315 are ON, the clock signal CLK_DRV is at a low potential level lower than the high power supply potential VGH. This potential is the same as the low power supply potential VGL.

[0117] The gate of the P-type TFT552 is connected to the gate of the pull-down P-type TFT312, and they are at the same potential. One source / drain of the P-type TFT552 is connected to the gates of the pull-up P-type TFT311 and the pull-down N-type TFT315, and they are at the same potential. The other source / drain of the P-type TFT552 is supplied with a high power supply potential VGH. The high power supply potential VGH is constant.

[0118] One of the source / drain terminals of the P-type TFT553 is connected to the gate of the pull-down P-type TFT312, and they are at the same potential. Signal IN2 is applied to the gate of the P-type TFT553. Signal IN2 is the output signal for the next stage shift register.

[0119] The gate of the P-type TFT554 is connected to the gate of the pull-up P-type TFT311, and their gate potentials are identical. One source / drain of the P-type TFT554 is connected to the gate of the pull-down P-type TFT312 via node N5, and they are at the same potential. The other source / drain of the P-type TFT554 is supplied with a high power supply potential VGH. The gates of the P-type TFT554, P-type TFT311, and N-type TFT315 are connected to node N6, and a clock signal CLK_DRV is supplied to them via capacitor 558.

[0120] The gate of the P-type TFT555 is supplied with signal IN1. One source / drain of the P-type TFT555 is connected to the gate of a pull-down P-type TFT312 via node N5, and they are at the same potential. The other source / drain of the P-type TFT555 is supplied with a low power supply potential VGL. The low power supply potential VGL is constant.

[0121] The operation of the circuit shown in Figure 11 will be explained below. Figure 12 shows the timing chart of the circuit shown in Figure 11. In the following, a high potential level of a signal is represented as H, and a low potential level as L. All high potential levels of signals are at the high power supply potential VGH, and low potential levels are at the low power supply potential VGL. In Figure 12, all signals are synchronized.

[0122] First, let's describe the state immediately before time T11. Input signal IN1 is H, clock signal CLK_DRV is L, and input signal IN2 is H. The potential of node N5 is H, and the potential of node N6 is L. The pull-down P-type TFT312 is OFF. P-type TFTs 553 and 555 are OFF. The pull-down N-type TFT315 is OFF, and the pull-up P-type TFT311 and P-type TFT554 are ON. The output signal OUT is H.

[0123] Next, the operation of the components at time T11 and immediately afterward at time T12 will be described. At time T11, the clock signal CLK_DRV changes from L to H, and immediately afterward at time T12, the input signal IN1 changes from H to L. In response to the change in the clock signal CLK_DRV, the potential of node N6 changes from L to H. The P-type TFT554 and the pull-up P-type TFT311 turn OFF. The pull-down N-type TFT315 turns ON.

[0124] In response to a change in input signal IN1, the P-type TFT 555 turns ON, and the potential of node N5 changes from H to L. The P-type TFT 552 turns ON, and the potential of node N6 is maintained at H. Also, the pull-down P-type TFT 312 turns ON. The clock signal CLK_DRV is H, and the output signal OUT remains H.

[0125] Next, we will explain the operation of the components at time T21, which follows time T12, and at time T22, which follows immediately after. At time T21, none of the signals change. At time T22, the input signal IN1 changes from L to H, and the clock signal CLK_DRV changes from H to L.

[0126] In response to the change in input signal IN1, the P-type TFT 555 turns OFF. The P-type TFT 553 remains OFF. Node N5 is in a floating state, and its potential is maintained at L. Therefore, the pull-down P-type TFT 312 remains ON.

[0127] As described above, the clock signal CLK_DRV changes to L, but the potential of node N6 is maintained at H by capacitor 559 and the ON P-type TFT 552. Therefore, the P-type TFT 554 and the pull-up P-type TFT 311 remain OFF, and the pull-down N-type TFT 315 remains ON. Since the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L.

[0128] Next, we will explain the operation of the components at time T31, which follows time T22, and at time T32, which follows immediately after. At time T31, the clock signal CLK_DRV changes from L to H. In response to the change in the clock signal CLK_DRV from L to H, the output signal OUT changes from L to H.

[0129] At time T32, the input signal IN2 changes from H to L. In response to the change in input signal IN2 from H to L, the P-type TFT 553 turns ON, and the potential of node N5 changes from L to H. In response to the change in potential of node N5, the P-type TFT 552 turns OFF, and the pull-down P-type TFT 312 also turns OFF.

[0130] Node N6 is in a floating state, and its potential remains high. Therefore, the pull-up P-type TFT311 remains OFF, and the pull-down N-type TFT315 remains ON. Since the clock signal CLK_DRV is high, the output signal OUT is high.

[0131] Next, we will explain the operation of the components at time T41, which follows time T32, and at time T42, which immediately follows. At time T41, the input signal IN2 changes from L to H. In response to the change in input signal IN2 from L to H, the P-type TFT553 turns OFF.

[0132] At time T42, the clock signal CLK_DRV changes from H to L. This change in the clock signal CLK_DRV from H to L causes the potential of node N6 to change from H to L. In response, the P-type TFT 554 and the pull-up P-type TFT 311 turn ON, and the pull-down N-type TFT 315 turns OFF. Since the pull-up P-type TFT 311 is ON and the pull-down TFTs 312 and 315 are OFF, the output OUT remains H.

[0133] Next, we will describe the operation of the components at time T51, which follows time T42, and immediately after at time T52. At time T51, the clock signal CLK_DRV changes from L to H. There is no change in the signal at time T52.

[0134] In response to the change in the clock signal CLK_DRV from L to H, the potential of node N6 changes from L to H. In response to the change in the potential of node N6 from L to H, the P-type TFT554 and the pull-up P-type TFT311 turn OFF. The pull-down N-type TFT315 turns ON. The pull-down P-type TFT312 remains OFF. Since the clock signal CLK_DRV is H, the output OUT remains H.

[0135] Next, we will describe the operation of the components at time T61, following time T52, and immediately after, at time T62. There is no change in the signals at time T61. At time T62, the clock signal CLK_DRV changes from H to L. Accordingly, the potential of node N6 changes from H to L.

[0136] In response to the change in potential at node N6 from H to L, the P-type TFT 554 and the pull-up P-type TFT 311 turn ON. The pull-down N-type TFT 315 turns OFF. The pull-down P-type TFT 312 remains OFF. The pull-up P-type TFT 311 turns VGH on output line 3. 21 Since it is supplied to the signal, the output OUT remains high.

[0137] From time 62 onwards, the operation from time T42 to time T62 is repeated until the next frame. As described above, between time T42 and time T62, the P-type TFT 554 and the pull-up P-type TFT 311 are switched ON / OFF. The two P-type TFTs are ON between time T42 and time T51, and OFF from time T51 to T62 (T42).

[0138] If a P-type TFT remains ON, a Vg+ stress is applied, which can cause a Vt (threshold) shift. As described above, by switching the two P-type TFTs 554 and 311 ON / OFF in accordance with the clock signal CLK_DRV, the Vg+ stress is alleviated, and instability in circuit operation due to the Vt shift can be suppressed.

[0139] The periods from time T11 to T12, from time T21 to T22, from time T31 to T32, from time T41 to T42, from time T51 to T52, and from time T61 to T62 are very short periods compared to the clock period. The clock period is, for example, the period (length) from time T11 to time T31.

[0140] In one cycle of the clock signal CLK_DRV shown in Figure 12, the H period is slightly longer than the L period, but the difference is very small, and the duty cycle of the clock signal CLK_DRV is effectively 50%. The clock signal CLK_DRV can appropriately generate the output signal OUT and effectively suppress the Vt shift of the TFT.

[0141] Figure 13 shows a partial configuration of a shift register, including the shift register units described with reference to Figures 11 and 12. Figure 13 shows the first-stage shift register unit SR11, the second-stage shift register unit SR12, and the third-stage shift register unit SR13. Each of the shift register units SR11, SR12, and SR13 can have the circuit configuration described with reference to Figures 11 and 12. Depending on the design, the shift register can be composed of n connected stages (where n is a positive integer) of shift register units.

[0142] Each shift register unit includes multiple signal terminals. Specifically, these are the VGH terminal 631, IN1 terminal 632, VGL terminal 633, OUT terminal 635, CLK_DRV terminal 636, and IN2 terminal 637. In Figure 13, the terminals of the first-stage shift register unit SR11 are indicated by symbols as an example.

[0143] The OUT terminal 635 outputs the output signal OUT shown in Figure 12. A constant high power supply potential VGH is supplied to the VGH terminal 631. A constant low power supply potential VGL is supplied to the VGL terminal 633. The signal from the IN1 terminal 632 is the input signal IN1 in Figure 12. The signal input to the CLK_DRV terminal 636 is the clock signal CLK_DRV shown in Figure 12. The signal from the IN2 terminal 637 is the input signal IN2 in Figure 12. Some input signals to the shift registers are supplied from the driver IC 134.

[0144] The shift register units SR11, SR12, and SR13 each output output signals OUT11, OUT12, and OUT13 from the OUT terminal 635, respectively. The output signals are supplied to the gate of the TFT24 in the pixel circuit, and further supplied to the IN1 terminal 632 of the next stage shift register unit and the IN2 terminal 637 of the previous stage shift register unit. The start signal ST is input to the IN1 terminal 632 of the first stage shift register unit SR11.

[0145] The (2k-1)th stage CLK_DRV terminal 636 is supplied with the clock signal C11, and the 2kth stage CLK_DRV terminal 636 is supplied with the clock signal C12. k is a positive integer. Clock signals C11 and C12 each show changes corresponding to the clock signal CLK_DRV explained with reference to Figure 12 for each shift register unit.

[0146] Next, other configuration examples of the shift register unit will be described. Figure 14 shows an example of the shift register unit configuration. Below, the differences from the configuration example shown in Figure 11 will be mainly explained. The shift register unit shown in Figure 14 includes P-type TFTs 557 and 558 in addition to the configuration example shown in Figure 11. Also, the gate of the pull-down N-type TFT 315 is not connected to the gate of the pull-up P-type TFT 311. Node N7 is shown on the line connecting the gates of the P-type TFT 554 and the pull-up P-type TFT 311.

[0147] The gate of the P-type TFT557 is connected to output line 321, and they are at the same potential. A high power supply potential VGH is applied to one of the source / drain of the P-type TFT557. The other source / drain of the P-type TFT557 is connected to the gate of the pull-down N-type TFT via node N8, and they are at the same potential.

[0148] The gate of the P-type TFT558 is supplied with the clock signal CLK_RST. One of the source / drain of the P-type TFT558 is supplied with a low power supply potential VGL. The other source / drain of the P-type TFT558 is connected to the gate of a pull-down N-type TFT via node N8, and they are at the same potential.

[0149] Figure 15 shows the timing chart for the circuit shown in Figure 14. Compared to the timing chart shown in Figure 12, the time variation of the potential of node N6 has been removed, and the time variations of the clock signal CLK_RST and the potentials of nodes N7 and N8 have been added.

[0150] First, let's describe the state immediately before time T11. Input signal IN1 is H, clock signal CLK_DRV is L, clock signal CLK_RST is H, and input signal IN2 is H. The potential at node N5 is H, the potential at node N7 is L, and the potential at node N8 is L.

[0151] The pull-down P-type TFT312 is OFF. P-type TFTs 553 and 555 are OFF. P-type TFT 558 is OFF. The pull-up P-type TFTs 311 and 554 are ON, and the pull-down N-type TFT315 is OFF. The output signal OUT is H, and P-type TFT 557 is OFF.

[0152] Next, we will describe the operation of the components at time T11 and immediately afterward at time T12. At time T11, the clock signal CLK_DRV changes from L to H. In response to the change in the clock signal CLK_DRV, the potential of node N7 changes from L to H. The P-type TFT554 and the pull-up P-type TFT311 turn OFF.

[0153] At time T12, the input signal IN1 changes from high to low, and the clock signal CLK_RST changes from high to low. In response to the change in the clock signal CLK_RST, the P-type TFT 558 turns ON. The potential of node N8 remains low, and the pull-down N-type TFT 315 remains OFF.

[0154] In response to a change in the input signal IN1, the P-type TFT 555 turns ON, and the potential of node N5 changes from H to L. The pull-down P-type TFT 312 turns ON. The clock signal CLK_DRV is H, and the output signal OUT remains H.

[0155] Next, at time T21, after time T12, the clock signal CLK_RST changes from L to H. In response to the change in the clock signal CLK_RST, the P-type TFT558 turns OFF. The potential of node N8 is maintained at L, and the pull-down N-type TFT315 remains OFF.

[0156] Next, at time T22, immediately following time T21, the input signal IN1 changes from L to H, and the clock signal CLK_DRV changes from H to L. In response to the change in input signal IN1, the P-type TFT 555 turns OFF. The P-type TFT 553 remains OFF. Node N5 is in a floating state, and its potential is maintained at L. Therefore, the pull-down P-type TFT 312 remains ON.

[0157] As described above, the clock signal CLK_DRV changes to L, but the potential of node N7 is maintained at H by capacitor 559 and the ON P-type TFT 552. Therefore, the P-type TFT 554 and the pull-up P-type TFT 311 remain OFF. Since the clock signal CLK_DRV changes from H to L, the output signal OUT changes from H to L. The P-type TFT 557 turns ON, the potential of node 8 changes from L to H, and the pull-down N-type TFT 315 turns ON.

[0158] Next, at time T31, after time T22, the clock signal CLK_DRV changes from L to H. The potential of node N7 remains H, and the P-type TFT554 and the pull-up P-type TFT311 remain OFF. The potential of node N5 remains L, and the potential of node N8 remains H. Therefore, the pull-down P-type TFT312 and the pull-down N-type TFT315 remain ON.

[0159] As the clock signal CLK_DRV changes from L to H, the output signal OUT also changes from L to H. In response, the P-type TFT557 turns OFF. Node N8 becomes floating, and its potential remains H.

[0160] Next, at time T32, immediately following time T31, the input signal IN2 changes from H to L, and the clock signal CLK_RST changes from H to L. In response to the change in input signal IN2 from H to L, the P-type TFT 553 turns ON, and the potential of node N5 changes from L to H. In response to the change in potential of node N5, the P-type TFT 552 and the pull-down P-type TFT 312 turn OFF.

[0161] In response to the change in the clock signal CLK_RST from high to low, the P-type TFT 558 turns ON. The potential of node N8 changes from high to low, and the pull-down N-type TFT 315 turns OFF. Output line 321 becomes floating, and the output signal OUT remains high.

[0162] Next, at time T41, after time T32, the input signal IN2 changes from L to H, and the clock signal CLK_RST changes from L to H. In response to the change in input signal IN2 from L to H, the P-type TFT553 turns OFF. Node N5 becomes floating, and its potential is maintained at H. In response to the change in clock signal CLK_RST from L to H, the P-type TFT558 turns OFF. Node N8 becomes floating, and its potential is maintained at L.

[0163] At time T42, immediately following time T41, the clock signal CLK_DRV changes from H to L. This change in the clock signal CLK_DRV from H to L causes the potential of node N7 to change from H to L. In response, the P-type TFT 554 and the pull-up P-type TFT 311 turn ON. The potential of node N5 remains H. Node N8 is in a floating state and remains L. Therefore, the pull-down TFTs 312 and 315 remain OFF. As a result, the output OUT remains H.

[0164] Next, at time T51, after time T42, the clock signal CLK_DRV changes from L to H. Accordingly, the potential of node N7 changes from L to H. In response to the change in the potential of node N7 from L to H, the P-type TFT 554 and the pull-up P-type TFT 311 turn OFF. Node N5 is floating and remains H. Node N8 is floating and remains L. Therefore, the pull-down TFTs 312 and 315 remain OFF. Output line 321 is floating and output OUT remains H.

[0165] At time T52, immediately following time T51, the clock signal CLK_RST changes from H to L. The P-type TFT 558 turns ON. The potential of node N8 remains L. Other TFTs, including the pull-down N-type TFT 315, remain OFF. Output line 321 is floating, and output OUT remains H.

[0166] Next, at time T61, after time T52, the clock signal CLK_RST changes from L to H. The P-type TFT 558 turns OFF. Node N8 becomes floating, and its potential remains L. All other TFTs also remain OFF. Output line 321 is floating, and output OUT remains H.

[0167] At time T62, immediately following time T61, the clock signal CLK_DRV changes from H to L. Accordingly, the potential of node N7 changes from H to L. Node N 7In response to the change in potential from H to L, the P-type TFT 554 and the pull-up P-type TFT 311 turn ON. The other TFTs remain OFF. The pull-up P-type TFT 311 turns VGH on output line 3 21 When this is applied, the output OUT remains high.

[0168] From time 62 onwards, the operation from time T42 to time T62 is repeated until the next frame. As described above, between time T42 and time T62, the P-type TFT 554 and the pull-up P-type TFT 311 switch ON / OFF. The two P-type TFTs are ON from time T42 to time T51, and OFF from time T51 to T62 (T42). By switching the two P-type TFTs 554 and 311 ON / OFF in accordance with the clock signal CLK_DRV, Vg+ stress is alleviated, and instability in circuit operation due to Vt shift can be suppressed.

[0169] Figure 16 shows a partial configuration of a shift register, including the shift register units described with reference to Figures 14 and 15. Figure 16 shows the first-stage shift register unit SR21, the second-stage shift register unit SR22, and the third-stage shift register unit SR23. Shift register units SR21, SR22, and SR23 can each have the circuit configuration described with reference to Figures 14 and 15. Depending on the design, the shift register can be composed of n connected stages (where n is a positive integer) of shift register units.

[0170] Each shift register unit includes multiple signal terminals. Specifically, these are the VGH terminal 651, IN1 terminal 652, VGL terminal 653, CLK_RST terminal 654, OUT terminal 655, CLK_DRV terminal 656, and IN2 terminal 657. In Figure 16, the terminals of the first-stage shift register unit SR21 are indicated by symbols as an example.

[0171] The OUT terminal 655 outputs the output signal OUT shown in Figure 14. A constant high power supply potential VGH is supplied to the VGH terminal 651. A constant low power supply potential VGL is supplied to the VGL terminal 653. The signal from the IN1 terminal 652 is the input signal IN1 in Figure 15. The signal input to the CLK_RST terminal 654 is the clock signal CLK_RST shown in Figure 15. The signal input to the CLK_DRV terminal 656 is the clock signal CLK_DRV shown in Figure 15. The signal from the IN2 terminal 657 is the input signal IN2 in Figure 15. Some input signals to the shift register unit are supplied from the driver IC 134.

[0172] The shift register units SR21, SR22, and SR23 output output signals OUT21, OUT22, and OUT23, respectively, from the OUT terminal 655. The output signals are supplied to the gate of the TFT24 in the pixel circuit, and further supplied to the IN1 terminal 652 of the next stage shift register unit and the IN2 terminal 657 of the previous stage shift register unit. The start signal ST is input to the IN1 terminal 652 of the first stage shift register unit SR21.

[0173] The (2k-1)th stage CLK_DRV terminal 656 is supplied with the clock signal C21, and the 2kth stage CLK_DRV terminal 656 is supplied with the clock signal C22. The (2k-1)th stage CLK_RST terminal 654 is supplied with the clock signal C22, and the 2kth stage CLK_RST terminal 654 is supplied with the clock signal C21. k is a positive integer. Clock signals C21 and C22 show changes corresponding to the clock signal CLK_DRV explained with reference to Figure 15, respectively, for each shift register unit.

[0174] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0175] 10 OLED display device, 105 data line, 106 scan line, 108 power line, 109 measurement control line, 110 reference voltage supply line, 110 reference voltage supply line, 125 display area, 131, 132 scan driver, 134 driver IC, 311 pull-up P-type TFT, 312 pull-down P-type TFT, 315 pull-down N-type TFT, 321 output line, 331 high-potential line, 332 low-potential line, 333 low-potential line, 341 residual charge, 351, 352, 361, 362 LTPS film, 353, 363 oxide semiconductor film, 611 VGH terminal, 612 IN terminal, 613 VGL terminal, 614 CLK_RST terminal, 615 OUT terminal, 616 CLK_DRV terminal, N1, N2, N3, N4 Node, SR1-SR3 shift register unit

Claims

1. A shift register, It includes multiple shift register units that output sequential output signals, Each of the aforementioned multiple shift register units includes a circuit that outputs an output signal from an output line, The aforementioned circuit is First output signal supply wiring, Second output signal supply wiring, Output line and, A first P-type thin-film transistor that switches ON / OFF between the first output signal supply wiring and the output line, An N-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, A second P-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, Includes, While the first P-type thin-film transistor is ON, the N-type thin-film transistor and the second P-type thin-film transistor are OFF, and the signal from the first output signal supply wiring is supplied to the output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and the signal from the second output signal supply wiring is supplied to the output line. The aforementioned circuit is First control switch thin-film transistor, The second control switch thin-film transistor, It further includes, The first control switch thin-film transistor and the second control switch thin-film transistor have the same conductivity type and are controlled ON / OFF by the same input signal. When one of the first control switch thin-film transistor and the second control switch thin-film transistor is in the ON state, it applies a gate signal to the first P-type thin-film transistor and the N-type thin-film transistor. The other of the first control switch thin-film transistor and the second control switch thin-film transistor, in the ON state, provides a gate signal to the second P-type thin-film transistor. Shift register.

2. A shift register according to claim 1, The first P-type thin-film transistor and the second P-type thin-film transistor are P-type polysilicon thin-film transistors. Shift register.

3. A shift register according to claim 2, A first gate signal is input to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal, which exhibits a time evolution in the opposite direction to the first gate signal, is input to the gate of the second P-type thin-film transistor. Shift register.

4. A shift register according to claim 1 or 2, The second P-type thin-film transistor sets the potential of the output line to a potential that is a predetermined voltage higher than the potential of the second output signal supply wiring. The N-type thin-film transistor sets the potential of the output line from a potential that is a predetermined voltage higher than the potential of the second output signal supply wiring to the potential of the second output signal supply wiring. Shift register.

5. A shift register according to claim 1, One of the first output signal supply wiring and the second output signal supply wiring provides a constant potential signal. The other of the first output signal supply wiring and the second output signal supply wiring provides a signal that periodically changes between a low potential and a high potential. Shift register.

6. A shift register according to claim 1, The circuit further includes a third control switch thin-film transistor, A first gate signal is applied to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal is applied to the gate of the second P-type thin-film transistor. One of the first gate signal and the second gate signal is applied to the gate of the third control switch thin-film transistor. The third control switch thin-film transistor, in the ON state, provides the other of the first gate signal and the second gate signal. Shift register.

7. A shift register according to claim 1, The circuit further includes a fourth control switch thin-film transistor, A first gate signal is applied to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal is applied to the gate of the second P-type thin-film transistor. The fourth control switch thin-film transistor is in a diode connection state. A periodically changing signal is input to the drain of the fourth control switch thin-film transistor. The fourth control switch thin-film transistor, in a forward bias state, provides either the first gate signal or the second gate signal. Shift register.

8. A shift register according to claim 1, The circuit further includes a third control switch thin-film transistor and a fourth control switch thin-film transistor, A first gate signal is applied to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal is applied to the gate of the second P-type thin-film transistor. One of the first gate signal and the second gate signal is applied to the gate of the third control switch thin-film transistor. The third control switch thin-film transistor, in the ON state, receives the other of the first gate signal and the second gate signal. The fourth control switch thin-film transistor is in a diode connection state. A periodically changing signal is input to the drain of the fourth control switch thin-film transistor. The fourth control switch thin-film transistor, in a forward bias state, provides either the first gate signal or the second gate signal. Shift register.

9. A shift register, It includes multiple shift register units that output sequential output signals, Each of the aforementioned multiple shift register units includes a circuit that outputs an output signal from an output line, The aforementioned circuit is First output signal supply wiring, Second output signal supply wiring, Output line and, A first P-type thin-film transistor that switches ON / OFF between the first output signal supply wiring and the output line, An N-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, A second P-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, Includes, While the first P-type thin-film transistor is ON, the N-type thin-film transistor and the second P-type thin-film transistor are OFF, and the signal from the first output signal supply wiring is supplied to the output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and the signal from the second output signal supply wiring is supplied to the output line. The circuit further includes a fourth control switch thin-film transistor, A first gate signal is applied to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal is applied to the gate of the second P-type thin-film transistor. The fourth control switch thin-film transistor is in a diode connection state. A periodically changing signal is input to the drain of the fourth control switch thin-film transistor. The fourth control switch thin-film transistor, in a forward bias state, provides either the first gate signal or the second gate signal. Shift register.

10. A shift register, It includes multiple shift register units that output sequential output signals, Each of the aforementioned multiple shift register units includes a circuit that outputs an output signal from an output line, The aforementioned circuit is First output signal supply wiring, Second output signal supply wiring, Output line and, A first P-type thin-film transistor that switches ON / OFF between the first output signal supply wiring and the output line, An N-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, A second P-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, Includes, While the first P-type thin-film transistor is ON, the N-type thin-film transistor and the second P-type thin-film transistor are OFF, and the signal from the first output signal supply wiring is supplied to the output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and the signal from the second output signal supply wiring is supplied to the output line. The circuit further includes a third control switch thin-film transistor and a fourth control switch thin-film transistor, A first gate signal is applied to the gates of the first P-type thin-film transistor and the N-type thin-film transistor. A second gate signal is applied to the gate of the second P-type thin-film transistor. One of the first gate signal and the second gate signal is applied to the gate of the third control switch thin-film transistor. The third control switch thin-film transistor, in the ON state, receives the other of the first gate signal and the second gate signal. The fourth control switch thin-film transistor is in a diode connection state. A periodically changing signal is input to the drain of the fourth control switch thin-film transistor. The fourth control switch thin-film transistor, in a forward bias state, provides either the first gate signal or the second gate signal. Shift register.

11. A shift register, It includes multiple shift register units that output sequential output signals, Each of the aforementioned multiple shift register units includes a circuit that outputs an output signal from an output line, The aforementioned circuit is First output signal supply wiring, Second output signal supply wiring, Output line and, A first P-type thin-film transistor that switches ON / OFF between the first output signal supply wiring and the output line, An N-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, A second P-type thin-film transistor that switches ON / OFF between the second output signal supply wiring and the output line, Includes, While the first P-type thin-film transistor is ON, the N-type thin-film transistor and the second P-type thin-film transistor are OFF, and the signal from the first output signal supply wiring is supplied to the output line. While the N-type thin-film transistor and the second P-type thin-film transistor are ON, the first P-type thin-film transistor is OFF, and the signal from the second output signal supply wiring is supplied to the output line. The circuit outputs an L-level signal pulse, The first output signal supply wiring supplies a signal at a constant H level. During a predetermined period in which the output line outputs an L-level signal pulse followed by an H-level signal, the first P-type thin-film transistor repeatedly switches ON / OFF. Shift register.

12. A shift register according to claim 11, The first P-type thin-film transistor and the N-type thin-film transistor are turned ON / OFF by a clock signal. The second output signal supply wiring supplies the clock signal. Shift register.

13. A shift register according to claim 11, The first P-type thin-film transistor is turned ON / OFF by a clock signal, During the predetermined period, the N-type thin-film transistor and the second P-type thin-film transistor are OFF. Shift register.

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