Capacitively coupled variable positive voltage level shifting circuit

Abstract

This invention discloses a capacitively coupled variable positive voltage level shifter circuit, comprising: a capacitive coupling unit, a protection unit, and a level output unit. The capacitive coupling unit consists of a symmetrical PMOS transistor, a capacitor, and a NOT gate, receiving the input signal and power supply. The protection unit consists of a Zener diode and two NMOS transistors. The level output unit consists of three sets of NMOS transistors and PMOS transistors. It can be applied to electronic circuits that transmit signals between circuits or systems with different voltage levels, adjusting the voltage signal of the input signal to the level required by the target circuit. Furthermore, the output level can be adjusted by adjusting the diode and the input power supply, while maintaining the logical characteristics of the signal.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically a capacitively coupled variable positive voltage level shifting circuit. Background Technology

[0002] With the rapid development of integrated circuit technology, chip integration is constantly increasing, functional modules are becoming increasingly complex, and the need for signal interaction between different voltage levels is becoming more frequent. As a bridge connecting different voltage levels, the performance of level shifting circuits directly affects the stability, reliability, and efficiency of the entire integrated circuit system. In emerging application scenarios such as IoT devices, 5G communication base stations, and new energy vehicle electronic control systems, not only are level shifting circuits required to effectively convert between high and low voltage signals, but stringent requirements are also placed on their response speed, power consumption, and anti-interference capabilities.

[0003] Traditional level shifting circuits primarily rely on capacitive coupling and level conversion chips to achieve signal shifting and transmission. However, these circuits exhibit numerous problems in practical applications. Regarding charge leakage, traditional circuits depend on coupling capacitors to transmit level signals, but due to manufacturing limitations and parasitic effects during circuit operation, charge leakage is unavoidable. For example, in applications requiring the maintenance of a specific level for extended periods, the charge on the capacitor gradually dissipates, causing the output level to deviate from the preset value and triggering signal transmission errors. In intelligent sensor nodes, after weak signals undergo level shifting, level drift caused by charge leakage can lead to significant errors in the sensor's data acquisition, affecting the system's decision-making accuracy.

[0004] Unstable level transitions are a major drawback of traditional level shifting circuits. In high-speed signal transmission scenarios, such as high-speed data exchange in data centers and high-frequency signal processing within AI chips, signal levels need to transition within an extremely short time. However, traditional circuits, due to the switching delays of their internal components and the influence of parasitic capacitance and inductance, struggle to achieve fast and accurate level transitions. When the input signal changes, the output signal may exhibit phenomena such as excessively slow rise / fall times or ringing, leading to compromised signal integrity. In severe cases, it may even prevent the correct identification of signals, limiting the data transmission rate and operating frequency of integrated circuit systems. This has become a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a capacitively coupled variable positive voltage level shifter circuit to overcome the shortcomings of the prior art. It can be applied to electronic circuits that transmit signals between circuits or systems with different voltage levels, adjust the voltage signal of the input signal to the level required by the target circuit, and adjust the output level by adjusting the diode and the input power supply, while keeping the logic characteristics of the signal unchanged.

[0006] One embodiment of this application provides a capacitively coupled variable positive voltage level shifting circuit, comprising:

[0007] The system includes a capacitive coupling unit, a protection unit, and a level output unit. The capacitive coupling unit includes a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1. The protection unit includes a first Zener diode D1, a second Zener diode D2, a first NMOS transistor N1, and a second NMOS transistor N2; The level output unit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5; The electrical connections are as follows: One end of the first capacitor C1 is connected in series with the first PMOS transistor P1, and one end of the second capacitor C2 is connected in series with the second PMOS transistor P2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are connected to the power supply. The drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the first capacitor C1 and the second capacitor C2, respectively. The gate of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1. The other end of the first capacitor C1 is connected to the first input signal. The other end of the second capacitor C2 is connected to the second input signal inverted by the NOT gate. connect; The cathodes of the first Zener diode D1 and the second Zener diode D2 are respectively connected to the power supply. The connections are as follows: the anode of the first Zener diode D1 is connected to the drain of the first NMOS transistor N1, and the anode of the second Zener diode D2 is connected to the drain of the second NMOS transistor N2. The drains of the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to the power supply. The source of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the source of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are respectively connected to the power supply. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the gates of the first PMOS transistor P1 and the second PMOS transistor P2, respectively. The drains of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the drains of the first NMOS transistor N1 and the second NMOS transistor N2, respectively. Among them, a first connection point a is provided between the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3, and a second connection point b is provided between the drain of the fourth PMOS transistor P4 and the fourth NMOS transistor N4. The source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are respectively connected to the anode of the first Zener diode D1 and the anode of the second Zener diode D2. The gates of the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are directly connected and a third connection point c is provided. The third connection point c is connected to the second connection point b. The source of the fifth PMOS transistor P5 is connected to the power supply. The source of the fifth NMOS transistor N5 is connected to the anode of the second Zener diode D2, and the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5. An output point d is provided, which is used as the output of the level output unit and connected to the external circuit.

[0008] Optionally, the capacitive coupling unit is used to achieve voltage boost; the protection unit is used to maintain the capacitor level and prevent circuit components from being mis-connected; the level output unit is used to adjust the phase of the level so that the output level corresponds to the high and low potentials of the input level.

[0009] Optionally, the capacitive coupling unit adopts a first cross-latch structure; the first cross-latch structure includes a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1.

[0010] Optionally, the first capacitor C1 and the second capacitor C2 have the same capacitance value, and the first PMOS transistor P1 and the second PMOS transistor P2 include P-type LDMOS transistors.

[0011] Optionally, the first input signal The range of values ​​is ,in, This indicates the high level of the first input signal.

[0012] Optionally, the gates of the first PMOS transistor P1 and the third PMOS transistor P3 are connected, and the level output unit adopts a second cross-latch structure; the second cross-latch structure includes a bridge arm interlock structure formed by connecting the first connection point a and the second connection point b, and a symmetrical structure formed by the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, and the fourth NMOS transistor N4; wherein, one end of the symmetrical structure is connected to the power supply. The other end is connected to the reference voltage after being stepped down by the first Zener diode D1 and the second Zener diode D2. .

[0013] Optionally, the reference voltage This includes the gate control voltages of the first NMOS transistor N1 and the second NMOS transistor N2; the threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are... The reference voltage With the threshold voltage The difference is .

[0014] Optionally, the reference voltage With the threshold voltage The difference Less than the power supply High level of the first input signal The difference.

[0015] Optionally, by adjusting the power supply The output level is determined by the breakdown voltages of the first Zener diode D1 and the second Zener diode D2.

[0016] Another embodiment of this application provides an apparatus including the capacitively coupled variable positive voltage level shift circuit described in any of the preceding claims.

[0017] Compared with the prior art, the present invention provides a capacitively coupled variable positive voltage level shifting circuit, comprising: a capacitive coupling unit, a protection unit, and a level output unit, wherein the capacitive coupling unit consists of a symmetrical PMOS transistor, a capacitor, and a NOT gate, and receives an input signal. and power supply The protection unit consists of a Zener diode and two NMOS transistors; the level output unit consists of three sets of NMOS and PMOS transistors. It can be applied to electronic circuits that transmit signals between circuits or systems with different voltage levels. It adjusts the voltage signal of the input signal to the level required by the target circuit, and the output level can be adjusted by adjusting the diodes and the input power supply, while maintaining the logic characteristics of the signal unchanged. Attached Figure Description

[0018] Figure 1 A schematic diagram of a capacitively coupled variable positive voltage level shift circuit structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram showing the connection of each unit of a capacitively coupled variable positive voltage level shift circuit provided in an embodiment of the present invention. Figure 3 The waveform diagram shows the simulation results of a capacitively coupled variable positive voltage level shift circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] Traditional level shifting circuits have significant shortcomings in device protection. In real-world operating environments, circuits are inevitably affected by external factors such as voltage fluctuations, electrostatic discharge, and electromagnetic interference. For example, in industrial control, complex electromagnetic environments can induce transient overvoltages in circuits, and traditional circuits lack effective overvoltage protection mechanisms, easily leading to faults such as MOSFET gate oxide breakdown and device burnout. Furthermore, during level shifting, PMOS and NMOS transistors may simultaneously conduct, resulting in a shoot-through phenomenon. This causes a large instantaneous current to flow through the devices, generating excessive power consumption and heat, accelerating device aging, and reducing circuit reliability and lifespan.

[0020] As integrated circuits evolve towards higher voltage, higher speed, and lower power consumption, the performance of traditional level shifting circuits can no longer meet the demands of modern electronic systems. Developing novel level shifting circuits with high stability, fast response, and strong protection capabilities has become a key aspect of driving progress in integrated circuit technology. Therefore, an innovative level shifting circuit design is urgently needed to address many problems in existing technologies and improve the overall performance and application adaptability of integrated circuit systems.

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] See Figure 1 , Figure 1 A schematic diagram of a capacitively coupled variable positive voltage level shift circuit structure provided in an embodiment of the present invention is shown below. Figure 1 As shown, a capacitively coupled variable positive voltage level shifter circuit includes: The system includes a capacitive coupling unit, a protection unit, and a level output unit. The capacitive coupling unit comprises a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1. The protection unit comprises a first Zener diode D1, a second Zener diode D2, a first NMOS transistor N1, and a second NMOS transistor N2. The level output unit comprises a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5.

[0024] Figure 1 The electrical connections are shown below: One end of the first capacitor C1 is connected in series with the first PMOS transistor P1, and one end of the second capacitor C2 is connected in series with the second PMOS transistor P2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are connected to the power supply. The drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the first capacitor C1 and the second capacitor C2, respectively. The gate of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1. The other end of the first capacitor C1 is connected to the first input signal. The other end of the second capacitor C2 is connected to the second input signal inverted by the NOT gate. Connections. The cathodes of the first Zener diode D1 and the second Zener diode D2 are respectively connected to the power supply. The connections are as follows: the anode of the first Zener diode D1 is connected to the drain of the first NMOS transistor N1, and the anode of the second Zener diode D2 is connected to the drain of the second NMOS transistor N2. The drains of the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to the power supply. The first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the power supply. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the gates of the first PMOS transistor P1 and the second PMOS transistor P2, respectively. The drains of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the drains of the first NMOS transistor N1 and the second NMOS transistor N2, respectively. A first connection point a is provided between the drains of the third PMOS transistor P3 and the third NMOS transistor N3, and a second connection point b is provided between the drains of the fourth PMOS transistor P4 and the fourth NMOS transistor N4. The sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the anodes of the first Zener diode D1 and the second Zener diode D2, respectively.

[0025] The gates of the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are directly connected and a third connection point c is provided. The third connection point c is connected to the second connection point b. The source of the fifth PMOS transistor P5 is connected to the power supply. The source of the fifth NMOS transistor N5 is connected to the anode of the second Zener diode D2, and the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5. An output point d is provided, which is used as the output of the level output unit and connected to the external circuit.

[0026] It should be noted that the above electrical connection can be a direct electrical connection or an indirect electrical connection. A direct electrical connection means that two devices are directly connected, while an indirect electrical connection means that there are other devices such as capacitors and resistors connected between the connected A and B.

[0027] Wherein, the first connection point a is the junction connecting the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3; the second connection point b is the junction connecting the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4; the third connection point c is the junction connecting the gate of the fifth PMOS transistor P5 and the gate of the fifth NMOS transistor N5; and the output point d is the junction connecting the drain of the fifth PMOS transistor P5 and the drain of the fifth NMOS transistor N5, which is also the output... .

[0028] The function of the capacitive coupling unit is to boost the voltage, thereby changing the level; the protection unit maintains the capacitor level and prevents the device from being mis-energized during normal circuit operation, thus ensuring the normal operation of the circuit; the function of the level output unit is to adjust the phase of the level so that the output level corresponds to the high and low potentials of the input level.

[0029] The capacitive coupling unit adopts a first cross-latch structure; the first cross-latch structure includes a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1 to ensure stable operation.

[0030] The first capacitor C1 and the second capacitor C2 have the same capacitance value, and the first PMOS transistor P1 and the second PMOS transistor P2 include P-type LDMOS transistors.

[0031] For example, the first PMOS transistor P1 and the second PMOS transistor P2 are two P-type LDMOS transistors to meet the voltage withstand requirements of the circuit. C1 and C2 are coupling capacitors with the same capacitance value, and D1 and D2 are Zener diodes with a breakdown voltage of [missing value]. First input signal It has high and low level inputs, where the high level is... The low level is 0V, and the signal is inverted by an inverter U1. The first input signal The range of values ​​is , This indicates the high level of the first input signal.

[0032] When the first input signal When at a low level, High level The second PMOS transistor P2 is in the on state, at which time the gate potential of the first PMOS transistor P1 is pulled up to... Gate-source voltage It is currently in the off state.

[0033] When the first input signal When the voltage level rises from low to high, The signal transitions from high to low. At the instant of transition, no current flows in the branch containing the first capacitor C1, and the voltage across the capacitor remains constant. The drain voltage of the first PMOS transistor P1 changes with the first input signal. The increase in voltage causes the gate voltage of the second PMOS transistor P2 to rise below the threshold voltage, turning off the second PMOS transistor P2 and reducing the gate-source voltage. During this process, the current in the second capacitor C2 begins to decrease, and the drain voltage of the second PMOS transistor P2 decreases accordingly. The decrease in voltage reduces the gate-source voltage of the first PMOS transistor P1. It gradually reaches the threshold voltage and then conducts.

[0034] When the circuit is working normally, the first PMOS transistor P1 and the second PMOS transistor P2 will be in a cross-latch state. This state can prevent charge from leaking from the first PMOS transistor P1 and the second PMOS transistor P2 to the coupling capacitor when the output is stable, thus providing the necessary conditions for the stable operation of the level shift.

[0035] Specifically, the gates of the first PMOS transistor P1 and the third PMOS transistor P3 are connected, and the level output unit adopts a second cross-latch structure; the second cross-latch structure includes a bridge arm interlock structure formed by connecting the first connection point a and the second connection point b, and a symmetrical structure formed by the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, and the fourth NMOS transistor N4; wherein, one end of the symmetrical structure is connected to the power supply. The other end is connected to the reference voltage after being stepped down by the first Zener diode D1 and the second Zener diode D2. ,satisfy .

[0036] For example, the level output unit adopts a second cross-latch structure to prevent shoot-through between the upper and lower transistors. The output unit utilizes a symmetrical structure composed of the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, and the fourth NMOS transistor N4, with the upper end connected to a power supply. The lower end is connected to the reference voltage after being stepped down by Zener diodes D1 and D2. Then, the gates of the first PMOS transistor P1 and the third PMOS transistor P3 are connected together so that their switching states are the same. Simultaneously, the intermediate node a of the third PMOS transistor P3 and the third NMOS transistor N3 is connected to the intermediate node b of the fourth PMOS transistor P4 and the fourth NMOS transistor N4, completing the interlocking of the two bridge arms. When the third PMOS transistor P3 turns on along with the first PMOS transistor P1, the gate of the fourth NMOS transistor N4 is pulled high. ,That When the voltage exceeds the threshold, the transistor will turn on, and simultaneously, the fourth PMOS transistor P4, along with the second PMOS transistor P2, will be turned off, and point b will be pulled low. To ensure the third NMOS transistor N3 It is currently in the off state.

[0037] When the third PMOS transistor P3 is off and the fourth PMOS transistor P3P4 is on, the state is reversed, causing the third NMOS transistor N3 to turn on and the fourth NMOS transistor N4 to turn off. During normal circuit operation, the signals from the first PMOS transistor P1 and the second PMOS transistor P2 control the third PMOS transistor P3. It should be noted that the cross-latch mechanism of the fourth PMOS transistor P4 prevents a shoot-through situation involving the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, and the fourth NMOS transistor N4.

[0038] It should be noted that the reference voltage This includes the gate control voltages of the first NMOS transistor N1 and the second NMOS transistor N2; the threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are... The reference voltage With the threshold voltage The difference is ,satisfy .

[0039] The reference voltage With the threshold voltage The difference Less than the power supply High level of the first input signal The difference.

[0040] That is, the protection unit utilizes the breakdown voltage as The reference voltage generated by Zener diodes D1 and D2 The gate control voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are, and the threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are... When the voltage across the upper plate of the first capacitor C1 is lower than the difference between the reference voltage and the threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2, i.e. At this time, the first NMOS transistor N1 will turn on and begin charging the first capacitor C1 until the voltage on the upper plate of the first capacitor C1 rises to a level higher than 1000 kJ / kJ. At this time, the first NMOS transistor N1 is off, maintaining the capacitor level. The symmetrical second NMOS transistor N2 acts on the first capacitor C1, serving the same purpose. Meanwhile, to ensure that the first NMOS transistor N1 and the second NMOS transistor N2 do not conduct during normal circuit operation, It should be set lower than the supply voltage and the first input signal voltage. The difference between the high and low levels, i.e. This can prevent them from misleading the circuit when it is working normally, thus ensuring the normal operation of the circuit.

[0041] For example, the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 of the level output unit can be three P-type LDMOS transistors, and the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 can be three N-type LDMOS transistors.

[0042] In one alternative implementation, by adjusting the power supply... The output level is determined by the breakdown voltages of the first Zener diode D1 and the second Zener diode D2. The high level of the output is divided into... Low level is It can be achieved by adjusting the power supply voltage. Breakdown voltage of Zener diode To output a variable output level.

[0043] See Figure 2 , Figure 2 This is a schematic diagram showing the connection of each unit in a capacitively coupled variable positive voltage level shift circuit according to an embodiment of the present invention. First, the first input signal is determined. With power supply First input signal The signal is inverted by a NOT gate to obtain the second input signal. First input signal With the second input signal The input capacitive coupling unit controls the PMOS transistor's switching operation. Simultaneously, the protection unit safeguards the capacitive coupling unit, preventing voltage drops in the coupling capacitor from causing output errors. Finally, the level output unit receives the switching signal and power supply from the capacitive coupling unit. Power supply, output shifted level It is then passed to subsequent circuits.

[0044] In one alternative implementation, the output is controlled by the fifth PMOS transistor P5 and the fifth NMOS transistor N5. With input Level synchronization, high level is Low level is At the same time, it can be adjusted The input voltage and the breakdown voltage of the Zener diode can produce different output voltages. To meet different application requirements.

[0045] See Figure 3 , Figure 3 The waveform diagram shows the simulation results of a capacitively coupled variable positive voltage level shift circuit provided in an embodiment of the present invention. The simulation conditions are set as follows: power supply... The voltage is set to 18V. Zener diodes (D1, D2) are selected as model 1N750, with a breakdown voltage of [missing information]. 4.7V; Input signal (Green waveform) is a pulse signal with an amplitude of 0V to 3V.

[0046] observe Figure 3 visible: Level shifting and phase synchronization: Output signal (correspond Figure 3 The bottom blue waveform successfully transitioned from the low-voltage domain (0V-3V) to the high-voltage domain. Its high-level signal remained stable at... (18V), low level stabilizes at (Approximately 13.3V), and the rising and falling edges of the output waveform are steep, similar to the input signal. Maintaining a high degree of phase synchronization verifies the signal integrity of the circuit under high-speed switching.

[0047] Voltage regulation function of the protection unit: internal node voltage (correspond Figure 3 The red waveform in the middle layer visually illustrates the working mechanism of the protection unit. During the signal holding period, charge leakage is inevitable due to the coupling capacitor. However, once the voltage drops to the set protection threshold, the NMOS transistor in the protection unit immediately turns on to replenish the charge, dynamically clamping the voltage within a safe range, thereby avoiding logic errors caused by excessive voltage drift.

[0048] As can be seen from the above embodiments, the positive voltage level circuit in this invention can achieve stable level shifting for high and low level signals.

[0049] As can be seen, the beneficial effects achieved by the present invention using the above structure are as follows: (1) This invention can use P-type LDMOS transistors P1 and P2 to form a cross-latch structure, while the bridge arms formed by N3 and P3, and N4 and P4 are also cross-latched. During normal operation, P1 and P2 form a cross-latch state, which can effectively block the leakage path of charge from the output terminal to the coupling capacitor, ensuring charge stability during level shifting and maintaining the accuracy of the output signal. The symmetrical output structure of N3 and P3, and N4 and P4, combined with precise logic control, ensures that the output signal is stable and reliable. By using the interlocking mechanism to avoid device shoot-through, combined with reference voltage control, the output level is stabilized at the expected value, providing a high-quality input signal for subsequent circuits and improving the performance of the entire integrated circuit system.

[0050] (2) The present invention utilizes and The complementary control and capacitor voltage holding characteristics enable the circuit to achieve fast response and distortion-free transmission of level transitions. The capacitive coupling structure achieves near-zero delay; the only delay originates from the logic gates in the circuit, having a minimal impact on control response speed. Regardless of whether the input signal changes on the rising or falling edge, the output signal follows promptly and accurately, ensuring reliable signal transmission across different level domains and meeting the requirements of high-speed signal processing scenarios.

[0051] (3) This invention combines the reference voltage generated by the Zener diode with the interlocking mechanism of the MOSFET to provide multiple protections for the circuit devices. The Zener diode limits the voltage to prevent the MOSFET from being damaged by gate overvoltage, providing the necessary conditions for the stable operation of level shifting, greatly improving the reliability and stability of the circuit, and extending the service life of the circuit.

[0052] (4) The present invention can achieve variable output level by using different breakdown voltages of Zener diodes and different power supplies, so as to cope with different application scenarios.

[0053] This application also provides an apparatus comprising any of the above-described capacitively coupled variable positive voltage level shifting circuits.

[0054] Compared with the prior art, the present invention provides a capacitively coupled variable positive voltage level shifting circuit, comprising: a capacitive coupling unit, a protection unit, and a level output unit, wherein the capacitive coupling unit consists of a symmetrical PMOS transistor, a capacitor, and a NOT gate, and receives an input signal. and power supply The protection unit consists of a Zener diode and two NMOS transistors; the level output unit consists of three sets of NMOS and PMOS transistors. It can be applied to electronic circuits that transmit signals between circuits or systems with different voltage levels. It adjusts the voltage signal of the input signal to the level required by the target circuit, and the output level can be adjusted by adjusting the diodes and the input power supply, while maintaining the logic characteristics of the signal unchanged.

[0055] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0056] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0057] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A capacitively coupled variable positive voltage level shifting circuit, characterized in that: include: The system includes a capacitive coupling unit, a protection unit, and a level output unit. The capacitive coupling unit includes a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1. The protection unit includes a first Zener diode D1, a second Zener diode D2, a first NMOS transistor N1, and a second NMOS transistor N2; The level output unit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5; The electrical connections are as follows: One end of the first capacitor C1 is connected in series with the first PMOS transistor P1, and one end of the second capacitor C2 is connected in series with the second PMOS transistor P2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are connected to the power supply. The drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the first capacitor C1 and the second capacitor C2, respectively. The gate of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1. The other end of the first capacitor C1 is connected to the first input signal. The other end of the second capacitor C2 is connected to the second input signal inverted by the NOT gate. connect; The cathodes of the first Zener diode D1 and the second Zener diode D2 are respectively connected to the power supply. The connections are as follows: the anode of the first Zener diode D1 is connected to the drain of the first NMOS transistor N1, and the anode of the second Zener diode D2 is connected to the drain of the second NMOS transistor N2. The drains of the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to the power supply. The source of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the source of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are respectively connected to the power supply. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the gates of the first PMOS transistor P1 and the second PMOS transistor P2, respectively. The drains of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the drains of the first NMOS transistor N1 and the second NMOS transistor N2, respectively. Among them, a first connection point a is provided between the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3, and a second connection point b is provided between the drain of the fourth PMOS transistor P4 and the fourth NMOS transistor N4. The source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are respectively connected to the anode of the first Zener diode D1 and the anode of the second Zener diode D2. The gates of the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are directly connected and a third connection point c is provided. The third connection point c is connected to the second connection point b. The source of the fifth PMOS transistor P5 is connected to the power supply. The source of the fifth NMOS transistor N5 is connected to the anode of the second Zener diode D2, and the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5. An output point d is provided, which is used as the output of the level output unit and connected to the external circuit.

2. The capacitively coupled variable positive voltage level shifting circuit according to claim 1, characterized in that, The capacitive coupling unit is used to achieve voltage boost; the protection unit is used to maintain the capacitor level and prevent circuit components from being mis-energized. The level output unit is used to adjust the phase of the level so that the output level corresponds to the high and low potentials of the input level.

3. The capacitively coupled variable positive voltage level shifting circuit according to claim 2, characterized in that, The capacitive coupling unit adopts a first cross-latch structure; the first cross-latch structure includes a first capacitor C1, a second capacitor C2, a first PMOS transistor P1, a second PMOS transistor P2, and a NOT gate U1.

4. The capacitively coupled variable positive voltage level shifting circuit according to claim 3, characterized in that, The first capacitor C1 and the second capacitor C2 have the same capacitance value, and the first PMOS transistor P1 and the second PMOS transistor P2 include P-type LDMOS transistors.

5. A capacitively coupled variable positive voltage level shifting circuit according to claim 4, characterized in that, The first input signal The range of values ​​is ,in, This indicates the high level of the first input signal.

6. A capacitively coupled variable positive voltage level shifting circuit according to claim 5, characterized in that, The gates of the first PMOS transistor P1 and the third PMOS transistor P3 are connected. The level output unit adopts a second cross-latch structure. The second cross-latch structure includes a bridge arm interlock structure formed by connecting the first connection point a and the second connection point b, and a symmetrical structure formed by the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, and the fourth NMOS transistor N4. One end of the symmetrical structure is connected to the power supply. The other end is connected to the reference voltage after being stepped down by the first Zener diode D1 and the second Zener diode D2. .

7. A capacitively coupled variable positive voltage level shifting circuit according to claim 6, characterized in that, The reference voltage This includes the gate control voltages of the first NMOS transistor N1 and the second NMOS transistor N2; the threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are... The reference voltage With the threshold voltage The difference is .

8. A capacitively coupled variable positive voltage level shifting circuit according to claim 7, characterized in that, The reference voltage With the threshold voltage The difference Less than the power supply High level of the first input signal The difference.

9. A capacitively coupled variable positive voltage level shifting circuit according to claim 8, characterized in that, By adjusting the power supply The output level is determined by the breakdown voltages of the first Zener diode D1 and the second Zener diode D2.

10. A device, characterized in that, The variable positive voltage level shift circuit with capacitive coupling as described in any one of claims 1 to 9.

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