Crystal oscillator frequency self-calibration method, electronic device, and computer-readable storage medium

Abstract

This application discloses a crystal oscillator frequency self-calibration method, an electronic device, and a computer-readable storage medium. The method includes: acquiring a time deviation sequence; acquiring a voltage sequence; acquiring the processor's behavioral characteristics at the current wake-up time; determining the equivalent temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence, voltage sequence, and processor behavioral characteristics; testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matched test strategy based on the equivalent temperature of the crystal oscillator at the current wake-up time; and determining the final target capacitor connected to the crystal oscillator based on the target test frequency of the crystal oscillator with multiple different test capacitors connected and the multiple different test capacitors. This method can achieve self-calibration of the crystal oscillator frequency.

Description

Technical Field

[0001] This application relates to the field of embedded system clock technology, and in particular to a crystal oscillator frequency self-calibration method, electronic device, and computer-readable storage medium. Background Technology

[0002] Temperature can affect the frequency of a crystal oscillator, causing it to shift, which in turn leads to a time shift in the embedded system.

[0003] In existing technologies, to ensure the long-term stability of the real-time clock (RTC), a temperature sensor is usually set up to collect the temperature and then calibrate the crystal oscillator frequency, which increases the hardware cost. Summary of the Invention

[0004] This application provides a crystal oscillator frequency self-calibration method, an electronic device, and a computer-readable storage medium, which can achieve self-calibration of the crystal oscillator frequency without the need for a temperature sensor.

[0005] This application provides a crystal oscillator frequency self-calibration method, applied to a processor that operates based on the frequency provided by the crystal oscillator. The processor switches between sleep mode and wake-up mode at a preset cycle. The method includes: acquiring a time deviation sequence, the time deviation sequence including time deviation values ​​of the processor at multiple wake-up times, wherein the time deviation value of the processor at each wake-up time is equal to the difference between the test time and the theoretical time of the processor at that wake-up time; acquiring a voltage sequence, the voltage sequence including the supply voltage of a target circuit at the multiple wake-up times, wherein the target circuit is used to supply power to the processor; acquiring... The behavior characteristics of the processor at the current wake-up time are related to the number of times the processor has been woken up and the cumulative runtime within a preset time period before the current wake-up time. Based on the time deviation sequence, the voltage sequence, and the behavior characteristics of the processor, the equivalent temperature of the crystal oscillator at the current wake-up time is determined. Based on the equivalent temperature of the crystal oscillator at the current wake-up time, a matching test strategy is used to test the target test frequency of the crystal oscillator with multiple different test capacitors connected. Based on the target test frequency of the crystal oscillator with multiple different test capacitors connected and the multiple different test capacitors, the target capacitor finally connected to the crystal oscillator is determined.

[0006] A second aspect of this application provides an electronic device including a memory and a processor interconnected, wherein the memory is used to store a computer program, which, when executed by the processor, is used to implement the method as described in any of the above embodiments.

[0007] A third aspect of this application provides a computer-readable storage medium storing a computer program that can be executed by a processor to perform the steps of the method as described in any of the above embodiments.

[0008] Unlike existing technologies, the advantages of this application are as follows: This application first obtains multi-dimensional time series data such as time deviation, voltage and behavioral characteristics, and then infers the equivalent temperature environment of the crystal oscillator through fusion modeling. Based on the equivalent temperature, a matching test strategy is adopted to perform capacitance scanning and frequency measurement. The optimal capacitance value is selected according to the test results to complete self-calibration. The whole process does not require an external temperature sensor. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a flowchart illustrating the crystal oscillator frequency self-calibration method of this application; Figure 2 yes Figure 1 A flowchart illustrating one embodiment of step S400; Figure 3 yes Figure 2 A flowchart illustrating one embodiment of step S410; Figure 4 yes Figure 2 A flowchart illustrating one embodiment of step S420; Figure 5 yes Figure 2 A flowchart illustrating one embodiment of step S430; Figure 6 yes Figure 2 A flowchart illustrating one embodiment of step S440; Figure 7 yes Figure 1 A flowchart illustrating one embodiment of step S500; Figure 8 yes Figure 7 A flowchart illustrating one embodiment of step S530; Figure 9 yes Figure 1 A flowchart illustrating one embodiment of step S600; Figure 10 yes Figure 1 A flowchart illustrating an embodiment prior to step S600; Figure 11 yes Figure 1 A flowchart illustrating an embodiment following step S600; Figure 12 yes Figure 1 A flowchart illustrating another implementation method following step S600; Figure 13 This is a flowchart illustrating the method of this application in an application scenario; Figure 14 This is a schematic diagram of the structure of one embodiment of the electronic device of this application; Figure 15 This is a schematic diagram of one embodiment of the computer-readable storage medium of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0011] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0012] See Figure 1 , Figure 1 This is a flowchart illustrating the crystal oscillator frequency self-calibration method of this application. This application provides a crystal oscillator frequency self-calibration method applied to a processor. The processor operates based on the frequency provided by the crystal oscillator, and the processor switches between sleep mode and wake-up mode at a preset cycle. The method includes: S100: Obtain the time deviation sequence, which includes the time deviation values ​​of the processor at multiple wake-up times. The time deviation value of the processor at the wake-up time is equal to the difference between the test time and the theoretical time at the wake-up time.

[0013] Specifically, the processor continuously alternates between a low-power sleep mode and a normal wake-up mode according to a preset period, which can be 1 minute or 10 minutes, etc., and this application does not impose any restrictions. For each wake-up moment, the processor obtains the test time and the theoretical time of a crystal oscillator. The difference between the test time and the theoretical time yields the time deviation value for that wake-up moment. The time deviation value for each wake-up moment is recorded in a circular buffer. Multiple time deviation values ​​over a period of time constitute a time deviation sequence corresponding to each different wake-up moment, and the processor can read the time deviation sequence from the circular buffer. Optionally, the test time and theoretical time can be in the form of timestamps.

[0014] The specific formula for calculating the processor's time deviation at the wake-up moment is as follows: Δt[i] = t_wake_real[i]- t_wake_ideal[i].

[0015] Where t_wake_real[i] is the test time at the i-th wake-up time, t_wake_ideal[i] is the theoretical time at the i-th wake-up time, and Δt[i] is the time deviation value at the i-th wake-up time.

[0016] The specific formula for calculating the theoretical time of the processor at the wake-up moment is as follows: t_wake_ideal[i] = t_wake_ideal[i-1]+T_sleep.

[0017] Where t_wake_ideal[i-1] is the test time of the (i-1)th wake-up moment (i.e. the one before the i-th wake-up moment), and T_sleep is the preset period.

[0018] Obtain the time deviation sequence Δt_seq composed of multiple time deviation values.

[0019] In one implementation, each time the processor is woken up by a real-time clock (RTC) interrupt, at the beginning of the interrupt service routine (ISR), the test time of the current wake-up moment, recorded by a free-running counter driven by a high-frequency system clock (e.g., 48MHz), is read. At the same time, the theoretical time of the current wake-up moment is calculated in the interrupt service routine, and then the difference between the two is calculated to obtain the time deviation value of the current wake-up moment. Multiple time deviation values ​​(e.g., within a day) of the current wake-up moment are obtained, which is equivalent to obtaining the time deviation sequence of the current wake-up moment and the time deviation before it.

[0020] Of course, in some other implementations, the time deviation sequence may not include the current wake-up time, but may be a period of time before the current wake-up time.

[0021] S200: Obtain the voltage sequence, which includes the power supply voltage of the target circuit at multiple wake-up times. The target circuit is used to power the processor.

[0022] Specifically, the voltage is used to provide electrical signals to the target circuit in the processor to ensure its normal operation. At each wake-up time, similar to step S100, the voltage VDD of each wake-up time is acquired, and the voltage of the current wake-up time is recorded in the circular buffer. The voltage of the current wake-up time and the voltage of multiple different wake-up times before it are read from the circular buffer. These voltages constitute a voltage sequence.

[0023] In one implementation, at the i-th wake-up time, in the wake-up interrupt service routine, if the analog-to-digital converter (ADC) is idle, a sampling of the target circuit is initiated. The sampling result is converted into voltage VDD[i] through a pre-stored calibration coefficient and stored in a circular buffer. Then, the voltage sequence VDD_seq of the i-th wake-up time and the time period before it is read.

[0024] Of course, in some other implementations, the voltage sequence may not include the current wake-up time, but may be a period of time prior to the current wake-up time.

[0025] S300: Obtain the processor's behavioral characteristics at the current wake-up time. The processor's behavioral characteristics are related to the number of times the processor wakes up and the cumulative runtime within a preset time before the current wake-up time.

[0026] Specifically, the behavior characteristics of a processor mainly refer to its operating status. The number of times it is woken up within a preset time and the cumulative running time will result in different behavior characteristics and different power consumption.

[0027] In one embodiment, a counter is used to count the number of times the processor wakes up and the cumulative runtime within a preset duration prior to the current wake-up time. The preset duration can be, for example, 1 hour, 2 hours, or 4 hours. The processor's behavioral characteristics can be represented as Behav_curr = (Count_wake, Time_active), where Count_wake is the number of wake-ups within the preset duration, and Time_active is the cumulative runtime within the preset duration.

[0028] Of course, in some other implementations, the behavioral characteristics of the processor at the current wake-up time may not include the current wake-up time, but may be statistically analyzed over a period of time prior to the current wake-up time.

[0029] The order of steps S100, S200 and S300 is not restricted during execution; they can be executed simultaneously or in stages.

[0030] S400: Determine the equivalent temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence, voltage sequence, and processor behavior characteristics.

[0031] Specifically, equivalent temperature refers to a parameter that does not directly rely on physical temperature sensors but indirectly characterizes the thermal state of a crystal oscillator through other physical parameters. The time skew sequence characterizes the crystal oscillator's shift over time; this feature directly reflects the crystal oscillator's frequency shift and is one of the key parameters for assessing the crystal oscillator's temperature. The voltage sequence characterizes the voltage changes of the target circuit over time; voltage changes are usually accompanied by temperature changes in the overall embedded system, thus indirectly reflecting the crystal oscillator's temperature. Generally, higher temperatures correspond to lower voltages. The processor's behavioral characteristics characterize the processor's workload changes over time; the more times the processor is woken up and the longer its cumulative runtime, the more significant the temperature increase for the crystal oscillator. Therefore, combining these three factors allows for the indirect assessment of the crystal oscillator's equivalent temperature at the current wake-up time, eliminating the need for physical temperature sensors and enabling temperature prediction using existing components within the embedded system.

[0032] In steps S100, S200 and S300 above, the time period for acquiring the data before the current wake-up time can be the same or different. When they are different, the duration can be determined based on the degree of influence of the three factors on the temperature.

[0033] S500: Based on the equivalent temperature of the crystal oscillator at the current wake-up time, a matched test strategy is used to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected.

[0034] Specifically, the crystal oscillator is electrically connected to a portion of a capacitor array. By selecting capacitors with different capacitance values ​​to form the array, the crystal oscillator will output different frequencies when connected to different capacitors. Generally, only connecting to a subset of the capacitors will meet the required frequency. However, as temperature changes occur, the connected capacitors need to be adjusted to ensure time accuracy. Failure to adjust the capacitors will result in timing errors. Therefore, this step requires testing with different test capacitors to determine which capacitor should ultimately be connected to the crystal oscillator. It's important to note that the test capacitors are specifically selected from the capacitor array, not all capacitors in the array. This improves testing efficiency. Furthermore, when testing the target test frequency of the crystal oscillator with multiple different test capacitors, several different testing strategies can be selected. Different testing strategies involve different selections of test capacitors; that is, different test capacitors are selected for testing at different equivalent temperatures. This targeted testing method, rather than a generalized test, improves testing efficiency to a certain extent.

[0035] S600: Based on the target test frequency of the crystal oscillator when multiple different test capacitors are connected, determine the final target capacitor to be connected to the crystal oscillator among the multiple different test capacitors.

[0036] Specifically, by comparing and analyzing the target test frequencies of the crystal oscillator with multiple different test capacitors connected, the test capacitor that enables the optimal time calibration of the crystal oscillator is selected as the target capacitor, and the crystal oscillator is then connected to the target capacitor.

[0037] As can be seen from the above process, this application obtains data on three factors that affect the crystal oscillator temperature: the time deviation sequence, the voltage sequence, and the processor's behavioral characteristics. Then, it combines these three factors to perform an equivalent temperature evaluation of the crystal oscillator, obtaining the equivalent temperature of the crystal oscillator at the current wake-up time. By matching different test strategies with the equivalent temperature, different test capacitors can be connected to the crystal oscillator. Furthermore, based on multiple target test frequencies obtained from the test, the optimal test capacitor is selected as the target capacitor. The entire process does not rely on a temperature sensor, thus saving hardware costs and achieving crystal oscillator tuning, completing frequency self-calibration.

[0038] In one embodiment, see Figure 2 , Figure 2 yes Figure 1 A flowchart illustrating one embodiment of step S400, wherein step S400 includes: S410: Determine the first temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence.

[0039] Specifically, the time deviation sequence is an important indicator of the temperature change of the crystal oscillator. Therefore, the time deviation sequence can be processed and mapped to a first temperature. This mapping relationship can be calibrated experimentally to establish the correspondence between the time deviation and the first temperature.

[0040] S420: Determine the second temperature of the crystal oscillator at the current wake-up time based on the voltage sequence.

[0041] Specifically, voltage changes cause temperature changes in the crystal oscillator. Therefore, the voltage sequence can be processed and mapped to a second temperature. This mapping relationship can be established experimentally to establish the correspondence between voltage and the second temperature.

[0042] S430: Determines the third temperature of the crystal oscillator at the current wake-up time based on the processor's behavior characteristics.

[0043] Specifically, the behavior of the processor causes temperature changes in the crystal oscillator. Therefore, the behavior of the processor can be mapped to a third temperature. This mapping relationship can be established through experimental calibration, thereby establishing the correspondence between the behavior of the processor and the third temperature.

[0044] S440: Determine the equivalent temperature of the crystal oscillator at the current moment based on the first temperature, the second temperature, and the third temperature.

[0045] Specifically, the first temperature, the second temperature, and the third temperature are equivalent temperature components corresponding to different factors. The equivalent temperature of the crystal oscillator at the current moment is determined by comprehensively evaluating the first temperature, the second temperature, and the third temperature.

[0046] In one embodiment, see Figure 3 , Figure 3 yes Figure 2 A flowchart illustrating one embodiment of step S410, wherein step S410 includes: S411: Perform linear fitting on the time deviation sequence and determine the slope of the fitted line.

[0047] Specifically: based on the test time and the corresponding time deviations in the time deviation sequence, a straight line is fitted using the linear least squares method, and then the slope of the straight line is calculated.

[0048] S412: Determine the frequency drift slope of the crystal oscillator at the current moment based on the slope and the preset period.

[0049] Specifically: Dividing the slope by the preset period yields the frequency change per unit period, i.e., the frequency drift slope. This frequency drift slope is strongly correlated with the temperature drift characteristics of the crystal oscillator, and the frequency of the crystal oscillator typically has a negative temperature coefficient. If the frequency drift slope is negative, it indicates that the environment is cooling down; conversely, it indicates that the environment is heating up.

[0050] S413: Determine the first temperature of the crystal oscillator at the current wake-up time based on the frequency drift slope and the mapping function between the frequency drift slope and temperature.

[0051] Specifically: the mapping function between the frequency drift slope and temperature was calibrated by previous experiments. This mapping function can be a linear or piecewise linear function. By substituting the frequency drift slope into this function, the corresponding first temperature can be calculated.

[0052] The specific formula for determining the first temperature is as follows: T1 = Normalize(K_freq), where Normalize(K_freq) is a temperature function obtained by linearly or piecewise linearly mapping the frequency drift slope K_freq, covering the typical operating temperature range of -20°C to 60°C.

[0053] K_freq = slope / T_sleep, where slope is the slope obtained by linear fitting of the time deviation sequence, and T_sleep is the preset period.

[0054] Of course, the mapping function between the frequency drift slope and temperature can also incorporate a nonlinear compensation term to adapt to the asymmetric temperature drift characteristics of the crystal oscillator in high and low temperature regions, further improving the mapping accuracy and generalization ability. This nonlinear compensation term is dynamically updated based on the batch characteristics and aging trends of the crystal oscillator, ensuring the accuracy and consistency of the first temperature inference during long-term operation.

[0055] In one embodiment, see Figure 4 , Figure 4 yes Figure 2 A flowchart illustrating one embodiment of step S420, wherein step S420 includes: S421: Determine the target voltage based on the voltage sequence.

[0056] Specifically, data processing of the voltage sequence can involve calculating the average voltage of at least a portion of the voltage sequence and using this average voltage as the target voltage. This portion can be a part of the voltage sequence closest to the current wake-up time.

[0057] S422: Determine the second temperature of the crystal oscillator at the current wake-up time based on the target voltage and the mapping table between the target voltage and the second temperature.

[0058] Specifically, the mapping table between the target voltage and the second temperature is calibrated by previous experiments. Of course, there can be multiple mapping tables between the target voltage and the second temperature, each corresponding to a different battery state of charge range. Thus, the most matching mapping table is dynamically selected based on the current battery state of charge. The corresponding temperature found in the mapping table is the second temperature. Alternatively, the second temperature can be obtained by subtracting a reference temperature from the current temperature.

[0059] In one embodiment, see Figure 5 , Figure 5 yes Figure 2 A flowchart illustrating one embodiment of step S430, wherein step S430 includes: S431: Determine the processor's working type based on the number of times the processor wakes up and the cumulative runtime within a preset time period before the current wake-up time; wherein the working type includes at least two of deep sleep, intermittent work, and continuous activity.

[0060] Specifically, based on the number of times the processor wakes up and the cumulative runtime within a preset time before the current wake-up time, the processor's working type can be divided into three types: deep sleep corresponds to extremely low wake-up frequency and near-zero active duration; intermittent work is characterized by a moderate number of wake-ups and scattered short-term operation; and continuous activity is characterized by high-frequency wake-ups and a high proportion of cumulative running time.

[0061] S432: Determine the third temperature of the crystal oscillator at the current wake-up time based on the operating type.

[0062] Specifically, each work type has a preset self-heating temperature rise compensation value, i.e., the third temperature. It should be understood that the third temperature corresponding to the three work types of deep sleep, intermittent work and continuous activity increases in sequence, for example, it can be 0℃, +1.2℃ and +2.5℃ respectively; this compensation value has been measured and calibrated.

[0063] In one embodiment, see Figure 6 , Figure 6 yes Figure 2 A flowchart illustrating one embodiment of step S440, wherein step S440 includes: S441: The first temperature, the second temperature, and the third temperature are weighted and summed to obtain the first sum value.

[0064] Specifically, for the three temperatures corresponding to different factors, different weights are assigned to reflect their credibility and physical relevance: the first temperature (based on frequency drift estimation) has the highest weight, the second temperature (voltage-temperature relationship) has a relatively high weight in battery-powered devices, and the third temperature (active temperature rise compensation) has a relatively low weight as a dynamic correction term; the weighting coefficients are stored in memory after regression training with a large amount of measured data.

[0065] S442: Determine the equivalent temperature of the crystal oscillator at the current moment based on the first sum and the bias term.

[0066] Specifically, the bias term is a preset system-level calibration bias used to eliminate batch-specific process deviations and common errors from environmental temperature drift. The sum of the first value plus the bias term yields the current actual equivalent temperature of the crystal oscillator, a value that no longer depends on external sensors. It integrates a triple sensing dimension of frequency domain deduction, electrochemical characteristics, and thermodynamic dynamics; it is both a mapping of ambient temperature and a real-time representation of the coupling evolution of the crystal oscillator's own thermal inertia and system load.

[0067] The specific formula for determining the equivalent temperature of the crystal oscillator at the current moment is: T_eq = W1×T1+ W2×T2+ W3×T3+ B, where W1, W2, and W3 are the weighting coefficients for the first, second, and third temperatures, respectively, and B is the bias term.

[0068] In one embodiment, see Figure 7 , Figure 7 yes Figure 1 A flowchart illustrating one embodiment of step S500, wherein step S500 includes: S510: Determine the similarity between the equivalent temperature of the crystal oscillator at the current wake-up time and the equivalent temperature at the previous wake-up time.

[0069] Specifically, similarity is used to characterize the similarity between the equivalent temperature at the current wake-up time and the equivalent temperature at the previous wake-up time. For example, a similarity of 1 indicates that the two are completely equal. The closer the similarity is to 1, the more gradual the temperature change and the more stable the thermal state of the crystal oscillator. A similarity of 0 indicates a drastic temperature change, and the crystal oscillator needs frequency calibration. The similarity calculation formula is S = 1 - |T_eq_current - T_eq_previous| / ΔT_range, where ΔT_range is the maximum temperature change threshold that the system can tolerate (e.g., 5℃), T_eq_current is the equivalent temperature at the current wake-up time, and T_eq_previous is the equivalent temperature at the previous wake-up time.

[0070] S520: Determine the matching test strategy based on the confidence interval of the similarity; where different test strategies correspond to multiple different test capacitors in different test sequences.

[0071] Specifically, different testing strategies should be used for similarity scores in different confidence intervals, rather than using a fixed testing capacitor, in order to achieve the optimal balance between accuracy and efficiency.

[0072] S530: Uses a matching test strategy to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected.

[0073] Specifically, an adaptive scanning test sequence is used to dynamically load capacitance values ​​and capture the frequency response in real time.

[0074] The above steps use a similarity-adaptive scanning test sequence, which, unlike a fixed test sequence, can significantly improve testing efficiency and shorten frequency calibration time.

[0075] The confidence intervals of this application include a first confidence interval, a second confidence interval, and a third confidence interval; the testing strategies include a first testing strategy, a second testing strategy, and a third testing strategy; the first confidence interval corresponds to the first testing strategy, the second confidence interval corresponds to the second testing strategy, and the third confidence interval corresponds to the third testing strategy.

[0076] In one embodiment, step S530 includes: In response to the similarity being within the first confidence interval, the target test frequency of the crystal oscillator with multiple different test capacitors is determined using the first test strategy. Wherein, the lower limit of the first confidence interval is greater than or equal to the first confidence level. Under the first test strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is determined as the first initialization capacitor, and a first test sequence is constructed with the first initialization capacitor as the center, and the difference between the first initialization capacitor and the first initialization capacitor does not exceed the first capacitor value and the first test capacitor increases sequentially with the first step value.

[0077] Specifically, the lower limit of the first confidence interval is greater than or equal to the first confidence level. The first confidence interval is a high confidence interval. At this time, the thermal state of the crystal oscillator is relatively stable. In the first test strategy, the first initialization capacitor directly uses the target capacitor corresponding to the equivalent temperature at the previous wake-up time, and verifies the fine-tuning quickly in a narrow interval with a very small step. This avoids the redundant time consumption of global scanning and ensures the calibration accuracy.

[0078] In one embodiment, step S530 includes: In response to the similarity falling within the second confidence interval, a second testing strategy is adopted to test the target test frequency of the crystal oscillator with multiple different test capacitors connected. The upper limit of the second confidence interval is less than or equal to the first confidence level and greater than or equal to the second confidence level. Under the second testing strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is first determined as the second initialization capacitor. A second test sequence is constructed, centered on the second initialization capacitor and consisting of multiple test capacitors whose values ​​do not exceed the difference between the two initialization capacitors and increase sequentially with a second step value. When testing the test capacitors in the second test sequence, the rate of change of the target test frequency corresponding to adjacent test capacitors is determined. If the target frequency is within the second confidence interval, the target test frequency is determined. If the rate of change of the target test frequency exceeds the second preset threshold, the test capacitor corresponding to the rate of change of the target test frequency exceeding the second preset threshold is determined as the third initialization capacitor. A third test sequence is constructed with the third initialization capacitor as the center, and multiple test capacitors whose values ​​do not exceed the difference of the third initialization capacitor and are sequentially increased by a third step value. Among them, the range length of the capacitance value of the test capacitor in the second test sequence is greater than the range length of the capacitance value of the test capacitor in the first test sequence, the range length of the capacitance value of the test capacitor in the second test sequence is greater than the range length of the capacitance value of the test capacitor in the third test sequence, the second step value is greater than the first step value, and the second step value is greater than the third step value.

[0079] Specifically, the upper limit of the second confidence interval is less than or equal to the first confidence level, and greater than or equal to the second confidence level. The second confidence interval is a medium confidence interval. At this point, the thermal stability of the crystal oscillator is generally poor, and both exploration efficiency and model accuracy need to be considered. In the second test strategy, the second initialization capacitor directly uses the target capacitor corresponding to the equivalent temperature at the previous wake-up time, but the exploration range is larger than that in the first test strategy, and the scanning accuracy is reduced. That is, the difference between the second and first capacitors is greater than the difference between the first and second capacitors, and the second step value is greater than the first step value, which can quickly locate the frequency inflection point within a limited time. When a sudden change in the rate of change of the target test frequency is detected, the third test strategy is triggered, which narrows the scanning range and increases the step accuracy. Local high-resolution focusing is achieved by making the difference between the third and second capacitors less than the difference between the second and third step values ​​less than the second step value, so as to accurately capture the region on the response curve where the frequency is most sensitive to the capacitor. This strategy adopts a two-stage dynamic focusing mechanism: the first stage uses coarse-grained scanning to quickly locate the frequency response inflection point, and the second stage adaptively shrinks the scanning window and densifies the sampling density according to the inflection point position, improving the local scanning accuracy while ensuring the convergence speed. This achieves the optimization of intelligent switching between "exploration and focusing".

[0080] The formula for calculating the rate of change of the target test frequency is as follows: K i = |(F i - F i 1) / (C i - C i-1 )|, where Ki is the target test frequency change rate corresponding to the i-th test capacitor point, and Fi and Fi 1 represents the target test frequency obtained from two consecutive measurements, Ci and Ci', respectively. 1 represents the corresponding test capacitance. This formula quantifies the frequency response intensity caused by a small change in capacitance.

[0081] In one embodiment, step S530 includes: In response to the similarity being within the third confidence interval, a third testing strategy is adopted to test the target test frequency of the crystal oscillator with multiple different test capacitors connected. The upper limit of the third confidence interval is less than or equal to the second confidence level. Under the third testing strategy, the capacitor corresponding to the center value among all capacitor values ​​is determined as the fourth initialization capacitor, and a fourth test sequence of test capacitors covering the length of the capacitance value range of all capacitors is constructed. In the fourth test sequence, the capacitance difference between adjacent test capacitors within the preset range is less than the capacitance difference between adjacent test capacitors outside the preset range.

[0082] Specifically, if the upper limit of the third confidence interval is less than or equal to the second confidence level, the third confidence interval is a low confidence interval. At this point, the thermal stability of the crystal oscillator is very poor, and the historical data has low reference value. It is necessary to completely abandon the dependence on the historical best capacitor and instead adopt the "full-range wide-area scan" strategy. The capacitor corresponding to the center value of the capacitor array is used as the fourth initial capacitor to construct a fourth test sequence covering the entire range. In addition, the density of test capacitors is increased in the preset nonlinear sensitive area to achieve a non-uniform sampling distribution, thereby efficiently reconstructing the global characteristics of the crystal oscillator capacitor-frequency response curve with a limited number of scan points.

[0083] In one application scenario, the full range of the capacitor array is 0-20pF, with a first confidence interval greater than or equal to 0.7, a second confidence interval between 0.3 and 0.7, and a third confidence interval less than 0.3. For example, under the first testing strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is used as the first initialization capacitor, and 11 high-density scans are performed in 0.1pF steps within a narrow window of ±1.5pF. Under the second testing strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is used as the second initialization capacitor, and the process is performed in two stages within a wide window of ±5pF: the first stage completes 21 coarse scans in 0.5pF steps to identify monotonic intervals and extreme trends; the second stage locks the sub-interval with the steepest frequency response and performs local high-density verification in 0.1pF steps, balancing efficiency and accuracy. The third testing strategy uses 10pF as the center value and deploys 31 non-uniformly distributed test points in the full range of 0–20pF: 11 points each in the 0–5pF and 15–20pF intervals, and only 21 points in the 5–15pF interval. Furthermore, the test points are densified to 9 points each in the two typical nonlinear sensitive areas of 5–10pF and 10–15pF to ensure that key inflection points are fully captured.

[0084] Of course, in some other implementations, the range of confidence intervals can be other than that, and the number of confidence intervals can be increased or decreased according to the actual situation. This application does not limit this.

[0085] In one embodiment, see Figure 8 , Figure 8 yes Figure 7 A flowchart illustrating one embodiment of step S530, wherein step S530 includes: S531: For each test capacitor in the test sequence, set the test capacitor to be connected to the crystal oscillator and execute the first waiting period.

[0086] Specifically, according to the test sequence, the test capacitors are connected to the crystal oscillator one by one. Specifically, the test capacitors are written into the register, and the crystal oscillator is waited for the first period of time (e.g., greater than or equal to 20ms) to ensure that it enters a steady-state oscillation.

[0087] S532: Obtain the test frequency corresponding to the test capacitor at multiple different times, and determine the target test frequency.

[0088] Specifically, considering that a test frequency tested only once may have occasional interference that could affect the accuracy of calibration, the target test frequency is obtained after removing possible outliers by acquiring the test frequencies corresponding to the test capacitors at multiple time points and processing the data.

[0089] The specific calculation process for the target test frequency is as follows: First, collect test times t[0] to t[M] for M consecutive cycles (e.g., 5 cycles), and then calculate the single frequency F_single = (M-1) / (t[M] - t[0]). Repeat this acquisition-calculation process N times (e.g., 3 times) to obtain a set of frequency samples {F1, F2, F3}. Perform noise filtering on the frequency samples {F1, F2, F3} and take the median as the final target test frequency F_i of the test capacitor C_i. Finally, output the data tuple (C_i, F_i), which is used for subsequent modeling and optimization.

[0090] In one embodiment, see Figure 9 , Figure 9 yes Figure 1 A flowchart illustrating one embodiment of step S600, wherein step S600 includes: S610: Determine the first functional relationship based on all target test frequencies and corresponding test capacitors.

[0091] Specifically, curve fitting is performed on all target test frequencies and their corresponding test capacitances (i.e., data tuples (C_i, F_i)). For example, cubic spline interpolation or piecewise polynomial fitting can be used to construct a smooth and continuous first functional relationship of capacitance-frequency response, F = f(C), from the discrete test data. This first functional relationship can be used to predict frequency values ​​with high accuracy at capacitance points that are not directly measured.

[0092] S620: Calculate the calculation frequency corresponding to each of the multiple dummy capacitors using the first functional relationship; wherein, the multiple dummy capacitors are increased sequentially with the fourth step value.

[0093] Specifically, the fourth step value can be much smaller than the minimum adjustment step of the capacitor array. For example, the minimum step of the capacitor array itself is 0.05pF, while the fourth step value can be set to 0.01pF. Within the effective adjustment range of the capacitor, a high-density dummy capacitor sequence is generated at intervals of 0.01pF, and the corresponding calculation frequency is calculated by substituting it into the first function relationship, thereby outputting a series of calculation frequencies corresponding to the dummy capacitors. This result includes both measured and unmeasured values.

[0094] S630: If the absolute value of the calculated frequency deviation corresponding to multiple adjacent dummy capacitors is less than the third preset threshold, then the dummy capacitor corresponding to the center value of the capacitance range formed by the multiple adjacent dummy capacitors is determined as the target capacitor; wherein, the calculated frequency deviation is equal to the absolute value of the difference between the calculated frequency and the reference frequency.

[0095] Specifically, the frequency deviation is first determined, and the absolute value of the difference between the calculated frequency and the reference frequency is taken as the frequency deviation. Then, the frequency deviations corresponding to all dummy capacitors are traversed, and K consecutive intervals (e.g., K=5) with deviations less than a third preset threshold are selected. This interval is taken as a minimum value region, and the capacitor closest to the midpoint is the optimal capacitor, which can be used as the target capacitor. If the dummy capacitor corresponding to the midpoint is also a capacitor that the capacitor array can provide, then the capacitor corresponding to the midpoint is directly used as the target capacitor. If the dummy capacitor corresponding to the midpoint is not a capacitor that the capacitor array can provide, then the capacitor that the capacitor array closest to the midpoint can provide is used as the target capacitor. It can be seen that in this implementation, by modeling and optimizing after testing different test strategies in the above step S500, the required test time can be reduced and the target capacitor positioning accuracy can be significantly improved. At the same time, this optimization process is entirely based on the measured response curve and the high-density dummy capacitor deduction.

[0096] In one embodiment, see Figure 10 , Figure 10 yes Figure 1 A flowchart of an embodiment prior to step S600, which further includes the following steps before step S500: S450: Determine whether the triggering conditions are met, at least based on the equivalent temperature.

[0097] Specifically, a large change in equivalent temperature satisfies the triggering condition, while a small change in equivalent temperature does not.

[0098] S460: If the triggering condition is met, then execute the step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected, based on the equivalent temperature of the crystal oscillator at the current wake-up time and using a matching test strategy.

[0099] Specifically, if the triggering condition is met, step S500 is executed; otherwise, subsequent steps are skipped, and the system directly enters a low-power sleep mode. This step allows the crystal oscillator to be calibrated without thermal stability, and to actively intervene in calibration when thermal instability occurs. This avoids the power waste caused by redundant operations and ensures timely calibration during the critical window period when temperature changes cause frequency drift.

[0100] In one embodiment, the triggering condition includes the absolute value of the difference between the equivalent temperature at the current wake-up time and the equivalent temperature at the previous wake-up time exceeding a temperature difference threshold, and the duration being not less than a first duration.

[0101] Specifically, this involves two aspects. First, the absolute value of the difference between the equivalent temperature at the current wake-up time and the equivalent temperature at the previous wake-up time must exceed the temperature difference threshold. This means that the crystal oscillator's temperature fluctuation has been relatively drastic recently, indicating a significant frequency drift. Second, this temperature difference must persist for at least a first duration to eliminate transient noise interference and ensure that the triggered process is a real and observable temperature drift. These two conditions effectively distinguish between random disturbances and deterministic temperature changes, providing a reliable basis for calibration decisions.

[0102] In one embodiment, the triggering conditions also include timed wake-up and / or communication wake-up of the processor.

[0103] Specifically, timed wake-up utilizes the alarm function in the real-time clock to periodically wake the user at fixed intervals (e.g., 7 days), ensuring that frequency deviations caused by prolonged operation without adjustments do not accumulate beyond limits. Communication wake-up utilizes the opportunity of establishing a connection with the external world to perform a "health check." After receiving a valid timestamp at the General Attribute Protocol (GATT) layer of the Bluetooth (BLE) protocol stack or the Network Time Protocol (NTP) client of a Wi-Fi network, it compares the external time with the local real-time clock. If the time deviation exceeds the limit, calibration is triggered. This dual-track wake-up mechanism complements temperature drift triggering. Timed wake-up provides long-term stability assurance, communication wake-up receives external time and performs self-checks, while temperature drift triggering focuses on responding to sudden environmental changes. Together, these three mechanisms form a comprehensive triggering network covering time, communication, and physical status, ensuring that calibration achieves an optimal balance between power consumption, accuracy, and timeliness.

[0104] Furthermore, if the wake-up time when the previous trigger condition took effect is no more than the cooldown time before the current wake-up time, then the current wake-up time does not meet the trigger condition.

[0105] Specifically, for example, the cooling time is set to 1 hour, and the processor automatically starts a countdown after each adjustment is completed. If any trigger condition is met again before the countdown ends, the trigger flag at the current wake-up time will be masked to avoid the negative impact of high-frequency repeated calibration on system stability and power consumption.

[0106] In one embodiment, prior to step S500, the method further includes: The control system enters a tuning mode; the tuning mode includes at least the processor entering a sleep mode.

[0107] Specifically, the tuning mode setting is mainly used to enable the crystal oscillator frequency to self-calibrate in an interference-free environment. It can temporarily put the processor into sleep mode to avoid the processor handling high load work, which would cause the local temperature to become too high and affect the crystal oscillator test.

[0108] The specific steps for the aforementioned control system to enter the adjustment mode include: S11: Silent configuration of peripherals and interfaces.

[0109] Specifically, the first step is to disable digital noise sources: By configuring the peripheral clock enable register, the clocks of all high-frequency digital peripherals unrelated to frequency measurement are disabled, including but not limited to the clocks of the LCD controller, Universal Serial Bus (USB), Direct Memory Access (DMA), and all unused communication interfaces. This fundamentally eliminates synchronous digital noise generated by the internal switching circuits of these modules. The second step is to configure general-purpose input / output (GPIO) pins to analog mode: All GPIO pins not used for critical signals (such as crystal oscillator pins and debug interfaces) are configured to "analog input" mode via their mode registers. In this mode, the internal pull-up / pull-down resistors and Schmitt triggers of the GPIO pins are disabled, and the pins present high impedance, avoiding random switching current noise caused by floating inputs.

[0110] S12: Power supply switches to regulated state.

[0111] Specifically, the first power switching core power supply architecture: For processors using a switching power supply to power the digital core, the core domain power supply is forced to switch to the internal low-dropout linear regulator mode by configuring the power control register. Although this slightly increases static power consumption, it completely eliminates the ripple noise of the switching power supply in the MHz frequency range, which is a major factor affecting crystal oscillator phase noise. The second isolated analog power domain: Ensures that the analog power pins supplying power to the crystal oscillator and analog sections are connected via independent circuit board traces, and enables the relevant analog power regulators in software.

[0112] S13: Temporarily set up a high-precision measurement clock.

[0113] Specifically, the first step is to select the optimal clock source: the clock source for the timer used for frequency acquisition is configured via a register to be the output of the main phase-locked loop (MLL). The MLL's reference source should be an external high-speed crystal oscillator (HSE) rather than an internal RC oscillator (HSI) to obtain optimal long-term frequency stability and minimal jitter. The second step is to stabilize the clock path: before switching, ensure the MLL is locked and operating stably. During tuning, freeze the system clock configuration and prohibit any operations that might cause clock switching or changes in the division ratio.

[0114] S14: The processor enters sleep mode.

[0115] Specifically, the first step is to enter a controlled standby state: After completing all the above hardware configurations, the wireless network wait interrupt instruction is executed, causing the processor to enter sleep mode. In this mode, the processor suspends execution, but all peripherals with clocks enabled (such as timers used for real-time clock capture) continue to operate normally. This ensures that the frequency capture process is completed automatically by hardware, completely unaffected by unpredictable software task scheduling and memory access activities, thereby achieving the highest timestamp consistency.

[0116] The above configuration operations are completed by sequentially writing to the registers. The typical time from triggering to entering a stable sleep state is less than 5ms. This time mainly depends on the main phase-locked loop locking time and the low-dropout linear regulator settling time, which is much shorter than the crystal oscillator's own thermal settling time constant (usually >50ms), and therefore does not introduce additional delay.

[0117] In one embodiment, after step S600 described above, the method further includes: The control system has exited adjustment mode.

[0118] The steps for the control system to exit the tuning mode include: The processor exits sleep mode; the temporary high-precision measurement clock is canceled; the power supply returns to normal; and the silent configuration of peripherals and interfaces is canceled.

[0119] The above steps are the reverse configuration of steps S11 to S14. After the target test frequency measurement is completed, the timer captures the interrupt to wake up the processor. The interrupt service routine first records the key data, and then executes the above reverse configuration steps. The specific content of the execution is the same as above, and will not be repeated.

[0120] In one embodiment, see Figure 11 , Figure 11 yes Figure 1 A flowchart illustrating an embodiment following step S600, wherein the method further includes: S710: Obtain a first external reference time provided by an external time source at a first moment, a first local time provided by an internal real-time clock, and a first network delay time; and, at a second moment, a second external reference time provided by an external time source, a second local time provided by an internal real-time clock, and a second network delay time.

[0121] Specifically, the external time source needs to have high confidence—that is, meet the triple conditions of source credibility, path credibility, and time credibility—before triggering subsequent steps. Otherwise, the system will ignore the time source and maintain the current time. Source credibility means that the time source has been certified by an authoritative organization, such as a certified network time protocol server, satellite signals from a global navigation satellite system, or a cellular network synchronized with national standard time. Path credibility requires that transmission delays can be accurately modeled and compensated. For example, for network time protocols, a complete protocol interaction must be successfully completed and the round-trip delay obtained; for Bluetooth, communication with a verified paired device within a very short distance is required. Time credibility emphasizes that the timestamp must carry complete UTC metadata (including leap second identification and time zone offset). Furthermore, since the first local time is provided by the internal real-time clock at the first moment, but the first external reference time arriving at the local time usually has a network delay, the first network delay time needs to be obtained. Similarly, the second network delay time needs to be obtained for the second moment as well.

[0122] S720: Determine a first time when the first external reference time arrives at the local location based on a first external reference time and a first network delay time; and determine a second time when the second external reference time arrives at the local location based on a second external reference time and a second network delay time.

[0123] Specifically, the first time is the sum of the first external reference time and the first network delay time, and the first time is the time after calibration of the first external reference time; the second time is the sum of the second external reference time and the second network delay time, and the second time is the time after calibration of the second external reference time. Therefore, if the local time has no deviation, it should be equal to the calibrated time.

[0124] S730: Determine the first frequency deviation rate between the first time point and the second time point based on the first local time, the second local time, the first time point, and the second time point.

[0125] Specifically, the time difference between two moments is calculated based on the above multiple times, and then the first frequency deviation rate between the two moments is calculated based on the time difference. The first frequency deviation rate is the frequency error observation value, which smooths out short-term noise and directly reflects the systematic deviation of the crystal oscillator between the two moments.

[0126] In one embodiment, the formula for calculating the first frequency deviation rate is as follows: ΔT_true = (t_ext_corrected_1 - t_ext_corrected_0).

[0127] ΔT_local = (t_local_1 - t_local_0).

[0128] F_error_avg_ppm = 10 6 × (ΔT_local ΔT_true) / ΔT_.

[0129] Where t_ext_corrected_1 is the first time, t_ext_corrected_0 is the second time, t_local_1 is the first local time, and t_local_0 is the second local time; ΔT_true is the external standard time difference, ΔT_local is the time difference of the local real-time clock count; and F_error_avg_ppm is the first frequency deviation rate, in ppm.

[0130] S740: Obtain all equivalent temperatures between the first and second time points.

[0131] Specifically, it can be to obtain a sequence of all equivalent temperatures between the first and second time points, or it can be to obtain the average value of all equivalent temperatures.

[0132] S750: Using all equivalent temperatures between the first and second time points and the first frequency deviation rate between the first and second time points as supervised learning samples, update the weights and biases of the first, second, and third temperatures through a learning algorithm.

[0133] Specifically, using the equivalent temperature and the first frequency deviation rate as supervised learning samples, the weights and biases in steps S441 and S442 are updated using learning algorithms such as Recursive Least Squares (RLS) or Stochastic Gradient Descent (SGD). This allows the frequency drift trend included in the model's predicted equivalent temperature to be more consistent with the actually observed first frequency deviation rate. It can be seen that this step, based on the self-calibration of the crystal oscillator frequency, endows the self-calibration of the crystal oscillator frequency with "cognitive evolution" capability (i.e., self-learning capability). Each external time feedback is transformed into precise tuning of model parameters, achieving internal and external dual-loop verification. Thus, even without a physical temperature sensor, the accuracy of equivalent temperature inference and the robustness of frequency calibration are continuously improved.

[0134] In one embodiment, prior to step S730, the method further includes: If the absolute value of the difference between the first time and the first local time is greater than the first preset threshold, then the first local time will be corrected to the first time.

[0135] Specifically, if the absolute value of the difference between the first time and the first local time exceeds the first preset threshold (e.g., 10 seconds), the first local time needs to be directly corrected to the first time to avoid the local time deviating too much from the real time, without waiting for the adjustment result.

[0136] In one embodiment, prior to step S740, the method further includes: Obtain the first frequency deviation rate from historical data. If there are consecutive preset number of positive first frequency deviation rates, or consecutive preset number of negative first frequency deviation rates, then generate an early warning log.

[0137] Specifically, the stored multiple first frequency deviation rates are analyzed to determine the changing trend of the first frequency deviation rate. If there are multiple consecutive increases or decreases in the first frequency deviation rate in the same direction, and the change amplitude exceeds the second preset threshold, it is determined that the crystal oscillator temperature drift trend is significant and has not been fully compensated by internal adjustment. This triggers the crystal oscillator aging early warning mechanism and generates an early warning log. At this time, the adjustment mode can be triggered to calibrate the crystal oscillator frequency.

[0138] In one embodiment, see Figure 12 , Figure 12 yes Figure 1 A flowchart illustrating another embodiment following step S600, further comprising: S810: Store at least the equivalent temperature and the corresponding target capacitance.

[0139] Specifically, the equivalent temperature and the corresponding target capacitance are stored, which can be used for subsequent model training and optimization of the temperature-capacitance mapping relationship. In addition, key parameters such as adjustment time, test frequency, test strategy and similarity can be stored to build an enhanced knowledge record. Furthermore, an "atomic submission" mechanism can be used to write the knowledge to a circular knowledge base in memory, ensuring that the integrity of the knowledge base will not be destroyed by any unexpected power failure.

[0140] S820: Periodically analyzes multiple accumulated equivalent temperatures and corresponding target capacitances through a learning algorithm to establish a temperature and capacitance prediction model; the prediction model is used to optimize the test strategy.

[0141] Specifically, the learning algorithm is run periodically (e.g., every 10 records) to analyze the equivalent temperature and corresponding target capacitance. Linear regression is used to fit the relationship between the two, generating a lightweight lookup table or parameterized model. This model then feeds back into the testing strategy of step S500. This method dynamically optimizes the scan step size and range, and through self-learning, the accuracy and precision of the crystal oscillator's self-calibration continuously improve over time.

[0142] This application provides an application scenario, see below. Figure 13 , Figure 13 This is a flowchart illustrating the method of this application in an application scenario.

[0143] Step S1: If any one of the following conditions is met—timed wake-up, equivalent temperature meeting the trigger condition, or communication wake-up—execute the next step.

[0144] Step S2: Control the entry into tuning mode to reduce the impact on the crystal oscillator frequency testing process.

[0145] Step S3: Determine the equivalent temperature based on the fusion of time deviation sequence, voltage sequence and processor behavior characteristics.

[0146] Step S4: Select a matching test strategy based on equivalent temperature to reduce scan time and improve the accuracy of initial value preset.

[0147] Step S5: Perform capacitance scan and frequency measurement under the selected strategy.

[0148] Step S6: Fit the capacitance-frequency curve based on the measurement data and select the optimal capacitance as the target capacitance.

[0149] Step S7: Write parameters such as equivalent temperature and target capacitance into the knowledge base, and at the same time optimize the test strategy of step S4 through model training.

[0150] Step S8: Determine whether the high-confidence external feedback condition is met based on the credibility of the external time source; if it is met, proceed to step S9 to obtain the external timestamp and calculate the systematic frequency deviation for updating the long-term aging compensation model; otherwise, end directly.

[0151] Step S9: Calculate the frequency deviation rate based on the time information provided by the external time source.

[0152] Step S10: Construct supervised samples by combining the calculated frequency deviation rate with the corresponding equivalent temperature, and optimize the weights and bias terms in the equivalent temperature model in step S3 through model training.

[0153] The specific process of each of the above steps has been described above and will not be repeated here.

[0154] This application also provides a crystal oscillator frequency self-calibration system, which includes a trigger condition detection module, a mode control module, a capacitor array, a crystal oscillator circuit, a frequency acquisition module, a data processing module, a non-volatile storage module, a real-time clock time management module, and a dual closed-loop verification module.

[0155] The input of the trigger condition detection module is connected to the real-time clock time management module, communication peripherals, and data processing module, and the output is connected to the mode control module. It is used to implement the function of step S1 and monitor three types of events: timing, communication wake-up, and temperature change inference.

[0156] The mode control module is interconnected with the data processing module, clock controller, and peripheral controller, and is responsible for coordinating peripheral shutdown, power switching, and clock source switching actions.

[0157] The capacitor array is configured by a register and connected to both ends of the crystal oscillator circuit to adjust the crystal load.

[0158] One end of the crystal oscillator circuit is grounded, and the other end is connected to XTAL_IN (the input pin of the crystal oscillator). The output is led out through XTAL_OUT (the output pin of the crystal oscillator). The crystal oscillator circuit includes an inverting amplifier, a feedback resistor, etc., to drive an external 32.768kHz crystal oscillator.

[0159] The frequency acquisition module receives input from the XTAL_OUT pin and outputs a timestamp to the data processing module. It uses a high-speed timer to capture the rising edge timestamp of the crystal oscillator output signal to achieve high-precision frequency resolution.

[0160] The data processing module communicates with the frequency acquisition module, compensation capacitor, and non-volatile memory module, and executes the logic of steps S3 to S7 to complete the equivalent temperature calculation, graded scanning, frequency calculation, and optimal value selection.

[0161] The non-volatile memory module stores the optimal capacitance value and adjustment log, and supports retention even after power loss.

[0162] The real-time clock management module works in conjunction with the clock source and the dual closed-loop verification module to provide a high-precision real-time clock function, supporting alarm clock interruption and NTP / PTP time synchronization.

[0163] The dual closed-loop verification module connects to a highly reliable external time source via a wireless or wired communication interface to complete the closed-loop verification from steps S8 to S10.

[0164] See Figure 14 , Figure 14 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. The electronic device 300 includes a processor 310 and a memory 320. The processor 310 is coupled to the memory 320. The memory 320 stores program data. The processor 310 executes the program data in the memory 320 to implement the steps in any of the above embodiments. The detailed steps can be found in the above embodiments and will not be repeated here.

[0165] Among them, electronic device 300 can be any device with algorithm capabilities, such as mobile phone, tablet computer, smartwatch, desktop computer or laptop computer, without any restrictions.

[0166] See Figure 15 , Figure 15This is a schematic diagram of one embodiment of the computer-readable storage medium of this application. The computer-readable storage medium 400 stores a computer program 410, which can be executed by a processor to implement the steps in any of the above methods. Detailed method steps can be found in the relevant content above, and will not be repeated here.

[0167] Specifically, the computer-readable storage medium 400 can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or a device that can store the computer program 410. Alternatively, it can be a server that stores the computer program 410, which can send the stored computer program 410 to other devices for execution, or it can run the stored computer program 410 itself.

[0168] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for self-calibrating crystal oscillator frequency, characterized in that, The method is applied to a processor that operates at the frequency provided by the crystal oscillator, and the processor switches between sleep mode and wake-up mode at a preset cycle. The method includes: Obtain a time deviation sequence, the time deviation sequence including the time deviation value of the processor at multiple wake-up times, the time deviation value of the processor at the wake-up time being equal to the difference between the test time and the theoretical time of the processor at the wake-up time; A voltage sequence is obtained, the voltage sequence including the supply voltage of the target circuit at multiple wake-up times, the target circuit being used to supply power to the processor; The behavior characteristics of the processor at the current wake-up time are obtained, and the behavior characteristics of the processor are related to the number of times the processor is woken up and the cumulative running time within a preset time before the current wake-up time. Based on the time deviation sequence, the voltage sequence, and the behavioral characteristics of the processor, the equivalent temperature of the crystal oscillator at the current wake-up time is determined; Based on the equivalent temperature of the crystal oscillator at the current wake-up time, a matching test strategy is used to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected. Based on the target test frequency of the crystal oscillator with multiple different test capacitors connected, and the multiple different test capacitors, the final target capacitor connected to the crystal oscillator is determined.

2. The method according to claim 1, characterized in that, The step of determining the equivalent temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence, the voltage sequence, and the behavioral characteristics of the processor includes: Based on the time deviation sequence, determine the first temperature of the crystal oscillator at the current wake-up time; Based on the voltage sequence, determine the second temperature of the crystal oscillator at the current wake-up time; Based on the behavior characteristics of the processor, determine the third temperature of the crystal oscillator at the current wake-up time; The equivalent temperature of the crystal oscillator at the current moment is determined based on the first temperature, the second temperature, and the third temperature.

3. The method according to claim 2, characterized in that, The step of determining the first temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence includes: The time deviation sequence is linearly fitted to determine the slope of the fitted line; The frequency drift slope of the crystal oscillator at the current moment is determined based on the slope and the preset period. The first temperature of the crystal oscillator at the current wake-up time is determined based on the frequency drift slope and the mapping function between the frequency drift slope and temperature.

4. The method according to claim 2, characterized in that, The step of determining the second temperature of the crystal oscillator at the current wake-up time based on the voltage sequence includes: Determine the target voltage based on the voltage sequence; The second temperature of the crystal oscillator at the current wake-up time is determined based on the target voltage and the mapping table between the target voltage and the second temperature.

5. The method according to claim 2, characterized in that, The step of determining the third temperature of the crystal oscillator at the current wake-up time based on the behavioral characteristics of the processor includes: The processor's operating type is determined based on the number of times the processor is woken up and the cumulative runtime within a preset time period before the current wake-up time; wherein the operating type includes at least two of deep sleep, intermittent work, and continuous activity; Based on the operating type, the third temperature of the crystal oscillator at the current wake-up time is determined.

6. The method according to claim 2, characterized in that, The step of determining the equivalent temperature of the crystal oscillator at the current moment based on the first temperature, the second temperature, and the third temperature includes: The first temperature, the second temperature, and the third temperature are weighted and summed to obtain the first sum value; The equivalent temperature of the crystal oscillator at the current moment is determined based on the first sum and the bias term.

7. The method according to claim 6, characterized in that, After the step of determining the target capacitor to be connected to the crystal oscillator based on the target test frequency and the multiple different test capacitors connected to the crystal oscillator, the method further includes: Acquire a first external reference time provided by an external time source at a first moment, a first local time provided by an internal real-time clock, and a first network delay time; and acquire a second external reference time provided by an external time source, a second local time provided by an internal real-time clock, and a second network delay time at a second moment. Based on the first external reference time and the first network delay time, a first time when the first external reference time arrives at the local location is determined; and based on the second external reference time and the second network delay time, a second time when the second external reference time arrives at the local location is determined. Based on the first local time, the second local time, the first time, and the second time, determine the first frequency deviation rate between the first time and the second time; Obtain all the equivalent temperatures between the first time point and the second time point; Using all the equivalent temperatures between the first time and the second time and the first frequency deviation rate between the first time and the second time as supervised learning samples, the weights of the first temperature, the second temperature, and the third temperature, as well as the bias term, are updated by a learning algorithm.

8. The method according to claim 7, characterized in that, Before the step of determining the first frequency deviation rate between the first time and the second time based on the first local time, the second local time, the first time, and the second time, the method further includes: If the absolute value of the difference between the first time and the first local time is greater than the first preset threshold, then the first local time is corrected to the first time.

9. The method according to claim 7, characterized in that, Prior to the step of obtaining all the equivalent temperatures between the first time point and the second time point, the method further includes: Obtain the first frequency deviation rate from historical data. If there are consecutive preset number of positive first frequency deviation rates, or consecutive preset number of negative first frequency deviation rates, then generate an early warning log.

10. The method according to claim 1, characterized in that, The step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected, based on the equivalent temperature of the crystal oscillator at the current wake-up time and using a matched test strategy, includes: Determine the similarity between the equivalent temperature of the crystal oscillator at the current wake-up time and the equivalent temperature at the previous wake-up time; Based on the confidence interval of the similarity, a matching test strategy is determined; wherein, different test strategies correspond to multiple different test capacitors in different test sequences; The target test frequency of the crystal oscillator is tested using a matching test strategy with multiple different test capacitors connected.

11. The method according to claim 10, characterized in that, The step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matching test strategy includes: In response to the similarity being within a first confidence interval, it is determined that a first testing strategy will be used to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected. Wherein, the lower limit of the first confidence interval is greater than or equal to the first confidence level. Under the first test strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is determined as the first initialization capacitor, and a first test sequence is constructed with the first initialization capacitor as the center, and the difference between the first initialization capacitor and the first initialization capacitor does not exceed the first capacitor value, and the test capacitors are formed to increase in increments of the first step value.

12. The method according to claim 11, characterized in that, The step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matching test strategy includes: In response to the similarity being within the second confidence interval, it is determined that a second testing strategy will be used to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected. Wherein, the upper limit of the second confidence interval is less than or equal to the first confidence level and greater than or equal to the second confidence level. Under the second test strategy, the target capacitor corresponding to the equivalent temperature at the previous wake-up time is first determined as the second initialization capacitor, and a second test sequence is constructed with the second initialization capacitor as the center, and the difference between the second initialization capacitor and the second initialization capacitor does not exceed the second capacitor value, and the multiple test capacitors are formed in sequence with a second step value. When testing the test capacitors in the second test sequence, the target test frequency change rate corresponding to the adjacent test capacitors is determined. If the target test frequency change rate exceeds the second preset threshold, the test capacitor corresponding to the target test frequency change rate exceeding the second preset threshold is determined as the third initialization capacitor, and a third test sequence is constructed with the third initialization capacitor as the center, and the difference between the third initialization capacitor and the third initialization capacitor does not exceed the third capacitor value, and the multiple test capacitors are formed in sequence with a third step value. Wherein, the range length of the capacitance value of the test capacitor in the second test sequence is greater than the range length of the capacitance value of the test capacitor in the first test sequence, the range length of the capacitance value of the test capacitor in the second test sequence is greater than the range length of the capacitance value of the test capacitor in the third test sequence, the second step value is greater than the first step value, and the second step value is greater than the third step value.

13. The method according to claim 12, characterized in that, The step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matching test strategy includes: In response to the similarity being in the third confidence interval, it is determined that a third testing strategy is used to test the target test frequency of the crystal oscillator when multiple different test capacitors are connected. Wherein, the upper limit of the third confidence interval is less than or equal to the second confidence level. Under the third test strategy, the capacitor corresponding to the center value among all capacitor values ​​is determined as the fourth initial capacitor, and a fourth test sequence of the test capacitors covering the length of the capacitance value range of all capacitors is constructed. In the fourth test sequence, the capacitance difference between adjacent test capacitors within a preset range is less than the capacitance difference between adjacent test capacitors outside the preset range.

14. The method according to claim 10, characterized in that, The step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected includes: For each test capacitor in the test sequence, the test capacitor is connected to the crystal oscillator, and a first waiting period is executed; The test frequency corresponding to the test capacitor at multiple different times is obtained to determine the target test frequency.

15. The method according to claim 1, characterized in that, The step of determining the target capacitor to be connected to the crystal oscillator based on the target test frequency and the multiple different test capacitors connected to the crystal oscillator includes: The first functional relationship is determined based on all the target test frequencies and the corresponding test capacitors; The calculation frequency corresponding to each of the multiple dummy capacitors is calculated using the first functional relationship; wherein, the multiple dummy capacitors are increased sequentially with the fourth step value; If the absolute value of the calculated frequency deviation corresponding to multiple adjacent dummy capacitors is less than a third preset threshold, then the dummy capacitor corresponding to the center value of the capacitance range formed by the multiple adjacent dummy capacitors is determined as the target capacitor; wherein, the calculated frequency deviation is equal to the absolute value of the difference between the calculated frequency and the reference frequency.

16. The method according to claim 1, characterized in that, Before the step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matched test strategy based on the equivalent temperature of the crystal oscillator at the current wake-up time, the method further includes: At least based on the equivalent temperature, determine whether the triggering condition is met; If the triggering condition is met, then the step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected, based on the equivalent temperature of the crystal oscillator at the current wake-up time, using a matching test strategy, is executed.

17. The method according to claim 16, characterized in that, The triggering conditions include the absolute value of the difference between the equivalent temperature at the current wake-up time and the equivalent temperature at the previous wake-up time exceeding the temperature difference threshold, and the duration being not less than a first duration.

18. The method according to claim 16, characterized in that, Before the step of testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matched test strategy based on the equivalent temperature of the crystal oscillator at the current wake-up time, the method further includes: The control system enters a tuning mode; wherein, the tuning mode includes at least the processor entering a sleep mode; and, After the step of determining the target capacitor to be connected to the crystal oscillator based on the target test frequency and the multiple different test capacitors connected to the crystal oscillator, the method further includes: Control the system to exit the tuning mode.

19. The method according to claim 1, characterized in that, After the step of determining the target capacitor to be connected to the crystal oscillator based on the target test frequency and the multiple different test capacitors connected to the crystal oscillator, the method further includes: At least the equivalent temperature and the corresponding target capacitance are stored; The accumulated equivalent temperatures and corresponding target capacitances are periodically analyzed using a learning algorithm to establish a temperature-capacitance prediction model; wherein the prediction model is used to optimize the testing strategy.

20. An electronic device, characterized in that, The system includes an interconnected memory and a processor, wherein the memory is used to store a computer program, which, when executed by the processor, is used to implement the method as described in any one of claims 1-19.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that can be executed by a processor to implement the steps of the method as described in any one of claims 1-19.

Images