RLS echo cancellation system based on FPGA parallel architecture

Abstract

This invention belongs to the field of ultrasonic wireless communication technology through metal media, specifically a Resonant Linear Echo Cancellation (RLS) system based on an FPGA parallel architecture. The system includes a communication transmitter, a metal channel, and a communication receiver. The transmitter includes a digital modulation module, a DAC conversion circuit, a bandpass filter circuit, a signal amplification circuit, a voltage follower circuit, and an ultrasonic transducer. The receiver includes an ultrasonic transducer, a front-end signal conditioning circuit, an ADC conversion circuit, and an FPGA digital signal processing unit. The data to be transmitted is converted into ultrasonic waves by the transmitter and enters the metal channel. After propagation, it enters the receiver, where the FPGA digital signal processing unit performs echo cancellation and demodulation to recover the data. This system utilizes the parallel computing advantages of the FPGA to implement the RLS algorithm in hardware, achieving stable and reliable ultrasonic communication through a metal wall in a sealed metal cavity environment.

Description

Technical Field

[0001] This invention belongs to the field of ultrasonic wireless communication technology across metal walls, and relates to an echo cancellation method for ultrasonic communication across metal walls, specifically an RLS echo cancellation system based on an FPGA parallel architecture. Background Technology

[0002] In communication scenarios involving enclosed metal cavities and metal walls, ultrasound has become the mainstream signal transmission medium, replacing electromagnetic waves, due to its ability to penetrate metal shielding and its immunity to the skin effect. Current domestic and international technologies primarily focus on ultrasonic transmission and reception, front-end conditioning, demodulation, and decision-making. Some systems utilize microcontrollers or DSPs as core processing units, employing simple filtering and threshold decision-making to achieve low-speed data transmission, finding initial applications in industrial monitoring and pressure vessel status acquisition. As transmission rate demands increase, existing solutions are gradually incorporating adaptive filtering algorithms to suppress multipath echoes and inter-symbol interference from metal walls. Algorithms such as LMS and NLMS are widely used due to their simple implementation structure, while the RLS algorithm, with its fast convergence speed and small steady-state error, is more advantageous in high-reliability transmission scenarios. However, most of these algorithms remain at the software simulation and offline processing stage, with limited real-time hardware implementation.

[0003] Despite the continuous development of ultrasonic cross-metal communication technology, existing systems still have significant shortcomings. First, their echo interference suppression capabilities are insufficient. Multiple reflections of ultrasonic waves within the metal wall create strong multipath echoes, causing severe inter-symbol interference. Conventional filtering and simple adaptive algorithms struggle to quickly track time-varying channels, leading to signal distortion and increased bit error rate, failing to meet the demands of large data transmission such as images. Second, the processing platform's real-time performance is mismatched with its computing power. The serial execution architecture of microcontrollers and DSPs is ill-suited for the parallel processing requirements of high-order algorithms like RLS, resulting in high computational latency and low resource utilization, failing to meet real-time echo cancellation and high-speed demodulation requirements. Third, the integration of algorithms and hardware is low. Most solutions treat adaptive echo cancellation algorithms as independent functional modules, failing to integrate them with front-end signal conditioning and demodulation decision-making, leading to poor system compatibility and limited overall performance. Furthermore, existing systems generally lack specialized optimizations for enclosed metal cavity scenarios, exhibiting shortcomings in signal bandwidth, dynamic range, and anti-interference capabilities, making it difficult to balance transmission rate and reliability, and ultimately unable to achieve stable cross-wall transmission of high-quality image data.

[0004] Overall, existing ultrasonic communication solutions across metal walls generally suffer from problems such as weak echo interference suppression, insufficient real-time hardware processing performance, poor compatibility between algorithms and hardware architecture, and difficulty in balancing system stability and transmission rate, which cannot meet the requirements for high-speed and reliable data transmission in a closed metal cavity environment. Summary of the Invention

[0005] To address the shortcomings of existing ultrasonic communication systems across metal walls, such as insufficient echo interference suppression, poor real-time hardware processing, and low algorithm-hardware compatibility, this invention proposes an RLS echo cancellation system based on an FPGA parallel architecture. Leveraging the parallel computing advantages of FPGAs, the RLS algorithm is hardware-based to suppress multipath echoes and inter-symbol interference generated during ultrasonic wave propagation through a metal wall. The integrated design of the algorithm and ultrasonic transceiver link is optimized to achieve efficient coordination between echo cancellation and signal processing, overcoming the high bit error rate and low integration of existing systems. This enables stable and reliable ultrasonic communication across metal walls in a sealed metal cavity environment.

[0006] The present invention is implemented using the following technical solution: an RLS echo cancellation system based on FPGA parallel architecture, comprising a communication transmitter, a metal channel and a communication receiver; The communication transmitter includes a digital modulation module, a DAC conversion circuit, a bandpass filter circuit, a signal amplification circuit, a voltage follower circuit, and an ultrasonic transducer. The digital modulation module performs 2ASK binary amplitude shift keying modulation on the data to be transmitted to generate a 2ASK modulated signal that conforms to the system's operating frequency, and synchronously outputs the 2ASK modulated signal to the DAC conversion circuit. The DAC conversion circuit completes the conversion of the 2ASK modulated signal from the digital domain to the analog domain, and outputs an analog ultrasonic excitation signal to the bandpass filter circuit. The bandpass filter circuit filters the analog ultrasonic excitation signal, and the signal amplification circuit amplifies the voltage amplitude of the filtered analog ultrasonic excitation signal. The amplified analog ultrasonic excitation signal enters the ultrasonic transducer through the voltage follower circuit. The ultrasonic transducer converts the analog ultrasonic excitation signal into ultrasonic waves. The ultrasonic waves enter the metal channel for propagation. The multipath echoes formed by the ultrasonic waves propagating inside the metal channel are superimposed with the direct waves to form a superimposed signal. The communication receiver includes an ultrasonic transducer, a front-end signal conditioning circuit, an ADC conversion circuit, and an FPGA digital signal processing unit. The ultrasonic transducer receives the superimposed signal after passing through a metal channel and converts it into an analog electrical signal. The front-end signal conditioning circuit includes a signal amplification circuit and a bandpass filter circuit. The signal amplification circuit boosts the voltage amplitude of the analog electrical signal, and the bandpass filter circuit filters the boosted analog electrical signal. The ADC conversion circuit converts the front-end conditioned analog electrical signal into a digital signal, and then outputs the digital signal to the FPGA digital signal processing unit for subsequent echo cancellation and demodulation processing. The FPGA digital signal processing unit includes an RLS echo cancellation module and a demodulation module. The RLS echo cancellation module adopts a fully hardware parallel architecture, and through multiple sets of parallel computing units and pipelined processing, it realizes the real-time operation of the RLS algorithm to cancel the echo of the input digital signal. The demodulation module performs synchronous demodulation on the echo-cancelled digital signal, completes carrier recovery, symbol decision, and data reconstruction, and recovers the data to be transmitted from the communication transmitter.

[0007] The aforementioned RLS echo cancellation system based on FPGA parallel architecture has a metal channel that is a sealed metal cavity structure, which serves as the propagation medium for ultrasonic waves in this system.

[0008] The aforementioned RLS echo cancellation system based on an FPGA parallel architecture includes an RLS echo cancellation module comprising a tap delay module, a weight coefficient update module, and an error calculation module. The tap delay module, based on the FPGA's internal shift register array, performs multi-level controllable delay on the input digital signal to generate a time-aligned parallel tap input vector, providing the signal's historical state for subsequent weighted calculations. The error calculation module calculates the error signal time-by-time based on the preset expected output and the actual output of the RLS echo cancellation module, serving as the basis for algorithm iterative optimization. The weight coefficient update module, based on the exponential weighted least squares criterion of the RLS algorithm, uses the error signal and the parallel tap input vector to perform real-time iterative updates of the weight coefficients within the RLS echo cancellation module, tracking the time-varying characteristics of the channel.

[0009] The present invention has the following advantages: 1) This invention implements the RLS algorithm through FPGA, which can effectively suppress strong echo interference and inter-symbol interference formed by multiple reflections inside the metal wall, significantly improve the signal-to-noise ratio and waveform fidelity of the recovered data to be transmitted, and ensure the accuracy and stability of data transmission. 2) The algorithm is completed using an FPGA parallel architecture and state machine. Real-time signal processing can be achieved without relying on a high-performance processor. The system has fast response, strong anti-interference ability, and can adapt to the complex and ever-changing channel environment of a closed metal cavity. 3) The RLS echo cancellation module is integrated with the front-end signal conditioning circuit and demodulation module, resulting in a high degree of algorithm specialization, reasonable allocation of hardware resources, and a compact and highly integrated overall system structure. 4) This invention is specifically optimized for communication scenarios across metal walls. It can work stably under harsh conditions such as strong electromagnetic shielding, high signal attenuation, and severe multipath echo interference. It does not require opening holes or structural modifications to the metal cavity. It can achieve reliable and high-quality signal transmission while preserving the strength and sealing of the sealed metal structure. Attached Figure Description

[0010] Figure 1 This is a system structure diagram of the present invention.

[0011] Figure 2 This is a schematic diagram of superimposed signals.

[0012] Figure 3 A comparison of waveforms before and after RLS echo cancellation.

[0013] In the diagram: 1-Ultrasonic transmitting transducer, 2-Ultrasonic receiving transducer, 3-Metallic channel. Detailed Implementation

[0014] An RLS echo cancellation system based on FPGA parallel architecture comprises three main components: a communication transmitter, a metal channel 3, and a communication receiver.

[0015] like Figure 1As shown, the communication transmitter includes a digital modulation module, a DAC conversion circuit, a bandpass filter circuit, a signal amplification circuit, a voltage follower circuit, and an ultrasonic transducer 1. The digital modulation module, based on the internal logic resources of the FPGA, performs 2ASK binary amplitude-keying modulation on the data to be transmitted. It controls the amplitude output of the carrier signal according to the data to be transmitted, generates a 2ASK modulated signal conforming to the system's operating frequency through symbol mapping and multiplication with the carrier, and synchronously outputs this 2ASK modulated signal to the DAC conversion circuit. The DAC conversion circuit uses a high-speed digital-to-analog converter to convert the 2ASK modulated signal from the digital domain to the analog domain, outputting an analog ultrasonic excitation signal to the bandpass filter circuit. The bandpass filter circuit uses a Butterworth bandpass filter circuit to filter the analog ultrasonic excitation signal, effectively filtering out high-frequency noise and low-frequency power supply interference, while limiting the signal spectrum within the operating frequency range of the ultrasonic transducer 1, ensuring the signal bandwidth resonates with the transducer. Precise frequency matching improves electro-acoustic conversion efficiency; the signal amplification circuit uses an operational amplifier to amplify the voltage amplitude of the filtered analog ultrasonic excitation signal, ensuring that the signal amplitude meets the driving requirements of the ultrasonic transmitting transducer 1, and ensuring that the ultrasonic transmitting transducer 1 can generate sufficient energy to enter the metal channel 3; the voltage follower circuit uses a unity-gain buffer structure composed of operational amplifiers to provide input and output impedance buffering for the entire communication transmitter, reducing the influence of the ultrasonic transmitting transducer 1 on the preceding signal, improving the overall load capacity, ensuring stable driving between the signal amplification circuit and the ultrasonic transmitting transducer 1, and avoiding waveform distortion and amplitude attenuation; the ultrasonic transmitting transducer 1 converts the analog ultrasonic excitation signal processed by the communication transmitter into ultrasonic waves, which are then efficiently coupled into the metal channel 3 in the form of longitudinal waves for propagation.

[0016] The metal channel 3 is a sealed metal cavity structure and serves as the primary propagation medium for ultrasonic waves in this system. As ultrasonic waves propagate within the metal channel 3, they undergo multiple reflections and scatterings at the cavity walls, interfaces between different materials, and structural corners, generating multipath echoes of varying intensities and time delays. These multipath echoes, superimposed on the direct wave, will cause severe inter-symbol interference and signal distortion at the communication receiver. Furthermore, the metal channel 3 itself exhibits inherent attenuation characteristics for ultrasonic waves; as the propagation distance and wall thickness increase, the ultrasonic energy gradually diminishes.

[0017] The communication receiver includes an ultrasonic transducer 2, a front-end signal conditioning circuit, an ADC conversion circuit, and an FPGA digital signal processing unit. The ultrasonic transducer 2 converts the superimposed signal after passing through the metal channel 3 into an analog electrical signal. However, the amplitude of the superimposed signal is significantly attenuated, making it susceptible to environmental and circuit noise, and thus unable to be directly demodulated. The front-end signal conditioning circuit includes a signal amplification circuit and a bandpass filter circuit. The signal amplification circuit uses an operational amplifier to boost the voltage amplitude of the received weak analog electrical signal, amplifying it to a range suitable for the ADC conversion circuit while avoiding signal distortion. The bandpass filter circuit uses the same Butterworth bandpass filter circuit as the communication transmitter, with a filtering frequency strictly matched to the bandpass filter frequency of the communication transmitter, suppressing broadband noise and clutter introduced during propagation through the metal channel 3 and preserving the effective signal bandwidth. The ADC conversion circuit uses a high-speed, high-precision analog-to-digital converter to convert the front-end conditioned analog electrical signal into a high-precision digital signal, which is then output to the FPGA digital signal processing unit for subsequent echo cancellation and demodulation processing.

[0018] The FPGA digital signal processing unit includes an RLS echo cancellation module and a demodulation module. The RLS echo cancellation module adopts a fully hardware parallel architecture, using multiple parallel processing units and pipelined processing to achieve real-time operation of the RLS algorithm and cancel the echo of the input digital signal. The demodulation module synchronously demodulates the echo-cancelled signal, completing carrier recovery, symbol decision, and data reconstruction to recover the data to be transmitted from the communication transmitter. Specifically, the RLS echo cancellation module includes a tap delay module, a weight coefficient update module, and an error calculation module. The tap delay module, based on the FPGA's internal shift register array, performs multi-level controllable delay on the input digital signal, generating a time-aligned parallel tap input vector to provide the signal's historical state for subsequent weighted calculations. The error calculation module calculates the error signal time-by-time based on the preset expected output and the actual output of the RLS echo cancellation module, serving as the basis for algorithm iterative optimization. The weight coefficient update module, based on the exponentially weighted least squares criterion of the RLS algorithm, uses the error signal and the parallel tap input vector to perform real-time iterative updates of the weight coefficients within the RLS echo cancellation module, tracking the time-varying characteristics of the channel.

[0019] like Figure 2As shown, the data to be transmitted is modulated by the digital modulation module, then converted by a DAC, bandpass filtered, amplified, and voltage followed, and then drives the ultrasonic transmitting transducer 1 to generate ultrasonic waves (the upper waveform in the figure). The first peak appearing in the superimposed signal (the lower waveform in the figure) received by the ultrasonic receiving transducer 2 at the communication receiving end is the main impulse response. This waveform is the direct wave formed after the ultrasonic wave penetrates the metal channel 3, which is the effective signal of the communication information. The peaks that appear after the first peak represent multipath echoes. Due to the reflection and scattering of ultrasonic waves when propagating in the metal channel 3, the overall trend is a gradual attenuation. As the number of reflections continues to increase, the energy of the ultrasonic wave is continuously dissipated at the medium and interface, and the amplitude of the multipath echoes gradually attenuates to the system noise floor. The received superimposed signal eventually tends to flatten.

[0020] like Figure 3 As shown in the figure, 'a' represents the superimposed signal (and) received by the ultrasonic transducer 2 at the communication receiving end. Figure 2 (The waveform below is the same). In the figure, b indicates that after processing by the RLS echo cancellation module, the signal waveform has changed significantly. The amplitude of the main pulse response remains basically unchanged, and subsequent multipath echoes are effectively suppressed.

Claims

1. An RLS echo cancellation system based on an FPGA parallel architecture, characterized in that: It includes a communication transmitter, a metal channel (3), and a communication receiver; The communication transmitter includes a digital modulation module, a DAC conversion circuit, a bandpass filter circuit, a signal amplification circuit, a voltage follower circuit, and an ultrasonic transducer (1). The digital modulation module performs 2ASK binary amplitude keying modulation on the data to be transmitted to generate a 2ASK modulation signal that conforms to the system operating frequency, and outputs the 2ASK modulation signal synchronously to the DAC conversion circuit. The DAC conversion circuit completes the conversion of the 2ASK modulation signal from the digital domain to the analog domain and outputs the analog ultrasonic excitation signal to the bandpass filter circuit. The bandpass filter circuit filters the analog ultrasonic excitation signal, and the signal amplification circuit amplifies the voltage amplitude of the filtered analog ultrasonic excitation signal. The amplified analog ultrasonic excitation signal enters the ultrasonic transducer (1) through the voltage follower circuit. The ultrasonic transducer (1) converts the analog ultrasonic excitation signal into ultrasonic waves. The ultrasonic waves enter the metal channel (3) to propagate. When the ultrasonic waves propagate inside the metal channel (3), the multipath echoes formed are superimposed with the direct waves to form a superimposed signal. The communication receiver includes an ultrasonic receiving transducer (2), a front-end signal conditioning circuit, an ADC conversion circuit, and an FPGA digital signal processing unit; the ultrasonic receiving transducer (2) receives the superimposed signal after passing through the metal channel (3) and converts it into an analog electrical signal; the front-end signal conditioning circuit includes a signal amplification circuit and a bandpass filter circuit, wherein the signal amplification circuit boosts the voltage amplitude of the analog electrical signal, and the bandpass filter circuit filters the boosted analog electrical signal; The ADC conversion circuit converts the front-end conditioned analog electrical signal into a digital signal, and then outputs the digital signal to the FPGA digital signal processing unit for subsequent echo cancellation and demodulation processing. The FPGA digital signal processing unit includes an RLS echo cancellation module and a demodulation module. The RLS echo cancellation module adopts a fully hardware parallel architecture, and realizes the real-time operation of the RLS algorithm through multiple sets of parallel computing units and pipeline processing to cancel the echo of the input digital signal. The demodulation module performs synchronous demodulation on the echo-cancelled digital signal, completes carrier recovery, symbol decision and data reconstruction, and recovers the data to be transmitted from the input communication transmitter.

2. The RLS echo cancellation system based on FPGA parallel architecture according to claim 1, characterized in that: The metal channel (3) is a closed metal cavity structure.

3. The RLS echo cancellation system based on FPGA parallel architecture according to claim 1, characterized in that: The RLS echo cancellation module specifically includes a tap delay module, a weight coefficient update module, and an error calculation module. The tap delay module, based on the FPGA's internal shift register array, performs multi-level controllable delay on the input digital signal to generate a time-aligned parallel tap input vector, providing the signal history state for subsequent weighted operations. The error calculation module calculates the error signal time-by-time based on the preset expected output and the actual output of the RLS echo cancellation module, serving as the basis for algorithm iterative optimization. The weight coefficient update module is based on the exponentially weighted least squares criterion of the RLS algorithm. It uses the error signal and parallel tap input vector to complete the iterative update of the weight coefficients in the RLS echo cancellation module in real time, tracking the time-varying characteristics of the channel.

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