A fast convergence method for serdes digital eye diagram test

Abstract

The purpose of this invention is to provide a fast convergence method for SerDes digital eye diagram testing. This method includes: successively scanning points on the X and Y axes of the eye diagram; using points where bit errors occur as boundary points; and calculating the bit error rate based on the boundary points and the number of samples. This invention can significantly reduce the number of samples required for a single operation, thereby greatly reducing the time required for a single test. Using this method, the test time can be reduced from several hours to just a few minutes, saving testers a considerable amount of time for chip debugging and testing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a fast convergence method for SerDes digital eye diagram testing. Background Technology

[0002] Digital eye diagram (DAD) testing is an important tool for analyzing the quality of high-speed digital signal transmission. An eye diagram is generated by overlaying multiple cycles of signal waveforms on an oscilloscope, creating a shape resembling an eye. This diagram visually displays key parameters such as signal integrity, jitter, and noise. The eye diagram accumulates and displays the bit results of the acquired serial signal using the oscilloscope's persistence mode. The oscilloscope separates all symbols in the signal and displays them on the screen, forming an eye-like shape. The size of the "eye" in the eye diagram reflects the strength of inter-symbol interference (ISI); a larger and more upright eye indicates less ISI, and vice versa.

[0003] With the advancement of high-tech technologies such as big data computing and deep learning, which rely on massive data transmission, higher bandwidth requirements are being placed on the hardware design at the bottom layer of network transmission. The clock generation and recovery technologies used in SerDes high-speed serial channels, along with serial-to-parallel and parallel-to-serial conversion technologies, significantly increase the bandwidth of data transmission per pin, greatly improving the device's data throughput rate. As SerDes rates increase and channel attenuation worsens, the role of the receiver equalizer becomes increasingly important. Bit error rate (BER) is commonly used as a method to diagnose equalizer performance. Currently, the industry commonly uses digital eye diagrams (DADs) as a reference for testing receiver equalizer performance. The most common method is to compare the received data after adjusting the horizontal and vertical offsets with the original data to count the number of errors (BER). The software side records the BER after each adjustment and finally outputs the BER of the entire two-dimensional offset, forming the final digital eye diagram. Creating the eye diagram requires extensive data statistics; a common method is to scan all offset points step by step. For example, the horizontal and vertical offset range commonly used by SerDes manufacturers is 64. If the value is 64, then 1024 counts are required. Different protocols have different bit error rate requirements; for example, PCIe Gen 5 requires a certain bit error rate. Then at least statistics are needed. The data shows that PCIe Gen5 requires at least 34.5 hours. This method of performing a full scan takes too long, making it unsuitable for using eye diagrams as a performance benchmark. Otherwise, it would lead to excessively long SerDes testing cycles, even if the bit error rate (BER) is reduced as a benchmark. A single test would take approximately 20 minutes, which is still unacceptable for later performance exploration. Summary of the Invention

[0004] The purpose of this invention is to provide a fast convergence method for SerDes digital eye diagram testing. This method can greatly reduce the number of samples in one operation, thereby significantly reducing the time consumed in one test. Through the above method, the test time can be reduced from several hours to a few minutes. This solution saves testers a lot of time for chip debugging and testing.

[0005] A fast convergence method for the SerDes digital eye diagram test includes: Scan the points on the X and Y axes of the eye diagram sequentially; Use the points where errors occur during scanning as boundary points; The bit error rate is calculated based on the boundary points and the number of samples.

[0006] Preferably, the points of the successive scan eye diagram on the X and Y axes include: Set the initial value of the horizontal phase difference in the positive directions of the X and Y axes; Set the initial value of the horizontal phase difference in the negative directions of the X and Y axes; Each time, the X and Y axes are scanned by adding 1 to the initial value until an error occurs.

[0007] Preferably, the step of using the points where scanning errors occur as boundary points includes: Scan sequentially along the positive X-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative X-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the positive Y-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative Y-axis until a bit error occurs, and mark the bit error as a boundary point.

[0008] Preferably, the step of calculating the bit error rate based on boundary points and the number of samples includes: The current number of samples is obtained from the counter register; When the number of samples reaches the protocol requirement, the bit error rate is calculated based on the values ​​of the boundary points and the current number of samples.

[0009] Preferably, the step of using the points where scanning errors occur as boundary points further includes: Choose either the X or Y axis direction, set the initial bias to the maximum value a, and calculate the current bit error rate based on the number of samples. If the bit error rate is less than the protocol requirement, the current bias value is the boundary point; otherwise, the next bias value is half of the maximum value, a / 2. Calculate the bit error rate when the bias is a / 2. If the bit error rate is less than the protocol, add a / 4 to the current bias; otherwise, subtract a / 4 from the current bias. Then, configure the calculated bias into the register inside SerDes. The process is iterated, with the amount of bias modification divided by 2 each time, until the amount of bias modification becomes 1. The final boundary point is the bias obtained from the last calculation.

[0010] Preferably, the step of adding 1 to the initial value each time and scanning the X and Y axes until an error occurs includes: Connect the signal transmitter and the signal receiver through the system under test; The clocks of the synchronization signal transmitter and receiver; The sending end continuously sends data and increments by 1 with each subsequent data transmission; the receiving end counts the number of error bits.

[0011] Preferably, determining whether the eye diagram has converged based on the bit error rate at the boundary points includes: Total number of samples = Total number of sampling frames × Bit width; The error bit count is the total count of error bits after comparing the data after bias adjustment with the normal data in each of the total sampling cycles. Bit error rate = total number of bits / number of erroneous bits.

[0012] A fast convergence system for the SerDes digital eye diagram test includes: The scanning module is used to scan the points of the eye diagram on the X and Y axes one by one; The boundary point construction module is used to identify points where errors occur during scanning as boundary points. The bit error rate calculation module is used to calculate the bit error rate based on the boundary points and the number of samples.

[0013] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs a fast convergence method for a SerDes digital eye diagram test.

[0014] A computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform a fast convergence method for the SerDes digital eye diagram test.

[0015] The beneficial effects of this invention are as follows: 1. By analyzing the common digital bit error rate (BER) eye diagram sampling principle, this invention finds the core reference point for this function in SerDes testing and proposes a new methodology, changing from two-dimensional graphic scanning to boundary point search, thereby greatly saving the testing time; 2. This invention analyzes and summarizes the BER testing principle and introduces a new testing method: four-quadrant eye diagram scanning. The two-dimensional scan is transformed into a boundary scan along the X and Y axes, and the number of scan points decreases exponentially; 3. This invention transforms the point-by-point scan in the same direction into a bisection single-point scan, and the number of scan points also decreases exponentially. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a fast convergence method for SerDes digital eye diagram testing according to the present invention; Figure 2 This is a schematic diagram of the digital eye diagram of the present invention; Figure 3 This is a schematic diagram of the four-quadrant eye diagram of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0022] With the advancement of high-tech technologies such as big data computing and deep learning, which rely on massive data transmission, higher bandwidth requirements are being placed on the hardware design at the bottom layer of network transmission. The clock generation and recovery technologies used in SerDes high-speed serial channels, along with serial-to-parallel and parallel-to-serial conversion technologies, significantly increase the bandwidth of data transmission per pin, greatly improving the device's data throughput rate. As SerDes rates increase and channel attenuation worsens, the role of the receiver equalizer becomes increasingly important. Bit error rate (BER) is commonly used as a method to diagnose equalizer performance. Currently, the industry commonly uses digital eye diagrams (DADs) as a reference for testing receiver equalizer performance. The most common method is to compare the received data after adjusting the horizontal and vertical offsets with the original data to count the number of errors (BER). The software side records the BER after each adjustment and finally outputs the BER of the entire two-dimensional offset, forming the final digital eye diagram. Creating the eye diagram requires extensive data statistics; a common method is to scan all offset points step by step. For example, the horizontal and vertical offset range commonly used by SerDes manufacturers is 64. If the value is 64, then 1024 counts are required. Different protocols have different bit error rate requirements; for example, PCIe Gen 5 requires a certain bit error rate. Then at least statistics are needed. The data shows that PCIe Gen5 requires at least 34.5 hours. This method of performing a full scan takes too long, making it unsuitable for using eye diagrams as a performance benchmark. Otherwise, it would lead to excessively long SerDes testing cycles, even if the bit error rate (BER) is reduced as a benchmark. A single test would take approximately 20 minutes, which is still unacceptable for later performance exploration.

[0023] This invention analyzes the common digital bit error rate (BER) eye diagram sampling principle, identifies the core reference point for this function in SerDes testing, and proposes a new methodology, shifting from two-dimensional graphic scanning to boundary point search, thus significantly saving testing time. This invention analyzes and summarizes the BER testing principle, introducing a new four-quadrant eye diagram scanning method, transforming the two-dimensional scan into a boundary scan along the X and Y axes, resulting in an exponential decrease in the number of scan points. Furthermore, this invention transforms the point-by-point scan in the same direction into a bisection-based single-point scan, also resulting in an exponential decrease in the number of scan points.

[0024] Example 1 A fast convergence method for the SerDes digital eye diagram test includes: S100, successively scan the points of the eye diagram on the X and Y axes; refer to Figure 2 Eye diagram testing is primarily used for signal integrity analysis in high-speed interconnect systems, helping to evaluate system performance. Through eye diagrams, the effects of inter-symbol interference (ISI) and noise can be observed, allowing for adjustments to the characteristics of the receiver filter to reduce ISI and improve system transmission performance. Furthermore, eye diagrams visually display the distribution of signal noise and jitter, helping engineers identify and resolve potential signal integrity issues, ensuring the reliability of high-speed data transmission links.

[0025] S200 uses the points where errors occur during scanning as boundary points; The points where errors occur in a scan refer to the erroneous bits in the digital signal transmission that are directly or indirectly reflected through eye diagram analysis. It reflects the impact of signal quality on communication reliability and is a key evaluation indicator in high-speed digital design (such as SerDes, fiber optic communication, PCB routing). Eye diagram errors are a direct manifestation of signal integrity problems.

[0026] S300 calculates the bit error rate based on boundary points and the number of samples.

[0027] Bit error rate (BER) is a metric that measures the accuracy of data transmission. It represents the percentage of erroneous symbols or bits in the total transmitted data. Bit errors are mainly caused by the following factors: signal attenuation and noise: voltage fluctuations and electromagnetic interference (such as lightning) cause signal distortion; equipment failure: insufficient performance or failure of transmission equipment; synchronization errors: bit synchronization problems cause data stream misalignment. BER is a core indicator for measuring the reliability of digital system transmission, reflecting how many bits of data have a single error.

[0028] Current common digital bit error rate (BER) eye diagrams are generated by progressively scanning all bias points to form a complete two-dimensional graph. For example, in the SerDes chip testing phase, this invention adjusts the X-axis and Y-axis bias configurations via a host computer. SerDes performs one round of data transmission under this configuration, then calculates the total amount of data transmitted and the number of errors. Based on this, this invention can obtain the BER at the current bias point. Subsequently, it progressively scans all X and Y-axis bias points to obtain the corresponding BER, and then uses software to draw the aforementioned two-dimensional graph. Testers use this as a reference point for testing signal quality.

[0029] In this invention, a color is used to represent a specific bit error rate (BER) in the digital bit error rate (BER) eye diagram. Observations reveal that the shape and boundaries of each BER diagram are relatively regular. This invention finds that a fixed BER essentially resembles a diamond shape (often called an eye diagram). The size of the eye diagram is often used as a reference point for signal quality, and its size is generally described by the four boundary points on the X and Y axes. Therefore, this invention can reflect the current signal quality at the RX end by scanning only the boundary points on the four coordinate axes, thus serving as a reference indicator for testing. For example, for the PCIe protocol, the BER testing requirements are... Therefore, the present invention requires the measurement of four points. The larger the cumulative value of these four points, the better the signal quality of the current channel. The four-quadrant eye diagram is shown below. Figure 3 As shown.

[0030] Preferably, in step S100, the successive scanning of the eye diagram points on the X and Y axes includes: Set the initial value of the horizontal phase difference in the positive directions of the X and Y axes; Set the initial value of the horizontal phase difference in the negative directions of the X and Y axes; Before eye diagram scanning, an initial deviation value needs to be set on the X and Y axes. This initial deviation value can be set based on prior data and experience. After each eye diagram scan, a certain value is added to this initial deviation value until an error is detected. When an error is detected, it means that a boundary point has appeared on the X or Y axis.

[0031] Each time, the X and Y axes are scanned by adding 1 to the initial value until an error occurs.

[0032] Compared to two-dimensional graphics, this invention only requires scanning the four boundary points of the X and Y axes, which significantly reduces the overall testing time. For example, if the X-axis is ultimately located at ±15 and the Y-axis at ±10, the required time is approximately 26 minutes. This is especially beneficial in early performance and functional tests where the eye diagram is relatively poor, as the boundary eye diagram (above) is more suitable for these conditions. Figure 4The image position eye diagram is relatively small, so the time to complete one scan of this invention is relatively short. One scan may only take a few minutes, which is relatively acceptable to testers.

[0033] Preferably, in step S200, the point where a scanning error occurs is designated as a boundary point, including: Scan sequentially along the positive X-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative X-axis until a bit error occurs, and mark the bit error as a boundary point; In this embodiment of the invention, only points on the X and Y axes need to be scanned, without needing to scan points in the quadrants, which can greatly reduce the number of scans and quickly find boundary points.

[0034] Scan sequentially along the positive Y-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative Y-axis until a bit error occurs, and mark the bit error as a boundary point.

[0035] First, set the horizontal offset (phase difference) to 1 in the positive X direction. After sampling, check for bit errors in both data streams. If errors are found, the current point is the boundary point of the bit error rate. If no errors are found, increment the horizontal offset by 1 and continue sampling until errors occur. Repeat this process for the negative X direction and the positive and negative Y directions until the bit error rate boundary points in all four directions are reached. Calculate the sum of the values ​​in all four quadrants. This value can be used as a criterion for judging the current channel quality; a larger value indicates better channel signal quality after adjustment.

[0036] Preferably, in step S300, calculating the bit error rate based on boundary points and the number of samples includes: The current number of samples is obtained from the counter register; SerDes' internal digital design typically uses a pre-defined counter register (this pre-defined value register is controllable) to count the current total number of samples, for example, the bit error rate reference. If the data width is 40 bits, then this counter can be configured as follows: During eye diagram scanning, a countdown is performed based on this counter. When the count value decreases to 0, it indicates that the current number of samples has reached the protocol requirement. At the same time, the number of errors is recorded internally. The host computer can obtain the current bit error rate by reading the internal register and performing corresponding calculations. When the number of samples reaches the protocol requirement, the bit error rate is calculated based on the values ​​of the boundary points and the current number of samples.

[0037] Preferably, using the points where scanning errors occur as boundary points further includes: Choose either the X or Y axis direction, set the initial bias to the maximum value a, and calculate the current bit error rate based on the number of samples. If the bit error rate is less than the protocol requirement, the current bias value is the boundary point; otherwise, the next bias value is half of the maximum value, a / 2. Calculate the bit error rate when the bias is a / 2. If the bit error rate is less than the protocol, add a / 4 to the current bias; otherwise, subtract a / 4 from the current bias. Then, configure the calculated bias into the register inside SerDes. The process is iterated, with the amount of bias modification divided by 2 each time, until the amount of bias modification becomes 1. The final boundary point is the bias obtained from the last calculation.

[0038] Based on this, the present invention can further shorten the time by introducing a bisection method. The larger the deviation value of the digital eye diagram on the X and Y axes, the higher the bit error rate. Its sampling preset value is consistent with the above description; the main difference lies in the adjustment process of the X and Y axes. The bisection method steps are as follows: First, choose either the X or Y axis direction. Initially, set the offset to the maximum value 'a'. The host computer reads the internal registers and performs corresponding calculations to obtain the current bit error rate. If the bit error rate is less than the protocol requirement, the current configuration is a boundary point; otherwise, the next step is to set the offset to half of the maximum value. ; The host computer reads the internal registers and performs corresponding calculations to obtain the current bit error rate. If the bit error rate is less than the protocol value, the current bias is increased. Otherwise, reduce the current bias. The calculated bias is then configured into the registers inside SerDes. This invention places the bisection operation of searching a specific bit error rate on a host computer, and the algorithm can also be implemented in the hardware inside SerDes.

[0039] Repeat step two iteratively, dividing the offset change by 2 each time, so the configuration change amount each time is... If the configuration change amount becomes 1, then the final boundary point is the offset obtained from the last calculation.

[0040] Repeat the process for the four directions of the X and Y axes, and finally calculate the sum of the four quadrants, which is the size of the current four-quadrant eye diagram, and serves as the criterion for judging the current channel signal quality.

[0041] Preferably, the process of scanning the X and Y axes by adding 1 to the initial value each time until an error occurs includes: Connect the signal transmitter and the signal receiver through the system under test; The clocks of the synchronization signal transmitter and receiver; The sending end continuously sends data and increments by 1 with each subsequent data transmission; the receiving end counts the number of error bits.

[0042] Based on the above method, the horizontal and vertical deviation range commonly used by SerDes is 64. At 64, the maximum single-direction offset of one axis is 32, and a maximum of 5 samplings are required for SerDes in one direction. Therefore, scanning the entire four-quadrant eye diagram requires 20 operations. If the current X-axis is finally positioned at ±15 and the y-axis at ±10, a point-by-point scan might require 50 operations, reducing the time to only 40%. This scheme saves even more time when the channel quality is relatively good; theoretically, the worst channel requires 128 operations. Therefore, the convergence speed of the eye diagram testing method of this invention is significantly better than existing technologies, and the number of points to be scanned is exponentially reduced. This invention can greatly improve testing efficiency and reduce testing costs.

[0043] Preferably, determining whether the eye diagram has converged based on the bit error rate at the boundary points includes: Total number of samples = Total number of sampling frames × Bit width; The error bit count is the total count of error bits after comparing the data after bias adjustment with the normal data in each of the total sampling cycles. Bit error rate = total number of bits / number of erroneous bits.

[0044] If we use the bisection method to find the four boundary points of the eye diagram, the boundary point convergence is a gradual process. This process involves using multiple points, for example, six points. The bit error rate (BER) for each point is calculated, and this BER is the criterion for determining the convergence boundary. The convergence process follows the bisection method steps described earlier.

[0045] Example 2 A fast convergence system for the SerDes digital eye diagram test includes: The scanning module is used to scan the points of the eye diagram on the X and Y axes one by one; An eye diagram is a graph formed by superimposing multiple signal cycles and is used to evaluate the quality of digital signals (such as timing jitter, noise, inter-symbol interference, etc.). It displays the signal waveforms of multiple unit intervals (UI) of a digital signal superimposed to form an "eye" shape; the larger the opening of the eye diagram, the better the signal quality.

[0046] The boundary point construction module is used to identify points where errors occur during scanning as boundary points. The boundary points of an eye diagram mainly include eye height and eye width. Eye height refers to the vertical height of the eye diagram, usually defined as the difference between the minimum high-level value and the maximum low-level value. The magnitude of eye height reflects the degree of noise influence; the larger the eye height, the smaller the noise and the better the signal quality. Eye width refers to the horizontal width of the eye diagram, usually defined as the distance from the leading edge to the trailing edge. The magnitude of eye width reflects the degree of jitter influence; the larger the eye width, the greater the jitter and the higher the probability of sampling bit errors.

[0047] The bit error rate calculation module is used to calculate the bit error rate based on the boundary points and the number of samples.

[0048] Current common digital bit error rate (BER) eye diagrams are generated by progressively scanning all bias points to form a complete two-dimensional graph. For example, in the SerDes chip testing phase, this invention adjusts the X-axis and Y-axis bias configurations via a host computer. SerDes performs one round of data transmission under this configuration, then calculates the total amount of data transmitted and the number of errors. Based on this, this invention can obtain the BER at the current bias point. Subsequently, it progressively scans all X and Y-axis bias points to obtain the corresponding BER, and then uses software to draw the aforementioned two-dimensional graph. Testers use this as a reference point for testing signal quality.

[0049] This invention can reflect the signal quality at the current RX end by scanning only the boundary points on the four coordinate axes, thus serving as a reference indicator for testing. For example, for the PCIe protocol, the bit error rate test requirement is... Therefore, the present invention needs to measure 4 points. The larger the cumulative value of these 4 points, the better the signal quality of the current channel.

[0050] This invention analyzes existing bit error rate (BER) eye diagram sampling principles and summarizes a new channel quality assessment method—the four-quadrant eye diagram. Based on this scheme, a binary search approach is used to find the BER boundary points corresponding to different protocols. This method significantly reduces the number of samples required for a single operation, thereby greatly shortening the test time. The test time can be reduced from several hours to just a few minutes, saving testers considerable time in chip debugging and testing.

[0051] Example 3 An electronic device includes: a chip, a processor, and a memory, the memory for storing computer program code, the computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device executes a fast convergence method for the SerDes digital eye diagram test.

[0052] refer to Figure 4 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, memory 22, input device 23, and output device 24 are coupled together via connectors, which may include various interfaces, transmission lines, or buses, etc., and are not limited in this embodiment of the invention. It should be understood that in the various embodiments of the invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices, such as through various interfaces, transmission lines, buses, etc.

[0053] The processor 21 can be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Optionally, the processor can also be other types of processors, etc., and this embodiment of the invention is not limited thereto.

[0054] The memory 22 can be used to store computer program instructions, as well as various types of computer program code, including program code for executing the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), which is used for related instructions and data.

[0055] Input device 23 is used to input data and / or signals, and output device 24 is used to output data and / or signals. Output device 24 and input device 23 can be independent devices or an integrated device.

[0056] Example 4 A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform a fast convergence method for the SerDes digital eye diagram test.

[0057] This invention analyzes the common digital bit error rate (BER) eye diagram sampling principle, identifies the core reference point for this function in SerDes testing, and proposes a new methodology, shifting from two-dimensional graphic scanning to boundary point search, thus significantly saving testing time. This invention analyzes and summarizes the BER testing principle, introducing a new four-quadrant eye diagram scanning method, transforming the two-dimensional scan into a boundary scan along the X and Y axes, resulting in an exponential decrease in the number of scan points. Furthermore, this invention transforms the point-by-point scan in the same direction into a bisection-based single-point scan, also resulting in an exponential decrease in the number of scan points.

[0058] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A fast convergence method for SerDes digital eye diagram testing, characterized in that, include: Scan the points on the X and Y axes of the eye diagram sequentially; Use the points where errors occur during scanning as boundary points; Determine whether the eye diagram has converged based on the bit error rate at the boundary points.

2. The fast convergence method for SerDes digital eye diagram testing according to claim 1, characterized in that, The points on the X and Y axes of the successive scan eye diagram include: Set the initial value of the horizontal phase difference in the positive directions of the X and Y axes; Set the initial value of the horizontal phase difference in the negative directions of the X and Y axes; Each time, the X and Y axes are scanned by adding 1 to the initial value until an error occurs.

3. The fast convergence method for SerDes digital eye diagram testing according to claim 1, characterized in that, The step of using points where scanning errors occur as boundary points includes: Scan sequentially along the positive X-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative X-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the positive Y-axis until a bit error occurs, and mark the bit error as a boundary point; Scan sequentially along the negative Y-axis until a bit error occurs, and mark the bit error as a boundary point.

4. The fast convergence method for SerDes digital eye diagram testing according to claim 1, characterized in that, The calculation of the bit error rate based on boundary points and the number of samples includes: The current number of samples is obtained from the counter register; When the number of samples reaches the protocol requirement, the bit error rate is calculated based on the values ​​of the boundary points and the current number of samples.

5. A fast convergence method for SerDes digital eye diagram testing according to claim 1, characterized in that, The step of using the points where scanning errors occur as boundary points also includes: Choose either the X or Y axis direction, set the initial bias to the maximum value a, and calculate the current bit error rate based on the number of samples. If the bit error rate is less than the protocol requirement, the current bias value is the boundary point; otherwise, the next bias value is half of the maximum value, a / 2. Calculate the bit error rate when the bias is a / 2. If the bit error rate is less than the protocol, add a / 4 to the current bias; otherwise, subtract a / 4 from the current bias. Then, configure the calculated bias into the register inside SerDes. The process is iterated, with the amount of bias modification divided by 2 each time, until the amount of bias modification becomes 1. The final boundary point is the bias obtained from the last calculation.

6. A fast convergence method for SerDes digital eye diagram testing according to claim 2, characterized in that, The step of scanning the X and Y axes by adding 1 to the initial value each time until an error occurs includes: Connect the signal transmitter and the signal receiver through the system under test; The clocks of the synchronization signal transmitter and receiver; The sending end continuously sends data and increments by 1 with each subsequent data transmission; the receiving end counts the number of error bits.

7. A fast convergence method for SerDes digital eye diagram testing according to claim 4, characterized in that, The step of determining whether the eye diagram has converged based on the bit error rate at the boundary points includes: Total number of samples = Total number of sampling frames × Bit width; The error bit count is the total count of error bits after comparing the data after bias adjustment with the normal data in each of the total sampling cycles. Bit error rate = total number of bits / number of erroneous bits.

8. A fast convergence system for SerDes digital eye diagram testing, characterized in that, include: The scanning module is used to scan the points of the eye diagram on the X and Y axes one by one; The boundary point construction module is used to identify points where errors occur during scanning as boundary points. The bit error rate calculation module is used to calculate the bit error rate based on the boundary points and the number of samples.

9. An electronic device, characterized in that, include: A chip, a processor, and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs a fast convergence method for SerDes digital eye diagram testing as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform a fast convergence method for SerDes digital eye diagram testing according to any one of claims 1 to 7.

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