Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor device and its fabrication method. The semiconductor device includes a substrate structure, a memory region, and a logic region. The substrate structure includes a first substrate and a second substrate. The memory region is disposed on the first substrate, and the logic region is disposed on the second substrate. The memory region and the logic region are bonded and packaged, such that the logic region, the second substrate, the memory region, and the first substrate are arranged sequentially, or the memory region, the first substrate, the logic region, and the second substrate are arranged sequentially. By forming the memory region and the logic region on the first substrate and the second substrate respectively, the process compatibility issues between the memory region and the logic region can be improved. Simultaneously, the occupied area of ​​the memory region can be increased, thereby increasing the storage density. Furthermore, bonding from the side of the first substrate away from the memory region, or from the side of the second substrate away from the logic region, can reduce the bonding line length, lower power consumption, and thus improve chip performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] A microcontroller unit (MCU), also known as a single-chip microcomputer or microcontroller, is a chip-level computer that integrates a central processing unit (CPU) with a reduced frequency and specifications, along with peripheral interfaces such as memory, timer, USB, A / D converter, UART, PLC, DMA, and even LCD driver circuitry, all onto a single chip. The MCU chip structure can be divided into a non-volatile FLASH memory area and a logic / periphery area.

[0003] In related technologies, traditional MCU architectures require compatibility between the non-volatile FLASH memory region and the logic / periphery region in terms of process technology. As technology nodes advance, gate heights are continuously reduced. When the logic region reaches 28nm, polygates are no longer used. Instead, technologies such as HKMG are adopted, using HK dielectric layers and metal materials for the gate. Meanwhile, the FLASH region uses polysilicon for the gate. This difference between the logic and FLASH structures is significant. In this case, it is difficult to process the logic and FLASH regions together, and the processes are incompatible. Therefore, it is difficult to scale down the non-volatile FLASH memory region synchronously, which limits the further development of MCU technology nodes and makes it difficult to meet the needs of higher-performance MCUs. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor device and a method for fabricating the same, which improves the process compatibility issues of MCU architecture and increases storage density, thereby at least partially solving the aforementioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor device is provided, comprising: The substrate structure includes a first substrate and a second substrate; Storage area, disposed on the first substrate; and The logic area is located on the second substrate; The storage area and the logic area are bonded and packaged such that the logic area, the second substrate, the storage area and the first substrate are arranged in sequence, or the storage area, the first substrate, the logic area and the second substrate are arranged in sequence.

[0006] Optionally, the storage area and the logic area are interconnected by hybrid bonding metal to form a package structure between the storage area and the second substrate, or a package structure is formed between the logic area and the first substrate.

[0007] Optionally, the storage region includes a first metal layer and a plurality of second metal layers located on the side of the first metal layer opposite to the first substrate, and the logic region includes a third metal layer and a plurality of fourth metal layers located on the side of the third metal layer opposite to the second substrate, wherein the first metal layer and the third metal layer are interconnected by a hybrid bonding metal.

[0008] Optionally, the technology node of the logical region is less than 28nm.

[0009] Optionally, the storage region includes a storage transistor array, a first dielectric layer formed on the first substrate and the storage transistor array, a first metal layer formed on the first dielectric layer, and a plurality of second metal layers located on the first metal layer. A first dielectric layer is disposed between the first metal layer and the second metal layers, and between two adjacent second metal layers. A first contact hole is formed on the first dielectric layer for electrically connecting the first metal layer and the first substrate. A first channel hole is formed on the first dielectric layer for metal interconnecting the first metal layer and adjacent second metal layers, as well as two adjacent second metal layers.

[0010] Optionally, the logic region includes a logic transistor array, a second dielectric layer formed on the second substrate and the logic transistor array, a third metal layer formed on the second dielectric layer, and a plurality of fourth metal layers located on the third metal layer. A second dielectric layer is disposed between the third metal layer and the fourth metal layers, and between two adjacent fourth metal layers. A second contact hole is formed on the second dielectric layer for electrically connecting the third metal layer and the second substrate. A second channel hole is formed on the second dielectric layer for metal interconnecting the third metal layer and the adjacent fourth metal layers, as well as two adjacent fourth metal layers.

[0011] Optionally, the storage region includes a third channel via formed in the first substrate and the first dielectric layer for metal interconnection between the first metal layer and the third metal layer; or, The logic region includes a fourth channel hole formed in the second substrate and the second dielectric layer for metal interconnection of the third metal layer and the first metal layer.

[0012] According to a second aspect of this disclosure, a method for fabricating a semiconductor device is provided, the semiconductor device comprising: The substrate structure includes a first substrate and a second substrate; Storage area, disposed on the first substrate; and The logic area is located on the second substrate; The method includes: Provide the first substrate and the second substrate; The storage area is disposed on the first substrate; The logic region is disposed on the second substrate; The bonding package interconnects the memory region and the logic region with metal, such that the logic region, the second substrate, the memory region, and the first substrate are arranged in sequence, or the memory region, the first substrate, the logic region, and the second substrate are arranged in sequence.

[0013] Optionally, setting the storage area on the first substrate includes: A storage transistor array is disposed on the first substrate; A first dielectric layer is formed on the first substrate and the memory transistor array; A first metal layer is formed on the first dielectric layer; Multiple first dielectric layers and multiple second metal layers are alternately formed on the first metal layer; The step of setting the logic region on the second substrate includes: A logic transistor array is disposed on the second substrate; A second dielectric layer is formed on the second substrate and the logic transistor array; A third metal layer is formed on the second dielectric layer; Multiple second dielectric layers and multiple fourth metal layers are alternately formed on the third metal layer.

[0014] Optionally, the metal interconnection of the memory area and the logic area via bonding packaging includes: A fourth channel hole is formed on the second substrate and the second dielectric layer; The third metal layer and the first metal layer are interconnected by hybrid bonding packaging; or... A third channel hole is formed on the first substrate and the first dielectric layer; The first metal layer and the third metal layer are interconnected by hybrid bonding packaging.

[0015] The above technical solution involves molding the memory area and logic area onto the first substrate and the second substrate, respectively. This improves the process compatibility between the memory area and the logic area, while also increasing the footprint of the memory area and thus increasing storage density. Furthermore, bonding and packaging the memory area and logic area, with the logic area positioned above the memory area (i.e., the logic area, the second substrate, the memory area, and the first substrate arranged sequentially), or vice versa (i.e., the memory area, the first substrate, the logic area, and the second substrate arranged sequentially), reduces bonding wire length, lowers power consumption, and thereby improves chip performance.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of another overall structure of the semiconductor device provided in an exemplary embodiment of this disclosure; Figures 3 to 7 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this disclosure.

[0018] Explanation of reference numerals in the attached figures 10. Semiconductor devices; 1. Substrate structure; 11. First substrate; 12. Second substrate; 2. Storage region; 21. First metal layer; 22. Second metal layer; 23. Storage transistor array; 24. First dielectric layer; 241. First contact hole; 25. First dielectric layer; 251. First channel hole; 26. Third channel hole; 3. Logic region; 31. Third metal layer; 32. Fourth metal layer; 33. Logic transistor array; 34. Second dielectric layer; 341. Second contact hole; 35. Second dielectric layer; 351. Second channel hole; 36. Fourth channel hole; 4. Packaging structure. Detailed Implementation

[0019] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0020] In this disclosure, unless otherwise stated, "inner" and "outer" refer to the interior and exterior of the outline of the corresponding component; "far" and "near" refer to the distance of the corresponding component relative to another component in terms of spatial position. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0021] According to the first aspect of this disclosure, reference to Figure 1 and Figure 2 As shown, this disclosure provides a semiconductor device 10, including a substrate structure 1, a storage region 2, and a logic region 3. The substrate structure 1 includes a first substrate 11 and a second substrate 12. The storage region 2 is disposed on the first substrate 11, and the logic region 3 is disposed on the second substrate 12. The storage region 2 and the logic region 3 are bonded and packaged so that the logic region 3, the second substrate 12, the storage region 2, and the first substrate 11 are arranged sequentially, or the storage region 2, the first substrate 11, the logic region 3, and the second substrate 12 are arranged sequentially.

[0022] By employing the aforementioned technical solution, the storage region 2 and the logic region 3 are respectively formed on the first substrate 11 and the second substrate 12, thereby improving the process compatibility issues between the storage region 2 and the logic region 3, while also increasing the occupied area of ​​the storage region 2 and increasing the storage density. Furthermore, by bonding and encapsulating the storage region 2 and the logic region 3, with the logic region 3 positioned above the storage region 2 (i.e., the logic region 3, the second substrate 12, the storage region 2, and the first substrate 11 arranged sequentially), or with the storage region 2 positioned above the logic region 3 (i.e., the storage region 2, the first substrate 11, the logic region 3, and the second substrate 12 arranged sequentially), the bonding wire length can be reduced, power consumption lowered, and chip performance improved.

[0023] In some embodiments, reference Figure 1 As shown, storage region 2 and logic region 3 can be interconnected via hybrid bonding metals to form a package structure 4 between storage region 2 and the second substrate 12, or, refer to Figure 2 As shown, an encapsulation structure 4 is formed between the logic region 3 and the first substrate 11. Thus, the memory region 2 and the logic region 3 can be encapsulated through hybrid bonding to achieve metal interconnection between the memory region 2 and the logic region 3, wherein, reference... Figure 1 If logic region 3 is located above storage region 2, then package structure 4 is located between storage region 2 and the second substrate 12, as shown in the reference. Figure 2 If the storage region 2 is located above the logic region 3, then the package structure 4 is located between the logic region 3 and the first substrate 11. Furthermore, by performing metal wire bonding from the side of the first substrate 11 away from the storage region 2, or from the side of the second substrate 12 away from the logic region 3, the metal wire length can be reduced, power consumption lowered, and chip performance improved.

[0024] In some embodiments, reference Figure 1 and Figure 2 As shown, the storage region 2 may include a first metal layer 21 and a plurality of second metal layers 22 located on the side of the first metal layer 21 facing away from the first substrate 11, and the logic region 3 may include a third metal layer 31 and a plurality of fourth metal layers 32 located on the side of the third metal layer 31 facing away from the second substrate. The first metal layer 21 and the third metal layer 31 are interconnected by a hybrid bonding metal. Thus, according to reference Figure 1 If logic region 3 is located above memory region 2, then package structure 4 is located between memory region 2 and the second substrate 12. Metal interconnects pass through the side of the second substrate 12 away from logic region 3 and are interconnected to the third metal layer 31. This eliminates the need for multiple fourth metal layers 32 above the third metal layer 31, shortening the metal line length, reducing power consumption, and improving chip performance. Similarly, refer to... Figure 2 If the storage area 2 is located above the logic area 3, the package structure 4 is located between the logic area 3 and the first substrate 11. The metal interconnects pass through the side of the first substrate 11 away from the storage area 2 and are interconnected with the first metal layer 21. There is no need to pass through multiple second metal layers 22 above the first metal layer 21. Similarly, the metal line length can be shortened, power consumption can be reduced, and chip performance can be improved.

[0025] In some embodiments, reference Figure 1 and Figure 2 As shown, the technology node of logic region 3 can be smaller than 28nm. It should be noted that logic region 3 below 28nm requires process technologies such as HKMG (High-K Metal Gate), FDSOI (Fully Depleted Silicon-on-Insulator), FINFET (Fin Field-Effect Transistor), and GAA (Gate-All-Around). These process technologies differ significantly from those of memory region 2, making it difficult to scale memory region 2 synchronously. This incompatibility between logic region 3 and memory region 2 limits the further development of MCU technology nodes and makes it difficult to meet the demands of higher-performance MCUs.

[0026] In this disclosure, the HKMG process is exemplarily employed. The HKMG process refers to replacing the traditional SiO2 or SiO with a high-k dielectric material (High-K material, commonly HfO2) in the gate oxide. NWithout changing the equivalent oxide thickness (EOT), increasing the physical thickness improves the quantum tunneling effect. Replacing the traditional polysilicon gate with a metal gate mitigates silicon depletion. Forming memory region 2 and logic region 3 on the first substrate 11 and the second substrate 12 respectively improves process compatibility between them and increases the occupied area of ​​memory region 2, thereby increasing storage density. Of course, logic region 3 can also employ technologies such as FDSOI, FINFET, and GAA, and this disclosure is not limited to these.

[0027] In some embodiments, reference Figure 1 and Figure 2 As shown, this disclosure exemplarily sets the storage area 2 as a floating gate structure. Specifically, the storage area 2 may include a storage transistor array 23, a first dielectric layer 24 formed on the first substrate 11 and the storage transistor array 23, a first metal layer 21 formed on the first dielectric layer 24, and a plurality of second metal layers 22 located on the first metal layer 21. A first contact hole 241 is formed on the first dielectric layer 24 for electrically connecting the first metal layer 21 and the first substrate 11.

[0028] The storage transistor array 23 mainly includes a floating gate and a control gate. The floating gate is used to store charge and change the threshold voltage. The control gate is used to control the charge injection and release on the floating gate. Charge is injected into the floating gate through tunneling effect or hot electron injection, and charge is released from the floating gate through tunneling effect.

[0029] In addition, the first contact hole 241 may be filled with, for example, tungsten metal to electrically connect the first substrate 11 and the first metal layer 21. Its main purpose is to realize the electrical connection between the source and drain of the first substrate 11 and the first metal layer 21. That is, the first contact hole 241 acts as a bridge between the first substrate 11 and the first metal layer 21, ensuring that electrical signals can be transferred from the first substrate 11 to the first metal layer 21, or interconnected from the first metal layer 21 to the first substrate 11.

[0030] It is understandable that as the complexity of integrated circuits increases, using only one layer of metal interconnect is no longer sufficient to meet the needs. Existing integrated circuits have more metal layers. For example, the memory region 2 may include a first metal layer 21 and a plurality of second metal layers 22 located above the first metal layer 21. A first dielectric layer 25 is disposed between the first metal layer 21 and the second metal layer 22, and between two adjacent second metal layers 22. A first channel hole 251 is formed on the first dielectric layer 25 for metal interconnection between the first metal layer 21 and the adjacent second metal layer 22, and between two adjacent second metal layers 22. The first channel hole 251 may be filled with copper or tungsten to have electrical and thermal conductivity.

[0031] Furthermore, in some other possible alternative embodiments not shown in the accompanying drawings, the storage area 2 may also be configured as a charge trapping structure, and this disclosure is not limited thereto.

[0032] In some embodiments, reference Figure 1 and Figure 2 As shown, the logic region 3 may include a logic transistor array 33, a second dielectric layer 34 formed on the second substrate 12 and the logic transistor array 33, a third metal layer 31 formed on the second dielectric layer 34, and a plurality of fourth metal layers 32 located on the third metal layer 31. A second contact hole 341 is formed on the second dielectric layer 34 for electrically connecting the third metal layer 31 and the second substrate 12.

[0033] The logic transistor array 33 mainly comprises a gate oxide layer made of high dielectric constant material and a metal gate. Compared to traditional silicon dioxide gate oxide layers, high dielectric constant materials can provide a higher effective dielectric constant at the same physical thickness, thereby reducing gate leakage current and allowing for the use of a thinner gate oxide layer, thus improving the transistor's drive current and performance. The metal gate provides better control over the threshold voltage, reducing fluctuations caused by doping. Furthermore, the metal gate has lower resistivity, reducing gate resistance and improving the transistor's switching speed. Additionally, the metal gate exhibits better stability at high temperatures, reducing reliability issues.

[0034] Furthermore, the second contact hole 341 may be filled with, for example, tungsten metal to connect the second substrate 12 and the third metal layer 31. Its main purpose is to realize the electrical connection between the source and drain of the second substrate 12 and the third metal layer 31. In other words, the second contact hole 341 acts as a bridge between the second substrate 12 and the third metal layer 31, ensuring that electrical signals can be transferred from the second substrate 12 to the third metal layer 31, or interconnected from the third metal layer 31 to the second substrate 12.

[0035] Similarly, a second dielectric layer 35 is provided between the third metal layer 31 and the fourth metal layer 32, and between two adjacent fourth metal layers 32. A second channel hole 351 is formed on the second dielectric layer 35 for metal interconnection between the third metal layer 31 and the adjacent fourth metal layer 32 and between two adjacent fourth metal layers 32. The second channel hole 351 can be filled with copper or tungsten to have electrical and thermal conductivity.

[0036] In some embodiments, reference Figure 2 As shown, if the storage area 2 is located above the logic area 3, the storage area 2 may include a third channel hole 26 formed on the first substrate 11 and the first dielectric layer 24. In this way, the storage area 2 and the logic area 3 are packaged by hybrid bonding. At this time, the package structure 4 is disposed between the logic area 3 and the first substrate 11. The third channel hole 26 can be formed on the first substrate 11 and the first dielectric layer 24 to fill with copper or tungsten metal, so as to facilitate the bonding of metal interconnects by hybrid bonding, for metal interconnection of the first metal layer 21 and the third metal layer 31.

[0037] Similarly, refer to Figure 1 As shown, if logic region 3 is located above storage region 2, logic region 3 includes a fourth channel hole 36 formed on the second substrate 12 and the second dielectric layer 34. Thus, storage region 2 and logic region 3 are packaged by hybrid bonding. At this time, the package structure 4 is disposed between storage region 2 and the second substrate 12. At this time, the fourth channel hole 36 can be formed on the second substrate 12 and the second dielectric layer 34 to fill with copper or tungsten metal, so as to facilitate the bonding of metal interconnects by hybrid bonding, for metal interconnection of the third metal layer 31 and the first metal layer 21.

[0038] It should be noted that the metal interconnection achieved by the formation of the third channel hole 26 and the fourth channel hole 36 and the filling of metal can be carried out during the forming process of the storage area 2 or the logic area 3, or it can be formed by hybrid bonding. This disclosure is not limited thereto.

[0039] According to the second aspect of this disclosure, reference to Figures 3 to 7 As shown, a method for fabricating a semiconductor device 10 is provided. The semiconductor device 10 includes a substrate structure 1, a storage region 2, and a logic region 3. The substrate structure 1 includes a first substrate 11 and a second substrate 12. The storage region 2 is disposed on the first substrate 11, and the logic region 3 is disposed on the second substrate 12. The method for fabricating the semiconductor device 10 includes steps S100 to S400.

[0040] In step S100, a first substrate 11 and a second substrate 12 are provided; In step S200, a storage area 2 is provided on the first substrate 11; In step S300, a logic region 3 is formed on the second substrate 12; In step S400, the bonding package interconnects the metal interconnect memory region 2 and the logic region 3, such that the logic region 3, the second substrate 12, the memory region 2 and the first substrate 11 are arranged in sequence, or the memory region 2, the first substrate 11, the logic region 3 and the second substrate 12 are arranged in sequence.

[0041] Using the above method, a first substrate 11 and a second substrate 12 are provided. A storage region 2 is formed on the first substrate 11, and a logic region 3 is formed on the second substrate 12. The semiconductor device 10 is then fabricated by bonding and packaging. If the logic region 3 is located above the storage region 2, the logic region 3, the second substrate 12, the storage region 2, and the first substrate 11 are arranged sequentially. If the storage region 2 is located above the logic region 3, the storage region 2, the first substrate 11, the logic region 3, and the second substrate 12 are arranged sequentially. The first substrate 11 and the second substrate 12 can be silicon substrates, silicon-germanium substrates, silicon carbide substrates, or silicon-coated insulating substrates; this disclosure is not limited to these.

[0042] In some embodiments, reference Figure 4 As shown, step S200 of setting the storage area 2 on the first substrate 11 includes steps S201 to S204: In step S201, a storage transistor array 23 is disposed on the first substrate 11; In step S202, a first dielectric layer 24 is formed on the first substrate 11 and the storage transistor array 23; In step S203, a first metal layer 21 is formed on the first dielectric layer 24; In step S204, a plurality of first dielectric layers 25 and a plurality of second metal layers 22 are alternately formed on the first metal layer 21; refer to Figure 5 As shown, step S300 of setting the logic region 3 on the second substrate 12 includes steps S301 to S304: In step S301, a logic transistor array 33 is disposed on the second substrate 12; In step S302, a second dielectric layer 34 is formed on the second substrate 12 and the logic transistor array 33; In step S303, a third metal layer 31 is formed on the second dielectric layer 34; In step S304, a plurality of second dielectric layers 35 and a plurality of fourth metal layers 32 are alternately formed on the third metal layer 31.

[0043] Thus, in step S201, the memory collective array mainly includes a floating gate and a control gate. The floating gate can be formed by depositing crystalline silicon, for example, using chemical vapor deposition (CVD). During this process, doping (typically using phosphorus or boron) can further enhance the conductivity of the crystalline silicon. The control gate is formed by depositing crystalline silicon on the top surface of the floating gate using, for example, chemical vapor deposition (CVD). During this process, doping (typically using phosphorus or boron) can further enhance the conductivity of the crystalline silicon.

[0044] In step S202, a first contact hole 241 is formed on the first dielectric layer 25 and filled with metal to electrically connect the first substrate 11 and the first metal layer 21 above it.

[0045] In step S203, the first metal layer 21 is electrically connected to the first substrate 11 through the first contact hole 241 and metal interconnects the plurality of second metal layers 22 above it.

[0046] In step S204, a first channel hole 251 is formed on the first dielectric layer 25 for metal interconnection of the first metal layer 21 and the adjacent second metal layer 22, as well as two adjacent second metal layers 22.

[0047] In step S301, the first substrate 11 is exposed to an oxygen environment at a high temperature to form a thin and uniform silicon dioxide layer, which is used as the initial gate oxide layer. For the HKMG process, this oxide layer may be completely removed or partially retained as an interface layer. A high dielectric constant material is deposited on the substrate using an ALD (atomic layer deposition) process.

[0048] Based on the required threshold voltage, an appropriate work function adjustment material is deposited, followed by the deposition of the main metal material, such as W and Ru, to form the final metal gate. The surface of the metal gate is planarized through a chemical mechanical polishing (CMP) process to ensure good interconnect performance.

[0049] In step S302, a second contact hole 341 is formed on the second dielectric layer 35 and filled with metal to electrically connect the second substrate 12 and the upper third metal layer 31.

[0050] In step S303, the third metal layer 31 is electrically connected to the first substrate 11 through the second contact hole 341 and metal interconnects the plurality of fourth metal layers 32 above it.

[0051] In step S304, a second channel hole 351 is formed on the second dielectric layer 35 for metal interconnection of the third metal layer 31 and the adjacent fourth metal layer 32, as well as two adjacent fourth metal layers 32.

[0052] In some embodiments, reference Figure 6 and Figure 7As shown, step S400, which involves bonding and encapsulating the memory region 2 and logic region 3 with metal interconnects, such that the logic region 3, the second substrate 12, the memory region 2, and the first substrate 11 are arranged sequentially, or the memory region 2, the first substrate 11, the logic region 3, and the second substrate 12 are arranged sequentially, includes steps S401 to S402: In step S401, a fourth channel hole 36 is formed on the second substrate 12 and the second dielectric layer 34; In step S402, the third metal layer 31 and the first metal layer 21 are interconnected by hybrid bonding encapsulation; Thus, for reference Figure 1 and Figure 6 As shown, if logic region 3 is located above storage region 2, in step S401, a fourth channel hole 36 is formed on the second substrate 12 and the second dielectric layer 34 and filled with metal for metal interconnection of the third metal layer 31 and the first metal layer 21.

[0053] In step S402, metal interconnects are bonded by hybrid bonding for use in metal interconnecting the third metal layer 31 and the first metal layer 21.

[0054] or, In step S401, a third channel hole 26 is formed on the first substrate 11 and the first dielectric layer 24; In step S402, the first metal layer 21 and the third metal layer 31 are interconnected by hybrid bonding encapsulation.

[0055] Thus, for reference Figure 2 and Figure 7 If the storage area 2 is located above the logic area 3, in step S401, a third channel hole 26 is formed on the first substrate 11 and the first dielectric layer 24 and filled with metal for metal interconnection of the first metal layer 21 and the third metal layer 31.

[0056] In step S402, metal interconnects are bonded by hybrid bonding for metal interconnecting the first metal layer 21 and the third metal layer 31.

[0057] The semiconductor device 10 of this embodiment can be obtained through the above steps, such as... Figure 1 and Figure 2 As shown, compared with related technologies, in the structure of the semiconductor device 10 disclosed herein, the memory region 2 and the logic region 3 are respectively formed on the first substrate 11 and the second substrate 12, which can improve the process compatibility issues between the memory region 2 and the logic region 3, and at the same time increase the occupied area of ​​the memory region 2, thereby increasing the storage density. Furthermore, bonding and packaging from the side of the first substrate 11 away from the memory region 2 or the side of the second substrate 12 away from the logic region 3 can reduce the bonding wire length, lower power consumption, and thus improve chip performance.

[0058] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0059] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0060] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor device, characterized in that, include: The substrate structure includes a first substrate and a second substrate; The storage area is located on the first substrate; as well as The logic area is located on the second substrate; The storage area and the logic area are bonded and packaged such that the logic area, the second substrate, the storage area and the first substrate are arranged in sequence, or the storage area, the first substrate, the logic area and the second substrate are arranged in sequence.

2. The semiconductor device according to claim 1, characterized in that, The storage area and the logic area are interconnected by hybrid bonding metal to form a package structure between the storage area and the second substrate, or between the logic area and the first substrate.

3. The semiconductor device according to claim 2, characterized in that, The storage area includes a first metal layer and a plurality of second metal layers located on the side of the first metal layer opposite to the first substrate, and the logic area includes a third metal layer and a plurality of fourth metal layers located on the side of the third metal layer opposite to the second substrate. The first metal layer and the third metal layer are interconnected by a hybrid bonding metal.

4. The semiconductor device according to claim 1, characterized in that, The technology node of the logical region is less than 28nm.

5. The semiconductor device according to claim 3, characterized in that, The storage region includes a storage transistor array, a first dielectric layer formed on the first substrate and the storage transistor array, a first metal layer formed on the first dielectric layer, and a plurality of second metal layers located on the first metal layer. A first dielectric layer is disposed between the first metal layer and the second metal layers, and between two adjacent second metal layers. A first contact hole is formed on the first dielectric layer for electrically connecting the first metal layer and the first substrate. A first channel hole is formed on the first dielectric layer for metal interconnecting the first metal layer and adjacent second metal layers, as well as two adjacent second metal layers.

6. The semiconductor device according to claim 5, characterized in that, The logic region includes a logic transistor array, a second dielectric layer formed on the second substrate and the logic transistor array, a third metal layer formed on the second dielectric layer, and a plurality of fourth metal layers located on the third metal layer. A second dielectric layer is disposed between the third metal layer and the fourth metal layers, and between two adjacent fourth metal layers. A second contact hole is formed on the second dielectric layer for electrically connecting the third metal layer and the second substrate. A second channel hole is formed on the second dielectric layer for metal interconnecting the third metal layer and the adjacent fourth metal layers, as well as two adjacent fourth metal layers.

7. The semiconductor device according to claim 6, characterized in that, The storage region includes a third channel via formed in the first substrate and the first dielectric layer for metal interconnection of the first metal layer and the third metal layer; or, The logic region includes a fourth channel hole formed in the second substrate and the second dielectric layer for metal interconnection of the third metal layer and the first metal layer.

8. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes: The substrate structure includes a first substrate and a second substrate; Storage area, disposed on the first substrate; and The logic area is located on the second substrate; The method includes: Provide the first substrate and the second substrate; The storage area is disposed on the first substrate; The logic region is disposed on the second substrate; The bonding package interconnects the memory region and the logic region with metal, such that the logic region, the second substrate, the memory region, and the first substrate are arranged in sequence, or the memory region, the first substrate, the logic region, and the second substrate are arranged in sequence.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of setting the storage area on the first substrate includes: A storage transistor array is disposed on the first substrate; A first dielectric layer is formed on the first substrate and the memory transistor array; A first metal layer is formed on the first dielectric layer; Multiple first dielectric layers and multiple second metal layers are alternately formed on the first metal layer; The step of setting the logic region on the second substrate includes: A logic transistor array is disposed on the second substrate; A second dielectric layer is formed on the second substrate and the logic transistor array; A third metal layer is formed on the second dielectric layer; Multiple second dielectric layers and multiple fourth metal layers are alternately formed on the third metal layer.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The bonding package interconnects the memory area and the logic area with metal, including: A fourth channel hole is formed on the second substrate and the second dielectric layer; The third metal layer and the first metal layer are interconnected by hybrid bonding packaging; or... A third channel hole is formed on the first substrate and the first dielectric layer; The first metal layer and the third metal layer are interconnected by hybrid bonding packaging.

Images