Micro light emitting diode with multi-layer passivation layer, micro light emitting diode chip and manufacturing method thereof

Abstract

This invention discloses a high-efficiency micro-light-emitting diode, comprising a light-emitting mesa and a passivation layer covering the side of the light-emitting mesa. The passivation layer comprises multiple layers, and the refractive indices of the different layers are different. By depositing a thin film with higher density, dielectric constant, and refractive index on the inner or outer side of an existing SiO2 film, the total internal reflection at the interface between the microlens and air or the total emission loss at the interface between the light-emitting mesa and the passivation layer can be reduced, thereby improving the light extraction efficiency.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to a micro light-emitting diode with multiple passivation layers, a micro light-emitting diode chip, and a method for manufacturing the same. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) microdisplay chips are a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. They integrate arrayed micron-sized LED units on an active addressable driver panel to enable the lighting and individual control of the LED units, thereby outputting the desired display image.

[0003] In the manufacturing process of Micro LEDs, dry etching and other processes are typically used to etch the MESA (Meta-Organic Acrylic Aperture Surface). During this process, numerous defects are formed in the sidewall regions of the Micro LED, leading to a decrease in the internal quantum efficiency of small-sized Micro LED devices and resulting in sidewall defects. Sidewall defects are the primary cause of the efficiency reduction in small-sized Micro LED devices.

[0004] Passivating pixel sidewall defects is one of the key technologies for improving the performance of Micro LED displays. By passivating pixel sidewall defects, the efficiency reduction caused by sidewall defects can be effectively reduced, thereby improving the external quantum efficiency (EQE) and internal quantum efficiency (IQE). Currently, most common passivation layers are made of SiO2 material using traditional chemical vapor deposition (CVD). However, as the size of Micro LED chips continues to shrink, the sidewall area ratio increases, leading to more severe sidewall luminescence problems, making SiO2 insufficient for meeting the requirements. Specifically, after photons are emitted from the multiple quantum wells of a Micro LED, total internal reflection (tir) occurs between the emitting mesa and the passivation layer, preventing some photons from passing through. Since SiO2 has a low refractive index, its total internal reflection loss is high, which in turn affects the luminous efficiency of the Micro LED chip. Summary of the Invention

[0005] To address some or all of the problems of the prior art, the first aspect of the present invention provides a micro light-emitting diode with multiple passivation layers, comprising:

[0006] A light-emitting platform, which can be used to emit light; and

[0007] A passivation layer covers the side surface of the light-emitting platform, and the passivation layer comprises multiple layers, wherein the refractive indices of the different layers are different.

[0008] Furthermore, the passivation layer includes a first passivation layer and a second passivation layer, and the first passivation layer and the second passivation layer are formed using the same process.

[0009] Furthermore, the first passivation layer and the second passivation layer are fabricated using a chemical vapor deposition (CVD) process.

[0010] Furthermore, the first material and the second material are selected from the group consisting of:

[0011] SiO2, SiO2, Al2O3, AlN, HfO2 and SiN x .

[0012] Furthermore, the passivation layer includes a first passivation layer and a second passivation layer, and the formation processes of the first passivation layer and the second passivation layer are different.

[0013] Furthermore, the material of the first passivation layer is SiO2, and the refractive index of the material of the second passivation layer is higher than that of SiO2.

[0014] Furthermore, the material of the second passivation layer is Al2O3.

[0015] Furthermore, the first passivation layer is fabricated using chemical vapor deposition (CVD) and the second passivation layer is fabricated using atomic layer deposition (ALD).

[0016] Furthermore, the refractive index of the material of the first passivation layer is higher than that of the material of the second passivation layer.

[0017] Furthermore, the material of the first passivation layer is Al2O3, and the material of the second passivation layer is SiO2.

[0018] Furthermore, the first passivation layer is fabricated using atomic layer deposition (ALD) and the second passivation layer is fabricated using chemical vapor deposition (CVD).

[0019] Furthermore, the thickness of the passivation layer is 20 to 1000 nanometers.

[0020] Furthermore, the thickness of the first passivation layer is 20 to 500 nanometers.

[0021] Furthermore, the thickness of the second passivation layer is 20 to 500 nanometers.

[0022] Furthermore, the light-emitting mesa sequentially includes a first epitaxial layer, a light-emitting layer, and a second epitaxial layer.

[0023] Furthermore, the material of the second epitaxial layer is a material layer of the second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first conductivity type is different from the second conductivity type.

[0024] Furthermore, the light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an InGaAs / AlGaAs multi-quantum well layer.

[0025] Furthermore, an electron blocking layer is provided on the first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer.

[0026] Based on the high light-emitting efficiency micro light-emitting diodes as described above, a second aspect of the present invention provides a micro light-emitting diode chip, which includes a micro light-emitting diode array bonded to a driving backplane, wherein the micro light-emitting diode array includes a plurality of micro light-emitting diodes as described above.

[0027] Furthermore, the micro-LED array includes a continuous top conductive layer disposed above the micro-LED array and contacting and covering the top of each light-emitting platform.

[0028] Furthermore, a metal layer is provided on the surface of the driving backplane, and a plurality of IC copper pillars are provided on the driving backplane. The IC copper pillars are electrically connected to the metal layer, and each light-emitting mesa of the micro LED array area corresponds to one IC copper pillar.

[0029] Furthermore, the material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.

[0030] Furthermore, a second electrode is provided between adjacent light-emitting platforms.

[0031] Furthermore, the second electrode is a ring-shaped reflective electrode, which is disposed around the semiconductor light-emitting platform.

[0032] Furthermore, the second electrode between adjacent light-emitting mesa has at least two peaks.

[0033] Furthermore, the second electrodes are interconnected.

[0034] Furthermore, the micro LED chip also includes at least one first electrode, which is electrically connected to the IC copper pillar.

[0035] Furthermore, the polarity of the first electrode is opposite to that of the second electrode.

[0036] Furthermore, the micro-light-emitting diode chip also includes a microlens array, which is located above the micro-light-emitting diode array area and includes multiple microlenses, wherein at least one microlens is disposed on the surface of the conductive layer on top of the micro-light-emitting diode.

[0037] Furthermore, the microlens has an air gap inside.

[0038] Furthermore, there are gaps between adjacent micro-projection lenses, but they are at least partially connected.

[0039] A third aspect of the present invention provides a method for manufacturing a miniature light-emitting diode chip, comprising:

[0040] Forming a semiconductor light-emitting module;

[0041] The semiconductor light-emitting module is bonded to the driver backplane;

[0042] Step etching is performed on the semiconductor light-emitting module;

[0043] Multiple passivation layers are sequentially formed on the sidewalls and surface of each pixel, wherein the refractive indices and / or formation processes of different layer materials are different.

[0044] A photolithographic etching opening is made above the corresponding pixel to expose at least a portion of the surface at the top of the pixel;

[0045] A top conductive layer is formed on the surface of the passivation layer;

[0046] A second electrode is formed at the interval of each pixel;

[0047] A first electrode is formed on the drive backplate; and

[0048] Deposited microlenses.

[0049] Furthermore, forming the semiconductor light-emitting module includes:

[0050] A second epitaxial layer, an electron blocking layer, a multilayer quantum well, and a first epitaxial layer are sequentially deposited on the substrate.

[0051] Furthermore, the step etching of the semiconductor light-emitting module includes:

[0052] The semiconductor light-emitting module is etched to form positive trapezoidal pixel structures.

[0053] Furthermore, the horizontal angle of the pixel in the trapezoidal structure is 65° to 85°.

[0054] Furthermore, the passivation layer includes a first passivation layer and a second passivation layer, and the refractive index of the material of the first passivation layer is lower than that of the second passivation layer.

[0055] Furthermore, the first passivation layer is made of SiO2, and the second passivation layer is made of SiN. x .

[0056] Furthermore, the passivation layer includes a first passivation layer and a second passivation layer, and the refractive index and formation process of the materials of the first passivation layer and the second passivation layer are different.

[0057] Furthermore, the material of the first passivation layer is SiO2, and the material of the second passivation layer is Al2O3.

[0058] Furthermore, the first passivation layer is fabricated using chemical vapor deposition (CVD) and the second passivation layer is fabricated using atomic layer deposition (ALD).

[0059] Furthermore, the material of the first passivation layer is Al2O3, and the material of the second passivation layer is SiO2.

[0060] Furthermore, the first passivation layer is fabricated using atomic layer deposition (ALD) and the second passivation layer is fabricated using chemical vapor deposition (CVD).

[0061] Furthermore, the manufacturing method further includes:

[0062] Deep trench etching is performed at the intervals between each pixel, and the second electrode is disposed at the deep trench.

[0063] This invention provides a micro-light-emitting diode (LED) with multiple passivation layers, comprising multiple passivation layers formed by different processes and / or materials with different refractive indices. First, a SiO2 film is deposited via CVD. The strong binding energy of the Si-O bonds effectively passivates defects on the pixel sidewalls, suppressing surface recombination and non-radiative recombination of charge carriers. Then, a thin film with higher film density, dielectric constant, and refractive index, such as an Al2O3 film or SiO2 film, is deposited on the surface of the SiO2 film using an ALD process. This further prevents the intrusion of water, oxygen, etc., during subsequent processing and operation of the micro-LED. Simultaneously, because the refractive index of this thin film is higher than that of SiO2, it also changes the light emission position of light emitted from the multiple quantum well (MQW) at the pixel sidewall, causing the light emitted from above the pixel sidewall to shift upwards. This further moves the light towards the center of the microlens, reducing total internal reflection at the interface between the microlens and air, and improving the luminous efficiency of the micro-LED. In addition, a thin film with a high refractive index, such as Al2O3, can be deposited first. Since the refractive index of the light-emitting mesa is usually greater than 2, directly covering the outside of it with a material with a high refractive index can effectively reduce the total internal reflection loss at the interface between the light-emitting mesa and the passivation layer compared to directly covering it with SiO2, thereby further improving the light extraction efficiency of the micro light-emitting diode. Attached Figure Description

[0064] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0065] Figure 1 This diagram illustrates the structure of a micro light-emitting diode with multiple passivation layers according to an embodiment of the present invention.

[0066] Figure 2 This diagram illustrates a partial optical path of a micro light-emitting diode with multiple passivation layers according to an embodiment of the present invention.

[0067] Figure 3 This diagram illustrates the structure of a micro light-emitting diode with multiple passivation layers according to yet another embodiment of the present invention.

[0068] Figure 4 This diagram illustrates a partial optical path of a micro light-emitting diode with multiple passivation layers, according to yet another embodiment of the present invention.

[0069] Figure 5 This diagram illustrates the structure of a miniature light-emitting diode chip according to an embodiment of the present invention.

[0070] Figure 6 This diagram illustrates the structure of a miniature light-emitting diode chip according to yet another embodiment of the present invention.

[0071] Figures 7A to 7D A schematic diagram showing a partial topography of a micro light-emitting diode chip according to different embodiments of the present invention;

[0072] Figure 8 A schematic flowchart illustrating a method for manufacturing a miniature light-emitting diode chip according to an embodiment of the present invention; and

[0073] Figures 9A to 9I The chip state is shown after each step of the method for manufacturing a miniature light-emitting diode chip according to the present invention has been performed. Detailed Implementation

[0074] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0075] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0076] It should be noted that the embodiments of the present invention describe the process steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.

[0077] In the fabrication of micro LED chips, processes such as dry etching are required to obtain the light-emitting mesa (MESA) to form pixels. However, sidewall defects can occur during this process. Currently, chemical vapor deposition (CVD) is often used to deposit SiO2 material as a passivation layer for Micro LED pixels to passivate these sidewall defects. However, the film formed by CVD has low density, allowing external environmental pollutants such as H2O and O2 to easily penetrate the chip during operation, damaging the light-emitting mesa. Furthermore, the refractive index of SiO2 is 1.45, resulting in significant total internal reflection losses during operation and affecting light extraction efficiency. To address these issues, one approach is to replace the passivation layer with a material with a higher refractive index. Another approach is to improve the deposition process to obtain a passivation layer with higher film density. Therefore, this invention provides a micro LED with a multi-layer passivation layer, which uses different or identical processes to deposit multiple thin films with different refractive indices to form the passivation layer. For example, CVD can be used to sequentially deposit SiO2 and SiN films. x Thin films, for example, can be deposited using CVD to deposit SiO2 thin films and ALD to deposit Al2O3 thin films. If SiO2 thin films are deposited first, followed by Al2O3 and SiN films... x Materials with higher refractive indices, such as thin films, benefit from the stronger binding energy of Si-O bonds, which can effectively passivate pixel sidewall defects and suppress surface recombination and non-radiative recombination of charge carriers. This is further enhanced by ALD deposition of Al2O3 thin films or CVD deposition of SiN. x The thin film exhibits higher film density, dielectric constant, and refractive index, covering the outer layer of SiO2, which can further prevent the intrusion of water, oxygen, etc. during subsequent processing and LED operation. Simultaneously, due to the presence of Al2O3 and SiN... x The refractive index is higher than that of SiO2, which changes the light emission position of the light emitted from the multi-quantum-well (MQW) at the pixel sidewall. This is achieved by inserting Al2O3 and SiN... xThe light rays emitted from above the pixel sidewall are then deflected upwards, causing them to move further towards the center of the microlens. This reduces total internal reflection at the interface between the microlens and air, improving the luminous efficiency of the micro-LED chip. If a thin film with a high refractive index, such as Al2O3, is deposited first, followed by a SiO2 film, the refractive index of Al2O3 (1.65) and the refractive index of the emitting mesa are typically greater than 2. Directly covering the outer side of the emitting mesa with Al2O3 material, compared to directly covering it with SiO2 (1.4 refractive index), effectively reduces total internal reflection loss at the interface between the emitting mesa and the passivation layer, further improving the light extraction efficiency of the micro-LED chip. Simultaneously, the excellent film density and high dielectric constant of Al2O3 further enhance the reliability of the micro-LED chip during subsequent operation. It should be understood that in other embodiments of the present invention, the passivation layer may comprise more layers, and the materials of each layer are not limited to SiO2 and Al2O3. The deposition process for each layer can also be selected from other common deposition processes in the art, depending on the required film density and other properties. Preferably, according to the generation order, the refractive index of each layer of material decreases from bottom to top, and is not lower than 1.4.

[0078] A miniature light-emitting diode (LED) chip includes an integrated circuit (IC) backplane and an array of miniature LEDs. The miniature LED array comprises multiple miniature LEDs. Each miniature LED can form at least a portion of a pixel element on the miniature LED chip.

[0079] In embodiments of the present invention, the size of each micro-LED chip is no more than 1 cm, preferably no more than 20 micrometers. The micro-LED structures are formed in an array within the micro-LED chips, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro-LED structures is in the nanometer range, for example, from 20 nm to 100 nm.

[0080] In some embodiments of the present invention, an integrated circuit (IC) backplane may be electrically connected to each micro-light-emitting diode in a micro-light-emitting diode array via separate metal interconnects. In some embodiments, each micro-light-emitting diode may be electrically controlled individually by the IC backplane. In some embodiments, the IC backplane may be electrically connected to the electrodes of the micro-light-emitting diode chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the micro-light-emitting diodes. In some embodiments, a dielectric layer may also be formed in the gaps between interconnects.

[0081] In some embodiments of the present invention, each micro-LED in the micro-LED array may include a micrometer-scale emitting mesa structure. In some embodiments, the emitting mesa structure may include, from bottom to top, a first type epitaxial layer, an emitting layer, and a second type epitaxial layer. That is, in the three-layer structure, the first type epitaxial layer is closest to the IC backplane; the emitting layer is located above the first type epitaxial layer and further away from the IC backplane; the second type epitaxial layer is located above the emitting layer and furthest away from the IC backplane. In some embodiments, the emitting layer is formed of multiple stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The main substrate material of the first type epitaxial layer may be, but is not limited to, Ga, N, As, P, In and includes, but is not limited to, waveguide layers, confinement layers, transition layers, and window layers; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary matrix material of the second type of epitaxial layer may be, but is not limited to, composed of at least two or more elements selected from Ga, N, As, P, In, and Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer.

[0082] In some embodiments, a top conductive layer may be formed on the top surface of the micro-LED array. In some embodiments, the top conductive layer may be shared by all micro-LEDs in the micro-LED array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro-LED array may include a single-layer micro-LED structure. In some embodiments, the micro-LED array may include a multi-layer vertically stacked micro-LED structure.

[0083] In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the spacing between the micro-LED arrays, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.

[0084] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0085] Figure 1 This diagram illustrates the structure of a micro light-emitting diode with multiple passivation layers according to an embodiment of the present invention. Figure 1As shown, a micro light-emitting diode with multiple passivation layers includes a light-emitting mesa 101 and passivation layers, wherein the passivation layers cover the side surface of the light-emitting mesa 101, and the passivation layers include a first passivation layer 121 and a second passivation layer 122. In one embodiment of the present invention, the refractive indices of the materials of the first passivation layer and the second passivation layer are different. The material of the first passivation layer is SiO2, and the refractive index of the material of the second passivation layer is higher than that of SiO2. In one embodiment of the present invention, the material of the second passivation layer is Al2O3 or SiN. x In one embodiment of the present invention, the first passivation layer and the second passivation layer are fabricated using chemical vapor deposition (CVD). In another embodiment of the present invention, the first passivation layer is fabricated using chemical vapor deposition (CVD), and the second passivation layer is fabricated using atomic layer deposition (ALD). Due to Al2O3 or SiN... x The refractive index of Al2O3 is higher than that of SiO2, which changes the light emission position of the light emitted from the MQW at the pixel sidewall. This is achieved by inserting Al2O3 or SiN. x The light rays emitted from above the pixel sidewall are then deflected upwards, causing them to move further towards the center of the microlens, such as... Figure 2 As shown, this can effectively reduce total internal reflection at the interface between the microlens and air, thereby improving luminous efficiency. In one embodiment of the present invention, the thickness of the passivation layer is 20 nm to 1000 nm. The thicknesses of the first and second passivation layers are respectively in the range of 20 to 500 nm.

[0086] Figure 3 This diagram illustrates the structure of a micro light-emitting diode with multiple passivation layers, according to yet another embodiment of the present invention. Its structure is similar to... Figure 1 The embodiments shown are basically the same, except that the order of the first passivation layer and the second passivation layer is the same as that shown. Figure 1 The embodiments shown are the opposite. That is, in some embodiments of the present invention, the refractive index of the material of the first passivation layer 321 is higher than the refractive index of the material of the second passivation layer 322. In one embodiment of the present invention, the material of the first passivation layer is Al2O3, and the material of the second passivation layer is SiO2. Simultaneously, the first passivation layer is fabricated using atomic layer deposition (ALD), and the second passivation layer is fabricated using chemical vapor deposition (CVD). In one embodiment of the present invention, both the first and second passivation layers can be fabricated using the same deposition process. Depositing a material with a higher refractive index first can reduce the total internal reflection loss at the interface between the light-emitting platform and the passivation layer, and its optical path is as follows... Figure 4 As shown.

[0087] In some embodiments of the present invention, the passivation layer also covers a portion of the top surface of the light-emitting platform, specifically, it covers the edge portion of the top surface of the light-emitting platform.

[0088] Based on the high light extraction efficiency of the micro light-emitting diodes mentioned above, Figure 5 and Figure 6 Schematic diagrams of the structures of micro light-emitting diode chips according to different embodiments of the present invention are shown. As shown in the figures, the micro light-emitting diode chip according to the present invention includes a micro light-emitting diode array, which includes a plurality of micro light-emitting diodes as described above. The micro light-emitting diode array is bonded to a driving backplane 501 through a metal bonding layer 502.

[0089] In one embodiment of the present invention, the micro light-emitting diode array includes multiple light-emitting mesa and a continuous top conductive layer 505.

[0090] In one embodiment of the present invention, as shown in the figure, the semiconductor light-emitting mesa includes a first epitaxial layer 531, a light-emitting layer 532, and a second epitaxial layer 533 deposited sequentially, wherein the light-emitting layer includes a multi-quantum well layer and an electron blocking layer. In one embodiment of the present invention, the light-emitting mesa of each micro-LED in the micro-LED array can be a micrometer-scale light-emitting mesa. In one embodiment of the present invention, the micrometer-scale light-emitting mesa may include, from bottom to top, a first type epitaxial layer, a light-emitting layer, and a second type epitaxial layer. That is, in the three-layer structure, the first type epitaxial layer is closest to the driving backplane; the light-emitting layer is located above the first type epitaxial layer and further away from the driving backplane; the second type epitaxial layer is located above the light-emitting layer and furthest away from the driving backplane. In one embodiment of the present invention, the light-emitting layer is formed by multiple stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In one embodiment of the present invention, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The primary substrate material of the first type of light-emitting mesa may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; additionally, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type of epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary substrate material of the second type of epitaxial layer may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the second type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in one embodiment of the invention, an ohmic contact layer may be formed on the confinement layer. In one embodiment of the invention, the first conductivity type is different from the second conductivity type.

[0091] In one embodiment of the present invention, the first epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second epitaxial layer can be a material layer of a second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer can be a material layer of a first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P. The multiple quantum well layer is an InGaN / GaN multiple quantum well layer, an InGaN / AlGaN multiple quantum well layer, or an InGaAs / AlGaAs multiple quantum well layer. The electron blocking device is disposed on a first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment of the present invention, the first epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0092] In one embodiment of the present invention, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1- y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the light-emitting layer is a multiple quantum well (MQW).

[0093] In embodiments of the present invention, one of the first type epitaxial layer and the second type epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer. The doped N-type contact layer is configured to be bonded to a bonding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al. x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. Furthermore, in these embodiments, the thickness of the N-type cladding layer is no greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e⁻¹. 17 cm -3 up to 1e 18 cm -3In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer formed on the doped N-type contact layer. The doped N-type contact layer is configured to be bonded to the bonding layer. The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e⁻¹. 18 cm -3 up to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm. In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer.

[0094] In some embodiments, the material of the P-type coating is Al. x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type coating is no greater than 380 nm, for example, the thickness of the P-type coating is 360 nm.

[0095] In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0096] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first-doped P-type transition layer formed on the P-type cladding layer, and a second-doped P-type transition layer formed on the first-doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0097] In some embodiments, the material of the first doped P-type transition layer is (Al) x Ga 1-x ) y In 1-y P, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example, 30 nm.

[0098] In some embodiments, the material of the second doped P-type transition layer is Al. x Ga 1-x As, where x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0099] In some embodiments, the doping concentration of the second-doped P-type transition layer is greater than the doping density of the first-doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second-doped P-type transition layer.

[0100] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second-doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second-doped P-type transition layer is 2 to 4 times that of the first-doped P-type transition layer.

[0101] For example, the doping concentration of the first doped P-type transition layer is greater than 1e. 18 cm -3 The doping density of the second-doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 Within the range, the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0102] Figures 7A to 7D A schematic diagram showing a partial topography of a micro light-emitting diode chip according to different embodiments of the present invention is provided. As shown in the figure, the semiconductor light-emitting mesa is stepped (…). Figure 7A and 7C ) or trapezoidal ( Figure 7B and 7D ).

[0103] In one embodiment of the present invention, the light-emitting platform can be arranged on the driving panel 501 in a regular or irregular manner as the pixel of the micro light-emitting diode chip.

[0104] The continuous top conductive layer 505 is disposed above the micro light-emitting diode array and contacts and covers the top of each light-emitting mesa. It is in electrical contact with the second epitaxial layer 533 of the light-emitting mesa, so as to connect the second epitaxial layers of each semiconductor light-emitting mesa in series. It is a transparent conductive layer.

[0105] As shown in the figure, there are gaps between the pixels formed by the various semiconductor light-emitting mesa, and a second electrode 506 is disposed at each gap, and the second electrode 506 is disposed on the surface of the continuous top conductive layer 505. In one embodiment of the present invention, the second electrode 506 is a ring-shaped reflective electrode, disposed around the light-emitting mesa, and is formed by magnetron sputtering or vapor deposition. Its material can be, for example, Al or Al alloy metal for the sidewall reflective mirrors, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au, or other metal materials. In one embodiment of the present invention, the second electrodes are interconnected.

[0106] like Figure 7A and 7C As shown, in some embodiments of the present invention, a deep trench is provided at the partition between two adjacent light-emitting mesa surfaces. The deep trench penetrates the micro-light-emitting diode array; specifically, it penetrates the bottom stack of the partition, and the second electrode 506 is disposed at the deep trench. As shown, in one embodiment of the present invention, the second electrode between adjacent light-emitting mesa surfaces has at least two peaks. Figure 7B and 7D As shown, in some embodiments of the present invention, deep trenches are not provided at the interval between two adjacent light-emitting platforms, but a passivation isolation layer and a continuous top conductive layer are directly formed. Therefore, the surface of the continuous top conductive layer between two adjacent light-emitting platforms is a horizontal or substantially horizontal plane. The second electrode is formed here, and its morphological interface is trapezoidal or approximately trapezoidal. The surface of the second electrode is not higher than the highest point of the continuous top conductive layer.

[0107] As previously described, the surface and sides of the light-emitting platform are covered with multiple passivation layers, but at least a portion of the surface of the second epitaxial layer 533 is exposed. The top conductive layer 505 is disposed on the surface of the passivation layers. The passivation layers not only reduce current leakage at the sidewalls but also passivate sidewall defects and prevent damage to the light-emitting platform from water, oxygen, etc., during operation. Figure 5 In the illustrated embodiment, the first passivation layer 541 is made of SiO2 material deposited using a CVD process, and the second passivation layer 542 is made of Al2O3 material deposited using an ALD process, or SiN material deposited using a CVD process. x Made of materials. Figure 6In the embodiment shown, the first passivation layer 641 is made of Al2O3 material deposited by ALD process, and the second passivation layer 642 is made of SiO2 material deposited by CVD process.

[0108] like Figure 7A and 7B As shown, in some embodiments of the present invention, the passivation layer only covers the side surface of the light-emitting platform, but not the top surface, and the highest point of the passivation layer is flush with the top surface of the light-emitting platform. In these embodiments, the continuous top conductive layer covering the top of the light-emitting platform is horizontal or substantially horizontal in planar shape. And as... Figure 7C and 7D As shown, in some embodiments of the present invention, the passivation layer not only covers the side surface of the light-emitting platform, but also covers the top edge of the light-emitting platform, and thus has a protrusion at the top edge of the light-emitting platform, so that the continuous top conductive layer 505 covering it also forms a protrusion at the top edge of the light-emitting platform.

[0109] In one embodiment of the present invention, the driving backplane 501 includes a substrate, a driving circuit, and IC copper pillars 511 connected to the driving circuit, and the micro-light-emitting diode array is electrically connected to the IC copper pillars 511. The substrate may be a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is approximately 700 micrometers thick. The driving circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device. As shown, the IC copper pillars 511 include a first IC copper pillar and a second IC copper pillar, wherein the first IC copper pillar is electrically connected to a first epitaxial layer of the semiconductor light-emitting module, and the second IC copper pillar is electrically connected to a first electrode 507. In one embodiment of the present invention, the polarity of the first electrode is opposite to that of the second electrode. In one embodiment of the present invention, each semiconductor light-emitting module has a common first electrode. The first electrode may be, for example, a P electrode or an anode electrode, and the second electrode is an electrode with a polarity opposite to that of the first electrode, such as an N electrode or a cathode electrode. In one embodiment of the invention, the first and second electrodes and their connecting components may be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO), or any combination thereof. In another embodiment of the invention, the first and second electrodes and their connecting components may be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO).

[0110] As shown in the figure, in one embodiment of the present invention, the micro-light-emitting diode chip further includes a microlens array. The microlens array is disposed above the micro-light-emitting diode array, wherein at least one microlens 508 is disposed on the surface of the conductive layer on top of the micro-light-emitting diode, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-light-emitting diode. The microlens is mainly used for focusing and / or collimating optical fibers; for example, the focal point of the microlens can be located in the light-emitting mesa of the micro-light-emitting diode by adjusting parameters such as the thickness and curvature of the microlens.

[0111] As shown in the figure, in one embodiment of the present invention, the microlenses of the microlens array correspond one-to-one with the light-emitting platform. Meanwhile, as... Figure 7A and 7B As shown, in some embodiments of the present invention, adjacent microlenses have gaps between them and their bottoms are connected to each other. The bottom of the gap may be lower than the top of the light-emitting platform of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting platform, or located above the second electrode, or located between the two peaks of the second electrode. Figure 7C and 7D As shown, in some other embodiments of the present invention, adjacent microlenses are completely connected, but there is a gap at the connection. Furthermore, the bottom of the connection may be lower than the top of the light-emitting platform of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting platform, or located above the second electrode, or located between the two peaks of the second electrode.

[0112] In addition, such as Figures 7A to 7D As shown, in one embodiment of the present invention, the microlens has an air gap inside.

[0113] In an embodiment of the present invention, the microlens can be formed by multiple depositions. In the process of forming the microlens, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlens 508 is formed on the surface of the passivation layer at the position corresponding to each light-emitting platform.

[0114] Figure 8 A schematic flowchart illustrating the manufacturing method of the micro light-emitting diode chip as described above is shown. Figure 8 As shown, a method for manufacturing a miniature light-emitting diode chip includes:

[0115] First, in step 801, as Figure 9A As shown, a semiconductor light-emitting module is provided. A second epitaxial layer 533, an electron blocking layer 5322, a multilayer quantum well 5321, and a first epitaxial layer 531 are sequentially deposited on a substrate 001, and then the substrate is thinned. In one embodiment of the present invention, the substrate may be a Si substrate, a SiC substrate, or a sapphire substrate.

[0116] Next, in step 802, as Figure 9B As shown, the semiconductor light-emitting module is bonded to a driving backplane. The semiconductor light-emitting module is bonded to the driving backplane 501 to form a bonding layer. The driving backplane includes a driving circuit to provide driving signals to the micro-light-emitting diode chip and control the switching of pixels. A plurality of IC copper pillars 511 are disposed on the driving backplane. These IC copper pillars are electrically interconnected with the semiconductor light-emitting module to achieve pixel control. In one embodiment of the present invention, after chip bonding, the substrate of the semiconductor light-emitting module can be further thinned by grinding or laser lift-off to further thin the buffer layer structure, facilitating subsequent fabrication of the PN step structure. In embodiments of the present invention, the bonding process may include, for example, thermosetting bonding, which will not be elaborated further here.

[0117] Next, in step 803, as Figure 9C As shown, etched steps are formed. The semiconductor light-emitting module is subjected to step etching. By adjusting the photolithographic morphology, it is ion-etched to form positive trapezoidal structure pixels. In one embodiment of the present invention, the horizontal angle of the positive trapezoidal structure pixels can be, for example, 65° to 85°.

[0118] Next, in step 804, as Figure 9D As shown, deep trenches are etched. Further deep trench etching is performed at the intervals between each pixel, for example, using photolithography and IBE (Inert Gas Physical Etching) processes. It should be understood that this step may be omitted in some embodiments of the invention.

[0119] Next, in step 805, as Figure 9E As shown, a passivation layer is formed. Passivation layer 504 is formed on the sidewalls and surface of each pixel. In one embodiment of the invention, a first passivation layer is first formed by depositing SiO2 material using a CVD process, and then SiN is deposited on the surface of the first passivation layer using a CVD process. xA second passivation layer is formed using the material, and the first and second passivation layers together form passivation layer 504. In one embodiment of the present invention, a first passivation layer is first formed by depositing SiO2 material using a CVD process, and then a second passivation layer is formed by depositing Al2O3 material on the surface of the first passivation layer using an ALD process. The first and second passivation layers together form passivation layer 504. In another embodiment of the present invention, a first passivation layer is first formed by depositing Al2O3 material using an ALD process, and then a second passivation layer is formed by depositing SiO2 material on the surface of the first passivation layer using a CVD process. The first and second passivation layers together form passivation layer 504. It should be understood that in other embodiments of the present invention, more passivation layers may be formed, wherein the materials and processes of each layer may be the same or different. After deposition, photolithographic etching is performed above the corresponding pixel to expose at least a portion of the surface of the second epitaxial layer.

[0120] Next, in step 806, as Figure 9F As shown, a transparent conductive layer is formed. A top conductive layer 505 is formed on the surface of the passivation layer to achieve shared series connection of the second epitaxial layer for each pixel.

[0121] Next, in step 807, as Figure 9G As shown, a second electrode is formed. An annular reflective electrode 506 is formed at the deep trench. In one embodiment of the invention, the annular reflective electrode is implemented using magnetron sputtering or vapor deposition. In another embodiment of the invention, the second electrode uses Al or Al alloy metal as the sidewall reflective mirror, and the electrode stack metal uses metal materials such as Ni, Al, Ti, Pt, and Au.

[0122] Next, in step 808, as... Figure 9H As shown, a first electrode is formed. A first electrode 507 is formed on the drive backplane. The first electrode is connected to the IC copper pillar, which serves to protect and elevate the IC, and facilitates subsequent wire bonding.

[0123] Next, in step 809, as Figure 9IAs shown, a microlens is deposited. SiO2 is deposited, and the photolithographic morphology is adjusted to form a microlens 508. In one embodiment of the present invention, a SiO2 film layer, i.e., the first transmission layer, is deposited by PECVD. The thickness of the film layer is approximately 2.5 to 3.5 μm. Subsequently, by adjusting the photolithographic morphology of the microlens, such as the resist thickness, exposure energy, and hardening temperature, the photolithographic array morphology at the corresponding pixel position is completed. The SiO2 material of the microlens passivation protective layer is ion-etched to form a hemispherical SiO2 microlens with a lens-like morphology, which can improve the light extraction efficiency to a certain extent. Thus, the initial structure of the micro-LED chip is formed. However, due to the poor step coverage of the SiO2 deposited by PECVD, microcracks easily form in the deep trenches of the pixels, causing diffuse reflection of the quantum well light source and reducing the light extraction efficiency of the microlens. In addition, due to the photolithography size and ion etching of the microlens, the overall radius of curvature, lower spacer height, spherical height, and lens spherical width of the microlens are all relatively small, failing to achieve the optimal conditions for the lens. Therefore, in some embodiments of the present invention, a secondary deposition can be performed to increase the radius of curvature, lower spacer height, spherical height, and lens spherical width of the microlens. In one embodiment of the present invention, the film thickness of the secondary SiO2 deposition needs to be determined based on the film thickness of the SiO2 deposited in the previous microlens and the etching morphology of the microlens. In one embodiment of the present invention, the film thickness of the secondary deposition is preferably 0.2 to 1 μm, and it can be performed in a single or multiple deposition operations. In one embodiment of the present invention, the secondary SiO2 deposition uses a mixed gas of SiH4 and N2O, with the ratio of SiH4 to N2O being 1:5. At the same time, the gas flow rate is controlled at a low level so that the deposition rate is much lower than that of the previous microlens deposition. The secondary deposition adopts a high vacuum environment process condition and a large flow rate of inert gas N2 to further improve the step coverage effect of the secondary SiO2 deposition, making it less prone to defects and even able to repair micro-defects in the previous microlens deposition, resulting in a better brightness improvement effect.

[0124] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A miniature light-emitting diode with multiple passivation layers, characterized in that, include: A light-emitting platform, configured to emit light; as well as A passivation layer covering at least a portion of the side surfaces of the light-emitting mesa, and the passivation layer comprising: A first passivation layer having a first material having a first refractive index; as well as The second passivation layer has a second material having a second refractive index, which is different from the first refractive index.

2. The miniature light-emitting diode as described in claim 1, characterized in that, The first and second materials are selected from the group consisting of the following: SiO2, SiO2, Al2O3, AlN, HfO2 and SiN x .

3. The miniature light-emitting diode as described in claim 1, characterized in that, The first passivation layer is closer to the light-emitting platform than the second passivation layer, and the second refractive index is higher than the first refractive index.

4. The miniature light-emitting diode as described in claim 1, characterized in that, The first passivation layer and the second passivation layer are formed using the same process.

5. The miniature light-emitting diode as described in claim 1, characterized in that, The first passivation layer and the second passivation layer were fabricated using chemical vapor deposition (CVD).

6. The miniature light-emitting diode as described in claim 1, characterized in that, The first passivation layer is formed by a first process, the second passivation layer is formed by a second process, and the first process is different from the second process.

7. The miniature light-emitting diode as described in claim 6, characterized in that, The first and second processes are selected from the group consisting of the following: Chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes.

8. The miniature light-emitting diode as described in claim 1, characterized in that, The thickness of the passivation layer is 20 to 1000 nanometers, wherein the thicknesses of the first passivation layer and the second passivation layer are 20 to 500 nanometers, respectively.

9. The miniature light-emitting diode as described in claim 1, characterized in that, The light-emitting platform comprises, in sequence, a first epitaxial layer, a light-emitting layer, and a second epitaxial layer.

10. The miniature light-emitting diode as described in claim 9, characterized in that, The second epitaxial layer is a material layer of the second conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P, and the first conductivity type is different from the second conductivity type.

11. The miniature light-emitting diode as described in claim 9, characterized in that, The light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / Al GaN multi-quantum well layer, or an InGaAs / Al GaAs multi-quantum well layer.

12. The miniature light-emitting diode as described in claim 9, characterized in that, An electron blocking layer is provided on the first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer.

13. A miniature light-emitting diode chip, characterized in that, include: Drive backplane; as well as A micro light-emitting diode array bonded to the driving backplane, wherein the micro light-emitting diode array comprises a plurality of micro light-emitting diodes as described in any one of claims 1 to 12.

14. The micro light-emitting diode chip as described in claim 13, characterized in that, The micro LED array includes a continuous top conductive layer disposed above the micro LED array and contacting and covering the top of each light-emitting platform.

15. The micro light-emitting diode chip as described in claim 13, characterized in that, The surface of the drive backplate is provided with a metal layer.

16. The micro light-emitting diode chip as described in claim 15, characterized in that, The drive backplane is provided with a plurality of IC copper pillars, which are electrically connected to the metal layer.

17. The micro light-emitting diode chip as described in claim 16, characterized in that, Each light-emitting mesa in the micro LED array region corresponds to an IC copper pillar.

18. The micro light-emitting diode chip as described in claim 15, characterized in that, The material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.

19. The micro light-emitting diode chip as described in claim 13, characterized in that, A second electrode is provided between adjacent light-emitting platforms.

20. The micro light-emitting diode chip as described in claim 19, characterized in that, The second electrode is a ring-shaped reflective electrode, which is arranged around the light-emitting platform.

21. The micro light-emitting diode chip as described in claim 19, characterized in that, A deep trench is provided between adjacent light-emitting platforms, the deep trench extends through the micro light-emitting diode array, and the second electrode is disposed at the deep trench.

22. The micro light-emitting diode chip as described in claim 21, characterized in that, The second electrode between adjacent light-emitting mesa has at least two peaks.

23. The micro light-emitting diode chip as described in claim 19, characterized in that, The second electrodes are interconnected.

24. The micro light-emitting diode chip as described in claim 16, characterized in that, Also includes: At least one first electrode is electrically connected to the copper pillar of the IC.

25. The micro light-emitting diode chip as described in claim 24, characterized in that, The polarity of the first electrode is opposite to that of the second electrode.

26. The micro light-emitting diode chip as described in claim 13, characterized in that, It also includes a microlens array, which is located above the micro-light-emitting diode array and includes multiple microlenses, wherein at least one microlens is disposed on the surface of the conductive layer on top of the micro-light-emitting diode.

27. The micro light-emitting diode chip as described in claim 13, characterized in that, It also includes a microlens array, which is located above the micro-light-emitting diode array and includes multiple microlenses, each of which corresponds to a light-emitting platform.

28. The micro light-emitting diode chip as described in claim 27, characterized in that, The microlens has an air gap inside.

29. The micro light-emitting diode chip as described in claim 27, characterized in that, Adjacent micro-projection lenses are interconnected, but there is a gap at the connection point.

30. The micro light-emitting diode chip as described in claim 27, characterized in that, The bottoms of adjacent micro-projection lenses are connected to each other.

31. A method for manufacturing a miniature light-emitting diode chip, characterized in that, Including the following steps: Forming a semiconductor light-emitting module; The semiconductor light-emitting module is bonded to the driver backplane; Step etching is performed on the semiconductor light-emitting module; Multiple passivation layers are sequentially formed on the sidewalls and surface of each pixel, with different layers having different refractive indices. A photolithographic etching is performed on the passivation layer above the corresponding pixel to expose at least a portion of the surface at the top of the pixel; A top conductive layer is formed on the surface of the passivation layer; A second electrode is formed at the interval of each pixel; A first electrode is formed on the drive backplate; as well as Deposited microlenses.

32. The manufacturing method as described in claim 31, characterized in that, The steps involved in forming a semiconductor light-emitting module are as follows: A second epitaxial layer, an electron blocking layer, a multilayer quantum well, and a first epitaxial layer are sequentially deposited on the substrate.

33. The manufacturing method as described in claim 31, characterized in that, The step etching process for the semiconductor light-emitting module includes the following steps: The semiconductor light-emitting module is etched to form positive trapezoidal pixel structures.

34. The manufacturing method as described in claim 33, characterized in that, The horizontal angle of the pixels in the trapezoidal structure is 65° to 85°.

35. The manufacturing method as described in claim 31, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer, wherein the refractive index of the material of the first passivation layer is lower than that of the second passivation layer.

36. The manufacturing method as described in claim 35, characterized in that, The first passivation layer is made of SiO2, and the second passivation layer is made of SiN. x .

37. The manufacturing method as described in claim 31, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer, and the formation processes of the first passivation layer and the second passivation layer are different.

38. The manufacturing method as described in claim 35, characterized in that, The first passivation layer is made of SiO2, and the second passivation layer is made of Al2O3.

39. The manufacturing method as described in claim 38, characterized in that, The first passivation layer is fabricated using chemical vapor deposition (CVD), and the second passivation layer is fabricated using atomic layer deposition (ALD).

40. The manufacturing method as described in claim 37, characterized in that, The first passivation layer is made of Al2O3, and the second passivation layer is made of SiO2.

41. The manufacturing method as described in claim 40, characterized in that, The first passivation layer is fabricated using atomic layer deposition (ALD) and the second passivation layer is fabricated using chemical vapor deposition (CVD).

42. The manufacturing method as described in claim 31, characterized in that, It also includes the following steps: Deep trench etching is performed at the intervals between each pixel, and the second electrode is disposed at the deep trench.

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