Collaborative optimization of ITO / InON:SnO x Methods for assessing the performance of ZnON thin-film transistors

Abstract

This invention discloses a method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors, comprising the following steps: treating the substrate surface with oxygen plasma; depositing an amorphous ITO thin film layer and an InON:SnO2:ZnON thin film layer on the treated substrate; subjecting the treated substrate to heat treatment at a temperature of 100°C; at room temperature, depositing an amorphous ITO target and an amorphous ZnON target on the treated InON:SnO2:ZnON thin film layer using RF co-sputtering to obtain an ITO:ZnON transition electrode; and depositing a copper target on the ITO:ZnON transition electrode using DC sputtering to obtain the source electrode and drain electrode. This invention solves the problem of existing thin-film transistors where high electrical performance and high bias voltage stability are difficult to achieve simultaneously.

Description

Technical Field

[0001] This invention belongs to the technical field of thin-film transistor fabrication methods, specifically involving the synergistic optimization of ITO / InON:SnO. x Methods for improving the performance of ZnON thin-film transistors. Background Technology

[0002] Driven by the development needs of next-generation electronic products (such as mini-LED or micro-LED, neuromorphic computing, and gas-sensitive / biosensors), amorphous indium tin oxide (ITO) has become a new research hotspot in the field of thin-film transistors (TFTs) due to its unique electrical and optical properties. However, it still faces the following key challenges:

[0003] Amorphous ITO, with its high carrier mobility and good conductivity, is a core material for high-performance thin-film transistors. However, it has poor bias stability and a large threshold voltage. In addition, existing methods to improve its bias stability often rely on fabrication / improvement methods that are not compatible with existing low-temperature processes, such as high-temperature (greater than 350°C) thin-film deposition and annealing or complex device structures (spacer layers, buffer layers, capping layers, and high-k dielectric layers, etc.) and their excessive thickness (channel layer thickness greater than 30 nm, electrode thickness greater than 60 nm, etc.), which may even require secondary annealing of the entire device.

[0004] Therefore, there is an urgent need for a fabrication method that matches existing semiconductor processes (without requiring complex device structures), is cost-effective, and can simultaneously solve the problem of high electrical performance and high bias stability of thin-film transistors at low temperatures (far below 350°C) (channel layer thickness less than 30nm, electrode thickness less than 60nm). Summary of the Invention

[0005] The purpose of this invention is to provide a collaboratively optimized ITO / InON:SnO x The method for improving the performance of ZnON (x=2) thin-film transistors solves the problem of high electrical performance and high bias voltage stability in existing thin-film transistors from the fabrication stage.

[0006] The technical solution adopted in this invention is to collaboratively optimize ITO / InON:SnO. x The method for assessing the performance of ZnON thin-film transistors, with the following specific steps: Step 1: Perform oxygen plasma treatment on the substrate surface; Step 2: Deposit an amorphous ITO thin film layer and an InON:SnO2:ZnON thin film layer on the treated substrate; Step 3: Perform heat treatment on the substrate after step 2; Step 4: At room temperature, amorphous ITO target and amorphous ZnON target are deposited on the InON:SnO2:ZnON thin film layer after step 3 by radio frequency co-sputtering to obtain ITO:ZnON transition electrode. Step 5: Deposit copper target material on ITO:ZnON transition electrode by DC sputtering to obtain source electrode and drain electrode.

[0007] The invention is further characterized by: The specific process of step 1 is as follows: the surface of the Si substrate with 100nm thermally grown SiO2 is placed into the plasma processing system for oxygen plasma treatment.

[0008] The specific process of step 2 is as follows: Step 2.1: At room temperature, an active layer mask is applied to the substrate and then transferred to the chamber of the RF magnetron sputtering coating instrument. An amorphous ITO target is added to the chamber, a vacuum is drawn, the RF sputtering power is set, argon gas is introduced, and the pressure regulating valve is moved to make the resistance unit of the magnetron sputtering coating instrument reach its maximum value. The ITO target baffle is opened, and after the amorphous ITO target is ignited, the ITO target baffle is closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle and the ITO target baffle are opened simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering to obtain an amorphous ITO thin film layer. Step 2.2: Remove the amorphous ITO target and add three amorphous InON, amorphous SnO2, and amorphous ZnON targets respectively into the chamber of the RF magnetron sputtering coating instrument. Evacuate the chamber, set the RF sputtering power, introduce argon gas, and move the pressure regulating valve to maximize the resistance of the magnetron sputtering coating instrument. Open the baffles for the amorphous InON, SnO2, and ZnON targets. Wait for the amorphous InON target... After the amorphous SnO2 and amorphous ZnON targets are fully ignited, the amorphous InON target baffle, the amorphous SnO2 target baffle, and the amorphous ZnON target baffle are turned off for pre-sputtering. After the pre-sputtering is completed, the amorphous InON target baffle, the amorphous SnO2 target baffle, the amorphous ZnON target baffle, and the sample baffle are turned on simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for co-sputtering to obtain an InON:SnO2:ZnON thin film layer.

[0009] In step 2.1, the gas pressure in the chamber after evacuation is 0.85 Pa, the radio frequency sputtering power is 45 W to 50 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time is 15 min to 20 min, and the formal sputtering time is 1 min to 2 min.

[0010] In step 2.2, after evacuation, the gas pressure in the chamber is maintained at 0.85 Pa. The RF sputtering power is 45 W to 50 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time for the three targets is 15 min to 20 min, the co-sputtering time is 1 min to 5 min, and the gas pressure in the chamber is maintained at 0.85 Pa during the co-sputtering process.

[0011] In step 3, the heat treatment is carried out in an air atmosphere at a temperature of 100°C for a duration of 0.5 to 0.8 hours.

[0012] The specific process of step 4 is as follows: At room temperature, an electrode mask is placed on the InON:SnO2:ZnON thin film layer treated in step 3, and then transferred to the chamber of the magnetron sputtering coating instrument. Three copper targets, amorphous ITO targets, and amorphous ZnON targets are added to the chamber at the same time. Vacuum is drawn, the RF sputtering power is set, argon gas is introduced, and the pressure regulating valve is moved to make the resistance unit of the magnetron sputtering coating instrument reach its maximum value. The amorphous ZnON target baffle and the amorphous ITO target baffle are opened, while the copper target baffle is kept closed. After the amorphous ZnON target and the amorphous ITO target are ignited, the amorphous ZnON target baffle and the amorphous ITO target baffle are closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle, the amorphous ZnON target baffle, and the amorphous ITO target baffle are opened at the same time, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering to obtain the ITO:ZnON transition electrode.

[0013] In step 4, after evacuation, the gas pressure in the chamber is maintained at 1.4 Pa, the RF sputtering power is 15 W to 20 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time is 15 min to 20 min, the gas pressure in the chamber is maintained at 1.4 Pa during the formal sputtering process, and the formal sputtering time is 1 min to 6 min.

[0014] The specific process of step 5 is as follows: At room temperature, after the ITO:ZnON transition electrode is sputtered, the amorphous ZnON target and the amorphous ITO target baffle are closed, and the gas pressure, argon flow rate and sputtering power in the chamber are kept constant. The copper target baffle is opened, and after the copper target is ignited, the copper target baffle is closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle and the copper target baffle are opened at the same time, and the substrate rotation of the magnetron sputtering coating instrument is started for formal DC sputtering to obtain the copper source electrode and drain electrode.

[0015] In step 5, the pre-sputtering time is 15-20 minutes, the formal sputtering time is 18 minutes, the formal sputtering power is 18W, and the gas pressure inside the chamber is maintained at 1.4Pa during the formal sputtering process.

[0016] The beneficial effects of this invention are as follows: The method of this invention, through pre-plasma treatment, the synergistic effect of ITO and InON:SnO2:ZnON dual-channel technology, and the ITO:ZnON / Cu electrode system, produces ITO / InON:SnO2:ZnON thin-film transistors with simultaneously high electrical performance and high bias voltage stability: the device mobility can reach 110.03 cm⁻¹. 2 / V The threshold voltage is -1.06V, and the on / off ratio is as high as 3.15×10⁻⁶. 8 After applying a positive gate bias voltage of 20V and a reverse gate bias voltage of -20V for 60 minutes, the threshold voltage drift was only 1.07V and -0.26V, respectively; after applying a negative gate bias voltage of -20V under illumination for 60 minutes, the threshold voltage drift was only -0.98V. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the ITO / InON:SnO2:ZnON thin film transistor (electrode: ITO:ZnON / Cu) obtained by the method of the present invention; Figure 2 The graphs show the transfer characteristic curves of the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistors prepared in Examples 1 to 3 of this invention. Figure 3 The output characteristic curve of the ITO / InON:SnO2:ZnON (electrode:ITO:ZnON / Cu) thin film transistor prepared in Example 2 of the present invention is shown. Figure 4 The graph shows the transfer characteristics of the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistor prepared in Example 2 of this invention after applying positive bias stress. Figure 5 The graph shows the transfer characteristics of the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistor prepared in Example 2 of this invention after applying negative bias stress. Figure 6 The graph shows the transfer characteristics of the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistor prepared in Example 2 of this invention after applying positive bias stress under light illumination. Figure 7 The transfer characteristic curve of the ITO / InON:SnO2:ZnON (electrode:ITO:ZnON / Cu) thin film transistor prepared in Example 2 of the present invention after applying negative bias stress under light illumination. Figure 8The image shows the X-ray diffraction analysis (XRD) pattern of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention. Figure 9 Scanning Electron Microscope (SEM) image and EDS schematic diagram of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention; Figure 10 This is an atomic force microscope (AFM) image of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of the present invention; Figure 11 The voltage-capacitance curve of the ITO / InON:SnO2:ZnON (electrode:ITO:ZnON / Cu) thin film transistor prepared in Example 2 of the present invention; Figure 12 The electron concentration distribution diagram is shown for the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistor prepared in Example 2 of the present invention. Figure 13 The image shows the full X-ray photoelectron spectroscopy (XPS) spectrum of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention, as etched with depth. Figure 14 The O 1s peak diagram of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention; Figure 15 The image shows the low frequency noise (LFN) characteristic test results of the ITO / InON:SnO2:ZnON (electrode: ITO:ZnON / Cu) thin film transistor prepared in Example 2 of this invention. Figure 16 The image shows the ultraviolet-visible spectroscopy (UV-Vis) spectrum of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention. Figure 17 The X-ray photoelectron spectroscopy (XPS) valence band spectrum of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention; Figure 18The image shows the ultraviolet photoelectron spectroscopy (UPS) of the ITO / InON:SnO2:ZnON thin film prepared in Example 2 of this invention. Figure 19 The band diagrams are shown for the amorphous ITO film prepared in Comparative Example 1 and the ITO / InON:SnO2:ZnON film prepared in Example 2 of this invention. Figure 20 The transfer characteristic curve of the amorphous ITO thin film transistor prepared in Comparative Example 1 of this invention is shown. Figure 21 This is a graph showing the output characteristics of the amorphous ITO thin-film transistor prepared in Comparative Example 1 of this invention. Figure 22 This is a graph showing the transfer characteristics of the amorphous ITO thin film transistor prepared in Comparative Example 1 of this invention after applying positive bias stress. Figure 23 This is a transfer characteristic curve of the amorphous ITO thin film transistor prepared in Comparative Example 1 of the present invention after applying negative bias stress; Figure 24 The XRD pattern of the amorphous ITO thin film prepared in Comparative Example 1 of this invention is shown. Figure 25 The image shows the AFM pattern of the amorphous ITO thin film prepared in Comparative Example 1 of this invention. Figure 26 XPS full spectrum of the amorphous ITO thin film prepared in Comparative Example 1 of this invention as a function of etching depth; Figure 27 The image shows the O 1s peak of the amorphous ITO thin film prepared in Comparative Example 1 of this invention. Figure 28 The image shows the LFN characteristic test pattern of the amorphous ITO thin film transistor prepared in Comparative Example 1 of this invention. Figure 29 The UV-Vis image is shown for the amorphous ITO thin film prepared in Comparative Example 1 of this invention. Figure 30 XPS valence band spectrum of the amorphous ITO thin film prepared in Comparative Example 1 of this invention; Figure 31 This is a UPS image of the amorphous ITO thin film prepared in Comparative Example 1 of this invention; Figure 32 The graph shows the transfer characteristics of the InON:SnO2 thin film transistor prepared in Comparative Example 2 of this invention. Figure 33 The output characteristic curve of the InON:SnO2 thin film transistor prepared in Comparative Example 2 of this invention is shown. Figure 34This is a graph showing the transfer characteristics of the InON:SnO2 thin film transistor prepared in Comparative Example 2 of this invention after applying positive bias stress. Figure 35 This is a graph showing the transfer characteristics of the InON:SnO2 thin film transistor prepared in Comparative Example 2 of this invention after applying negative bias stress. Figure 36 The transfer characteristic curve of the ITO / InON:SnO2:ZnON thin film transistor obtained in Comparative Example 3 of this invention; Figure 37 The output characteristic curve of the ITO / InON:SnO2:ZnON thin film transistor obtained in step 3 of Comparative Example 3 of this invention under the condition that the ZnON sputtering time is 3 min. Figure 38 This is a graph showing the transfer characteristics of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of the present invention after applying positive bias stress. Figure 39 This is a graph showing the transfer characteristics of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of the present invention after applying negative bias stress. Figure 40 This is a voltage-capacitance curve of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of the present invention. Figure 41 The electron concentration distribution diagram of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of the present invention is shown. Figure 42 This is the XPS full spectrum of the ITO / InON:SnO2:ZnON thin film obtained by etching depth in step 3 of Comparative Example 3 of the present invention under the condition that the ZnON sputtering time is 3 min. Figure 43 This is the O 1s peak diagram of the ITO / InON:SnO2:ZnON thin film obtained in step 3 of Comparative Example 3 of the present invention under the condition that the ZnON sputtering time is 3 min; Figure 44 This is a test image of the LFN characteristics of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of the present invention; Detailed Implementation The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0018] The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to the present invention is characterized by the following specific steps: Step 1: Perform pre-oxygen plasma treatment on the substrate surface; The specific process is as follows: The surface of the Si substrate with 100nm thermally grown SiO2 was placed in a plasma treatment system (model JSD200) for oxygen plasma treatment. The treatment power was 5W~10W and the treatment time was 5s~15s. Step 2: Deposit an amorphous ITO thin film layer and an InON:SnO2:ZnON thin film layer on the treated substrate; The specific process is as follows: Step 2.1: At room temperature, an active layer mask (containing several squares arranged in an array, each with a side length of 580 μm and a spacing of 280 μm between adjacent squares) is placed on the substrate. The substrate is then transferred to the chamber of an RF magnetron sputtering coating instrument (model JSD400-III). An amorphous ITO target is added to the chamber, and a vacuum is evacuated to a chamber pressure of 0.85 Pa. The RF sputtering power is set to 45 W~50 W, and argon gas is introduced at a flow rate of 20 ng / L. SCCM~25SCCM, move the pressure regulating valve to bring the resistance unit of the magnetron sputtering coating instrument to its maximum value, open the ITO target baffle, and after the amorphous ITO target ignites, close the ITO target baffle for pre-sputtering for 15min~20min. After the pre-sputtering is completed, simultaneously open the sample baffle and the ITO target baffle, start the substrate rotation of the magnetron sputtering coating instrument for formal sputtering for 1min~2min. During the formal sputtering, the gas pressure in the chamber is 0.85Pa, and an amorphous ITO thin film layer (channel I) is obtained. During the entire sputtering process, no external temperature is applied to the substrate; Step 2.2: Close the ITO target baffle, remove the amorphous ITO target, and simultaneously add three amorphous InON, amorphous SnO2, and amorphous ZnON targets to the chamber of the RF magnetron sputtering coating instrument. Evacuate the chamber to maintain a pressure of 0.85 Pa. Set the RF sputtering power to 45W~50W, introduce argon gas at a flow rate of 20SCCM~25SCCM, move the pressure regulating valve to maximize the resistance of the magnetron sputtering coating instrument, and open the amorphous InON, amorphous SnO2, and amorphous ZnON target baffles. Wait for the amorphous InON target to... After the N-target, amorphous SnO2 target, and amorphous ZnON target are all ignited, the amorphous InON target baffle, amorphous SnO2 target baffle, and amorphous ZnON target baffle are turned off for pre-sputtering for 15-20 minutes. After pre-sputtering, the amorphous InON target baffle, amorphous SnO2 target baffle, amorphous ZnON target baffle, and sample baffle are simultaneously opened, and the substrate rotation of the magnetron sputtering coating instrument is started for co-sputtering for 1-5 minutes. During co-sputtering, the gas pressure in the chamber is maintained at 0.85 Pa, resulting in an InON:SnO2:ZnON thin film layer (channel II). During the entire sputtering process, no external temperature is applied to the substrate; Step 3: The substrate treated in step 2 is subjected to heat treatment in an air atmosphere at a temperature of 100°C for a time of 0.5h to 0.8h, and then allowed to cool naturally to room temperature. The heat treatment is carried out in a tube furnace, model Thermo Scientific LBM. Step 4: At room temperature, amorphous ITO target and amorphous ZnON target are deposited on the InON:SnO2:ZnON thin film layer after step 3 by radio frequency co-sputtering to obtain ITO:ZnON transition electrode. The specific process is as follows: At room temperature, an electrode mask (with several squares arranged in an array on the electrode mask, each square having a side length of 160 μm and a spacing of 110 μm between adjacent squares) is placed on the InON:SnO2:ZnON thin film layer treated in step 3. The film is then transferred to the chamber of a magnetron sputtering coating instrument, and three copper targets, an amorphous ITO target, and an amorphous ZnON target are simultaneously added to the chamber. A vacuum is drawn to maintain the gas pressure in the chamber at 1.4 Pa. The RF sputtering power is set to 15 W~20 W, and argon gas is introduced at a flow rate of 20 SCCM~25 SCCM. The pressure regulating valve is moved to... When the resistance unit of the magnetron sputtering coating instrument reaches its maximum value, open the amorphous ZnON target baffle and the amorphous ITO target baffle, while keeping the copper target baffle closed. After the amorphous ZnON target and the amorphous ITO target are ignited, close the amorphous ZnON target baffle and the amorphous ITO target baffle and perform pre-sputtering for 15 min to 20 min. After the pre-sputtering is completed, simultaneously open the sample baffle, the amorphous ZnON target baffle and the amorphous ITO target baffle, and start the substrate rotation of the magnetron sputtering coating instrument for formal sputtering for 1 min to 6 min. During the formal sputtering process, the gas pressure in the chamber is maintained at 1.4 Pa to obtain the ITO:ZnON transition electrode. Step 5: At room temperature, deposit copper target material on ITO:ZnON transition electrode by DC sputtering to obtain source electrode and drain electrode; The specific process is as follows: At room temperature, after the ITO:ZnON transition electrode sputtering is completed, the amorphous ZnON target and amorphous ITO target baffles are closed, while maintaining the chamber pressure, argon flow rate, and sputtering power constant. The copper target baffle is opened, and after the copper target ignites, it is closed again for pre-sputtering for 15-20 minutes. After pre-sputtering, both the sample baffle and the copper target baffle are opened simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering for 18 minutes at a sputtering power of 18W. During formal sputtering, the chamber pressure is maintained at 1.4 Pa, resulting in copper source and drain electrodes, thus obtaining the desired coating. Figure 1 The ITO / InON:SnO2:ZnON thin-film transistor shown.

[0019] Example 1 Step 1: Transfer the Si substrate with 100nm thermally grown SiO2 into the plasma treatment system, perform oxygen plasma treatment on the substrate surface, set the treatment power to 8W, treat for 5s, and remove after treatment.

[0020] Step 2: Deposit an amorphous ITO thin film layer and an InON:SnO2:ZnON thin film layer on the treated substrate; The specific process is as follows: Step 2.1: At room temperature, an active layer mask (with several squares arranged in an array on the active layer mask, each square having a side length of 580 μm and a spacing of 280 μm between adjacent squares) is placed on the substrate. The substrate is then transferred to the chamber of an RF magnetron sputtering coating instrument (model JSD400-III). An amorphous ITO target is added to the chamber, and a vacuum is evacuated to a chamber pressure of 0.85 Pa. The RF sputtering power is set to 45 W, and argon gas is introduced at a flow rate of 22 SC. CM, move the pressure regulating valve to make the resistance unit of the magnetron sputtering coating instrument reach the maximum value, open the ITO target baffle, and after the amorphous ITO target is ignited, close the ITO target baffle for pre-sputtering for 18 minutes. After the pre-sputtering is completed, open the sample baffle and the ITO target baffle at the same time, start the substrate rotation of the magnetron sputtering coating instrument for formal sputtering for 1.5 minutes. During the formal sputtering, the gas pressure in the chamber is 0.85 Pa, and an amorphous ITO thin film layer (channel I) is obtained with a thickness of 5 nm. Step 2.2: Close the ITO target baffle, remove the amorphous ITO target, and simultaneously add three amorphous InON, amorphous SnO2, and amorphous ZnON targets to the chamber of the RF magnetron sputtering coating instrument. Evacuate the chamber to maintain a pressure of 0.85 Pa. Set the RF sputtering power to 45 W, introduce argon gas at a flow rate of 22 SCCM, and move the pressure regulating valve to maximize the resistance of the magnetron sputtering coating instrument. Open the baffles for the amorphous InON, SnO2, and ZnON targets. After all the amorphous InON, SnO2, and ZnON targets are fully ignited, close the baffle for the amorphous InON target. Pre-sputtering was performed for 18 minutes using the target baffle, amorphous SnO2 target baffle, and amorphous ZnON target baffle. After pre-sputtering, the amorphous InON target baffle, amorphous SnO2 target baffle, amorphous ZnON target baffle, and sample baffle were simultaneously opened. The substrate rotation of the magnetron sputtering coating instrument was started for co-sputtering. The sputtering time for amorphous InON and amorphous SnO2 targets was 3 minutes, and the sputtering time for amorphous ZnON targets was 3 minutes. The gas pressure in the chamber was maintained at 0.85 Pa during co-sputtering. An InON:SnO2:ZnON thin film layer (channel II) was obtained with a thickness of 15 nm. Step 3: Place the substrate treated in step 2 into a tube furnace and heat treat it in an air atmosphere. The heat treatment temperature is 100℃ and the heat treatment time is 0.8h. After heat treatment, allow it to cool naturally to room temperature. Step 4: At room temperature, cover the InON:SnO2:ZnON thin film layer treated in Step 3 with an electrode mask (the electrode mask has several squares arranged in an array, each square with a side length of 160μm and a spacing of 110μm between adjacent squares). Then transfer it to the chamber of the magnetron sputtering coating instrument, and simultaneously add three copper targets, an amorphous ITO target, and an amorphous ZnON target into the chamber. Evacuate the chamber to maintain a pressure of 1.4Pa, set the RF sputtering power to 18W, introduce argon gas at a flow rate of 22SCCM, and move the pressure regulating valve to adjust the resistance unit of the magnetron sputtering coating instrument. When the maximum value is reached, open the amorphous ZnON target baffle and the amorphous ITO target baffle, while keeping the copper target baffle closed. After the amorphous ZnON target and the amorphous ITO target are ignited, close the amorphous ZnON target baffle and the amorphous ITO target baffle for 18 minutes of pre-sputtering. After the pre-sputtering is completed, simultaneously open the sample baffle, the amorphous ZnON target baffle, and the amorphous ITO target baffle, and start the substrate rotation of the magnetron sputtering coating instrument for formal sputtering for 1.5 minutes. During the formal sputtering, the gas pressure in the chamber is maintained at 1.4 Pa to obtain an ITO:ZnON transition electrode with a thickness of 2 nm.

[0021] Step 5: At room temperature, after the ITO:ZnON transition electrode is sputtered, close the baffles for the amorphous ZnON target and the amorphous ITO target, and keep the chamber pressure, argon flow rate, and sputtering power constant. Open the copper target baffle, and after the copper target ignites, close the copper target baffle for pre-sputtering for 18 minutes. After the pre-sputtering is completed, open the sample baffle and the copper target baffle simultaneously, and start the substrate rotation of the magnetron sputtering coating instrument for formal sputtering for 18 minutes with a sputtering power of 18W. During the formal sputtering, the chamber pressure is maintained at 1.4Pa to obtain copper source and drain electrodes. The thickness of both source and drain electrodes is 45nm, thus obtaining the ITO / InON:SnO2:ZnON thin film transistor.

[0022] Example 2 The difference from Example 1 is that in step 4, the thickness of the obtained ITO:ZnON transition electrode is 4nm.

[0023] like Figure 3 As shown, the output characteristics after applying a gate voltage (-20~50V) are as follows: when V gs At 50V, the maximum saturation current reached 0.44mA; Figure 4 As shown, the bias stability of the ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm is reflected. When a forward bias voltage (20V) is applied for 60 minutes, the threshold voltage drift is 1.07V. Figure 5As shown, the bias stability of the ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm is reflected. After applying a negative bias voltage (-20V) for 60 min, the threshold voltage drift is -0.26V, a significant improvement compared to Comparative Examples 1 and 3. This is mainly due to the InON:SnO2:ZnON layer effectively reducing the interface state density, thereby suppressing the trapping and release of charge carriers under bias stress in the interface traps, and reducing the impact of PBS and NBS conditions. V TH After sputtering an ITO:ZnON transition electrode onto the ITO / InON:SnO2:ZnON thin-film transistor structure, the bias stability of the device achieves a further leap, significantly outperforming the bias stability of devices without sputtered ITO:ZnON transition electrodes; for example... Figure 6 As shown, the bias stability of an ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm is reflected. When a forward bias voltage (20V) is applied for 60 minutes under illumination, the threshold voltage drift is 1.21V. Figure 7 As shown, the bias stability of an ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm is reflected. When a negative bias voltage (-20V) is applied for 60 min under illumination, the threshold voltage drift is -0.94V. Figure 8 As shown, the ITO / InON:SnO2:ZnON film exhibits a high-intensity characteristic peak originating from the Si substrate with a 2θ angle of 69.36°, indicating that the prepared ITO / InON:SnO2:ZnON film retains its amorphous state even after heat treatment at 100℃ for 0.5~0.8h. Figure 9 It can be seen that the active layer is composed of a 5 nm ITO thin film and a 15 nm InON:SnO2:ZnON thin film layer stacked together, and has a clear SiO2 / ITO and ITO / InON:SnO2:ZnON interface; the In, Sn, Zn, N and O elements are uniformly distributed throughout the active layer, with no obvious interdiffusion or phase separation; Figure 10 As shown, the roughness of the ITO / InON:SnO2:ZnON film decreased to 0.56 nm, which is significantly lower than that of Comparative Example 1, which had a roughness of 0.87 nm. This indicates an improvement in the surface film quality and a reduction in surface defect density. Figure 11 The figure shows the voltage-capacitance curve of an ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm. Based on the voltage-capacitance data, the following formula is used: and formula Plotting the calculated depth against the electron concentration values Figure 12 Electron concentration distribution map; in Figure 12 The ITO / InON:SnO2:ZnON interface shows obvious N CV The peak value indicates that a two-dimensional electron gas was formed at the interface of the ITO / InON:SnO2:ZnON heterojunction, resulting in electron enrichment at the interface. The electron concentration on the ITO side of the interface is as high as 10. 19 cm -3 ;like Figure 13 The image shows the XPS full spectrum of the ITO / InON:SnO2:ZnON film. The results show the peak positions that should be present in the ITO / InON:SnO2:ZnON film, and there are no other obvious characteristic peaks, proving that no other impurities were introduced during the preparation of the ITO / InON:SnO2:ZnON film and the sample was not contaminated. Figure 14 The figure shows the O 1s peak diagram of the ITO / InON:SnO2:ZnON thin film. The results indicate that oxygen migrates from the channel layer to the ITO:ZnON transition electrode at the interface. The oxygen vacancy content of the ITO / InON:SnO2:ZnON thin film is 35.41%, compared to Comparative Example 3 with an oxygen vacancy content of 30.93%. A suitable increase in oxygen vacancy content improves carrier concentration and thus contributes to improved mobility. Simultaneously, the ITO:ZnON transition electrode blocks Cu diffusion, reducing the generation of additional trap states such as MO, indirectly stabilizing the function of oxygen vacancies in the channel. Figure 15 As shown, the normalized noise power spectral density versus frequency curves of an ITO / InON:SnO2:ZnON thin-film transistor with an ITO:ZnON transition electrode thickness of 4 nm under different gate overdrive voltages are all consistent with the classical flicker noise (1 / f The noise level showed a good fit with no significant deviation, indicating that the noise behavior of the ITO / InON:SnO2:ZnON thin-film transistor is mainly 1 / f Noise is dominant. Compared to Comparative Example 3, Example 2 shows a reduced interface defect density between the gate dielectric layer and the active layer, improved interface quality, reduced carrier trapping by interface defects, and better device electrical performance; such as Figure 16 As shown, the E of the ITO / InON:SnO2:ZnON thin film g It is 3.76 eV, compared to E gIn Comparative Example 1 (3.67 eV), after the ITO and InON:SnO2:ZnON films come into contact, the energy band of the ITO film bends downwards, while the energy band of the InON:SnO2:ZnON film bends upwards, forming a potential barrier at the interface between ITO and InON:SnO2:ZnON. When a forward bias is applied to the gate, this barrier traps electrons and induces a large accumulation of electrons within it, thus increasing mobility. Figure 17 and Figure 18 As shown, the band gap (E) of the ITO / InON:SnO2:ZnON thin film was determined using ultraviolet-visible spectroscopy and X-ray photoelectron spectroscopy (VPS). g The energy level difference (EVBM) between the valence band top and the Fermi level was determined using ultraviolet photoelectron spectroscopy, and the secondary electron cutoff energy (E0) of each thin film was also measured. cutoff ), and through the formula φ=21.22 E cutoff The work function (φ) of the thin film is calculated, and the E of the thin film is obtained. VBM It is 2.35 eV, E cutoff It is 17.21 eV.

[0024] Example 3 The difference from Example 1 is that in step 4, the thickness of the obtained ITO:ZnON transition electrode is 6nm.

[0025] Example 4 The difference from Example 1 is that in step 1, the processing power is 5W and the processing time is 15s; In step 2.1, the RF sputtering power is set to 50W, the argon flow rate is 25SCCM, the pre-sputtering time is 15min, and the formal sputtering time is 1.5min. In step 2.2, the RF sputtering power is set to 50W, the argon flow rate is 25SCCM, the pre-sputtering time is 20min, and the total sputtering time is 1min. In step 3, the heat treatment time is 0.5 hours; In step 4, the RF sputtering power is set to 20W, the argon flow rate is 25SCCM, the pre-sputtering time is 15min, and the formal sputtering time is 4min. In step 5, pre-sputtering is performed for 20 minutes.

[0026] Example 5 The difference from Example 1 is that in step 1, the processing power is 10W and the processing time is 10s; In step 2.1, the RF sputtering power is set to 50W, the argon flow rate is 20SCCM, the pre-sputtering time is 20min, and the formal sputtering time is 1min. In step 2.2, the RF sputtering power is set to 50W, the argon flow rate is 20SCCM, the pre-sputtering time is 15min, and the total sputtering time is 3min. In step 3, the heat treatment time is 0.8 hours; In step 4, the RF sputtering power is set to 15W, the argon flow rate is 20SCCM, the pre-sputtering time is 20min, and the formal sputtering time is 5min. In step 5, pre-sputtering is performed for 18 minutes.

[0027] Example 6 The difference from Example 1 is that in step 1, the processing power is 10W and the processing time is 10s; In step 2.1, the RF sputtering power is set to 48W, the argon flow rate is 23SCCM, the pre-sputtering time is 20min, and the formal sputtering time is 2min. In step 2.2, the RF sputtering power is set to 48W, the argon flow rate is 20SCCM, the pre-sputtering time is 20min, and the total sputtering time is 5min. In step 3, the heat treatment time is 0.6 hours; In step 4, the RF sputtering power is set to 15W, the argon flow rate is 20SCCM, the pre-sputtering time is 16min, and the formal sputtering time is 6min. In step 5, pre-sputter for 15 minutes.

[0028] Comparative Example 1 The fabrication of amorphous ITO thin-film transistors is carried out according to the following steps: Step 1: Transfer the substrate to the plasma treatment system and perform oxygen plasma treatment on the substrate surface. Set the treatment power to 8W and the treatment time to 5s. After the treatment is completed, remove the device.

[0029] Step 2: At room temperature, an active layer mask (with several squares arranged in an array on the active layer mask, each square having a side length of 580 μm and a spacing of 280 μm between adjacent squares) is placed over the substrate surface and transferred into the cavity. The cavity is evacuated to a pressure of 0.85 Pa using a pressure control system, and high-purity argon gas is introduced at a flow rate of 22 SCCM. The amorphous ITO target is sputtered using radio frequency (RF) at a power of 45 W to deposit the amorphous ITO thin film onto the substrate. Throughout the process, the pressure inside the chamber is maintained at 0.85 Pa, and the sputtering time is 1.5 min, resulting in an amorphous ITO thin film.

[0030] Step 3: At room temperature, an electrode mask (with several squares arranged in an array, each square having a side length of 160 μm and a spacing of 110 μm between adjacent squares) is placed over the surface of the amorphous ITO thin film. The mask is then transferred into the cavity. The cavity is evacuated to a pressure of 1.4 Pa using a pressure control system. High-purity argon gas with a flow rate of 22 SCCM is introduced. A copper electrode is deposited by DC sputtering for 18 min at a sputtering power of 18 W. The cavity pressure is maintained at 1.4 Pa throughout the process. A copper source electrode and drain electrode with a thickness of 45 nm are fabricated, resulting in an amorphous ITO thin film transistor.

[0031] like Figure 20 As shown, the mobility of the amorphous ITO thin-film transistor obtained in Comparative Example 1 is 22.25 cm⁻¹. 2 / Vs, threshold voltage is -3.13V, and on / off ratio is 2.48×10 6 ;like Figure 21 As shown, the output characteristics after applying a gate voltage (-20~50V) are as follows: when V gs At 50V, the maximum saturation current reached 0.0086mA; Figure 22 As shown, the bias stability of the amorphous ITO thin-film transistor is reflected. After applying a forward bias voltage (20V) for 60 minutes, the threshold voltage drift is 10.76V. Figure 23 As shown, this reflects the bias stability of the amorphous ITO thin-film transistor. After applying a negative bias voltage (-20V) for 60 minutes, the threshold voltage drift is -12.78V. Figure 24 As shown, the ITO thin film exhibits a high-intensity characteristic peak originating from the single-crystal Si substrate at a 2θ angle of 69.26°; Figure 25 The image shown is the AFM pattern of the amorphous ITO thin film, which shows that the roughness of the ITO film is 0.87 nm; Figure 26 The results showed peak positions typical of amorphous ITO films, with no other obvious characteristic peaks, proving that the sample was not contaminated. Figure 27 The results show that the oxygen defect content of the amorphous ITO film is 43.69%; Figure 28 As shown, the normalized noise power spectral density versus frequency curves of amorphous ITO thin-film transistors under different gate overdrive voltages are all similar to those of classical flicker noise (1 / f The noise level showed a good fit with no significant deviation, indicating that the noise behavior of the ITO / InON:SnO2:ZnON thin-film transistor is mainly 1 / f Noise is dominant, reducing instability caused by oxygen vacancies capturing and releasing charge carriers under bias conditions; such as Figure 29 As shown, the E of the amorphous ITO thin filmg The voltage is 3.67 eV, due to the presence of a large amount of V in the ITO thin film. O The introduced donor levels located below the conduction band are ionized, and electrons jump into the conduction band, causing E... F Closer to the conduction band, and oxygen vacancies will also be present in E. g The introduction of numerous localized state traps in amorphous ITO thin-film transistors (TITOs) leads to the trapping and release of electrons under bias voltage, resulting in poor stability. Figure 30 and Figure 31 As shown, the valence band density (E) of amorphous ITO thin films was determined using ultraviolet-visible spectroscopy and X-ray photoelectron spectroscopy. g and E VBM The Et of each thin film was determined using ultraviolet photoelectron spectroscopy. cutoff And through the formula φ=21.22 Ecutoff calculations yield the work function (φ) of the thin film, thus obtaining the Ecutoff of the thin film. VBM It is 2.29 eV, E cutoff It is 16.56 eV.

[0032] Comparative Example 2 The fabrication of amorphous InON:SnO2 thin-film transistors is carried out according to the following steps: Step 1: Transfer the substrate to the plasma treatment system and perform oxygen plasma treatment on the substrate surface. Set the treatment power to 8W and the treatment time to 5s. After the treatment is completed, remove the device. Step 2: At room temperature, an active layer mask (with several squares arranged in an array on the active layer mask, each square having a side length of 580 μm and a spacing of 280 μm between adjacent squares) is placed over the substrate surface and transferred into the cavity. The cavity is evacuated to a pressure of 0.85 Pa using a gas pressure control system. High-purity argon gas is introduced at a flow rate of 22 SCCM. Amorphous InON and amorphous SnO2 targets are co-sputtered. The RF sputtering power is set to 45 W and the sputtering time is 3 min. The amorphous InON:SnO2 thin film is deposited onto the substrate. Throughout the process, the gas pressure inside the chamber is maintained at 0.85 Pa to obtain the amorphous InON:SnO2 thin film. Step 3: At room temperature, an electrode mask (with several squares arranged in an array, each square having a side length of 160 μm and a spacing of 110 μm between adjacent squares) is placed over the surface of an amorphous InON:SnO2 thin film and transferred to the cavity. The cavity is evacuated to a pressure of 1.4 Pa using a gas pressure control system, and high-purity argon gas with a flow rate of 22 SCCM is introduced. A copper electrode is deposited by DC sputtering for 18 min at a sputtering power of 18 W. The cavity pressure is maintained at 1.4 Pa throughout the process. A copper source electrode and drain electrode with a thickness of 45 nm are fabricated, thus obtaining an amorphous InON:SnO2 thin film transistor. like Figure 32 As shown, the mobility of the amorphous InON:SnO2 thin-film transistor obtained in Comparative Example 2 is 32.18 cm⁻¹. 2 / Vs, threshold voltage is -9.08V, and on / off ratio is 1.93×10 6 ;like Figure 33 As shown, the output characteristics of the InON:SnO2 thin-film transistor after applying a gate voltage (-20~50V) are as follows: gs At 50V, the maximum saturation current reached 0.016mA; Figure 34 As shown, the bias stability of the amorphous InON:SnO2 thin-film transistor is reflected. After applying a forward bias voltage (20V) for 60 minutes, the threshold voltage drift is 9.92V. Figure 35 As shown, the bias stability of the amorphous InON:SnO2 thin film transistor is reflected. When a negative bias voltage (-20V) is applied for 60 minutes, the threshold voltage drift is -10.47V.

[0033] Comparative Example 3 The fabrication of ITO / InON:SnO2:ZnON thin-film transistors is carried out according to the following steps: Step 1: Transfer the substrate to the plasma treatment system and perform oxygen plasma treatment on the substrate surface. Set the treatment power to 8W and the treatment time to 5s. After the treatment is completed, remove the device. Step 2: At room temperature, an active layer mask (with several squares arranged in an array on the active layer mask, each square having a side length of 580 μm and a spacing of 280 μm between adjacent squares) is placed over the substrate surface and transferred into the cavity. An amorphous ITO target is then added into the cavity. The cavity is evacuated to a pressure of 0.85 Pa using a pressure control system. High-purity argon gas is introduced at a flow rate of 22 SCCM, and the amorphous ITO target is sputtered using radio frequency (RF) at a power of 45 W. The amorphous ITO film is deposited onto the substrate. Throughout the process, the pressure inside the cavity is maintained at 0.85 Pa, and the sputtering time is 1.5 min, resulting in an amorphous ITO film. Step 3: At room temperature, after obtaining the amorphous ITO thin film layer in Step 2, close the ITO target baffle, remove the ITO target, and simultaneously add three amorphous InON targets, amorphous SnO2 targets, and amorphous ZnON targets into the chamber. Evacuate the chamber to maintain a pressure of 0.85 Pa, set the RF sputtering power to 45 W, introduce argon gas at a flow rate of 22 SCCM, move the pressure regulating valve to maximize the resistance of the magnetron sputtering coating instrument, and open the amorphous InON target, amorphous SnO2 target, and... After the amorphous ZnON target baffle is fully ignited, the amorphous InON target, amorphous SnO2 target, and amorphous ZnON target baffle are closed for pre-sputtering for 15-20 minutes. After pre-sputtering, the sample baffle, amorphous InON target, amorphous SnO2 target, and amorphous ZnON target baffle are opened simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering for 3 minutes. During formal sputtering, the gas pressure in the chamber is maintained at 0.85 Pa to obtain an InON:SnO2:ZnON thin film layer. Among them, the sputtering time of amorphous InON target and amorphous SnO2 target remained unchanged at 3 min, and the sputtering time of amorphous ZnON target was 1 min, 2 min, 3 min, 4 min and 5 min respectively for five sets of experiments. Step 4: After the dual-channel deposition is completed, the device is transferred to a tube furnace and heat-treated in an air atmosphere at a temperature of 100°C for 0.5 to 0.8 hours. After the heat treatment is completed, the device is allowed to cool naturally to room temperature. Step 5: At room temperature, cover the InON:SnO2:ZnON thin film obtained in Step 4 with an electrode mask (the electrode mask has several squares arranged in an array, with a side length of 160 μm and a spacing of 110 μm between adjacent squares). Then transfer it to the chamber of a DC magnetron sputtering coating instrument, add a copper target to the chamber, evacuate to maintain the pressure in the chamber at 1.4 Pa, set the DC sputtering power to 18 W, and introduce argon gas at a flow rate of 22 SCCM. Move the pressure regulating valve to bring the resistance unit of the magnetron sputtering coating instrument to its maximum value, open the copper target baffle, and close the copper target baffle after the copper target ignites. Perform pre-sputtering for 15-20 minutes. After the pre-sputtering is completed, open the copper target baffle and the sample baffle at the same time, start the substrate rotation and perform formal sputtering for 18 minutes. During the formal sputtering process, the gas pressure in the chamber is maintained at 1.4 Pa to obtain a copper source electrode and drain electrode with a thickness of 45 nm, thereby obtaining an ITO / InON:SnO2:ZnON thin film transistor.

[0034] The results are as follows Figure 36 As shown, the device mobility increased to 77.85 cm⁻¹ when the ZnON target sputtering time was 3 min. 2 / Vs, threshold voltage -2.64V, on / off ratio improved to 1.07×10 7 ;like Figure 37 As shown, the output characteristics after applying a gate voltage (-20~50V) are as follows: when V gs At 50V, the maximum saturation current reached 0.26mA; Figure 38 As shown, when a forward bias voltage (20V) is applied for 60 minutes, the threshold voltage drift is 5.96V; Figure 39 As shown, when a negative bias voltage (-20V) is applied for 60 minutes, the threshold voltage drift is -1.71V, which is a significant improvement compared to Comparative Example 1. This is mainly due to the InON:SnO2:ZnON layer effectively reducing the interface state density, thereby suppressing the trapping and release of carriers under bias stress in the interface trap, and reducing the impact of PBS and NBS conditions. V TH ;like Figure 40 As shown, the voltage-capacitance curve of the ITO / InON:SnO2:ZnON thin film transistor obtained under the condition of ZnON sputtering time of 3 min in step 3 of Comparative Example 3 of this invention is shown; Figure 41 The ITO / InON:SnO2:ZnON interface also shows obvious N. CV The peak value indicates that a two-dimensional electron gas has formed at the interface of the ITO / InON:SnO2:ZnON heterojunction, and the peak electron concentration at the interface is relatively low compared with Example 2; Figure 42 The results showed peak positions expected in ITO / InON:SnO2:ZnON films, with no other obvious characteristic peaks, proving that no other impurities were introduced during the preparation of the ITO / InON:SnO2:ZnON film and the sample was not contaminated; Figure 43 The results show that the oxygen vacancy content of the ITO / InON:SnO2:ZnON film is 30.93%, which is significantly lower than that of Comparative Example 1 (43.69%), reducing instability caused by the capture and release of charge carriers by oxygen vacancies under bias conditions. Figure 44 As shown, compared to Comparative Example 1, The decrease in the value indicates that the interface defect density between the gate dielectric layer and the active layer in the device of Comparative Example 3 is reduced, the interface quality is improved, the capture of carriers by interface defects is reduced, the scattering and fluctuation during carrier transport are weaker, and the electrical performance of the device is better.

[0035] Carrier mobility, threshold voltage, on / off ratio, positive bias voltage, and negative bias voltage were tested for Examples 1-3 and Comparative Examples 1-3. The test results are shown in Table 1 and 2. Figure 2 As shown.

[0036] Table 1

[0037] As shown in Table 1, at room temperature, with the increase of ZnON sputtering time, the mobility of the ITO / InON:SnO2:ZnON thin film transistor reaches a maximum of 77.85 cm⁻¹ at a sputtering time of 3 min. 2 / Vs, threshold voltage is -2.64V, and on / off ratio reaches 1.07×10 7 With the addition of an ITO:ZnON transition electrode, the mobility of the ITO / InON:SnO2:ZnON thin-film transistor reaches a maximum of 110.03 cm⁻¹ when the thickness of the ITO:ZnON transition electrode increases to 4 nm. 2 / Vs, threshold voltage is -1.06V, and on / off ratio reaches 3.15×10 8 Furthermore, the ITO / InON:SnO2:ZnON thin-film transistor exhibits optimal positive and negative bias stability. After applying a positive bias voltage (20V) for 60 minutes, the threshold voltage drift is 1.07V; after applying a negative bias voltage (-20V) for 60 minutes, the threshold voltage drift is -0.26V; under illumination, after applying a positive bias voltage of 20V for 60 minutes, the threshold voltage drift is 1.21V; under illumination, after applying a negative bias voltage of -20V for 60 minutes, the threshold voltage drift is -0.94V.

[0038] Existing technologies still face numerous challenges in terms of performance indicators: they often achieve improvements in one aspect (such as threshold voltage, field-effect mobility, or on / off ratio), but it is difficult to simultaneously achieve high electrical performance, long-term bias stability, process thickness adaptability, and low-temperature compatibility. This has become a key bottleneck limiting the practical application of ITO-TFTs. To address the development needs of semiconductor processes compatible with existing oxide transistors, the functional partitioned all-amorphous oxide heterojunction design of this invention primarily involves oxygen plasma passivation of the substrate and the active layer interface. Non-metallic O / N is pre-cured on the target material. By adjusting the co-sputtering ratio between InON:SnO2:ZnON, InON:SnO2:ZnON back channels of varying thicknesses are constructed. These, together with the high-electron-concentration ITO front channel, form thin-layer (≤20nm) functional partitioned all-amorphous heterojunctions of varying thicknesses. Subsequently, through optimized electrode structure design, specifically using Cu and ITO:ZnON co-sputtering to form an amorphous oxide semiconductor (AOS) composite electrode structure, this composite electrode forms a homojunction interface with the back channel layer. Therefore, this invention solves the technical contradiction that high electrical performance and high bias stability of oxide transistors are difficult to coexist by using a low thermal budget (100°C) and without introducing dielectric layers and complex post-processing processes that are incompatible with semiconductor processes.

[0039] Characterization and simulation results confirm that: 1) as Figure 19 As shown, the band structure of the ITO thin film bends downwards, while the band structure of the InON:SnO2:ZnON thin film bends upwards, thus forming a potential barrier at the interface. When a forward bias is applied to the gate, this interface barrier traps electrons and induces significant electron accumulation within it, forming a quasi-two-dimensional electron gas (2DEG). This phenomenon reduces the probability of electron scattering and provides an efficient and localized transport channel for charge carriers, thereby making its field-effect mobility far exceed that of single-layer devices; 2) By adjusting the sputtering ratio of the three targets InON, SnO2, and ZnON in the back channel and their thickness ratio with ITO, the oxygen vacancy distribution is optimized and controlled to the optimal oxygen vacancy concentration, and the influence of water and oxygen in the environment on its bias stability is passivated, so that the ITO / InON:SnO2:ZnON device exhibits excellent electrical performance and bias stability at the same time; 3) In the composite electrode, the ITO:ZnON layer reduces the interface barrier between Cu and the channel layer, effectively blocking the thermal diffusion of Cu atoms into the channel layer, avoiding problems such as the increase of channel carrier trap states, threshold voltage drift and mobility decay, and the ITO:ZnON layer reduces the contact resistance between the channel and the electrode, optimizes the contact characteristics, and efficiently mobilizes the electrical performance of the oxide thin film transistor.

[0040] The above results highlight the significant advantages of the method of this invention in achieving high electrical performance and high bias stability in balanced oxide field-effect transistors. The technical solution of this invention differs significantly from existing technologies that believe high performance mainly depends on high temperature, excessively thick channel layers, or complex device structures. This invention achieves high mobility (110.03 cm⁻¹) with a thermal budget of 100°C and a 20 nm channel layer. 2 / V), high on / off ratio (3.15×10 8 This technology offers a simpler and more cost-effective solution for the field of oxide field-effect transistors (OFETs), characterized by a low threshold voltage (-1.06V) and high bias stability (PBS=1.07V, NBS=-0.26V). It also provides a low threshold voltage (-1.06V) and high bias stability (PBS=1.07V, NBS=-0.26V). This achievement meets the current urgent need for practical industrial production solutions.

[0041] This invention solves the problem of simultaneously optimizing high electrical performance and high stability in ITO / InON:SnO2:ZnON thin-film transistors. On the one hand, it achieves superior performance compared to competitors and commercial products; on the other hand, it matches the requirements of existing manufacturing processes, revolutionizing current methods that typically involve high temperatures, complex device structures, and excessive thicknesses for thin-film transistors. This method reduces production energy consumption, matches the requirements of existing low-temperature manufacturing processes, and facilitates the realization of various emerging flexible electronics based on thin-film transistors.

Claims

1. A method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors, characterized in that, The specific steps are as follows: Step 1: Perform pre-oxygen plasma treatment on the substrate surface; Step 2: Deposit an amorphous ITO thin film layer and an InON:SnO2:ZnON thin film layer on the substrate; Step 3: Perform heat treatment on the substrate after step 2; Step 4: At room temperature, amorphous ITO target and amorphous ZnON target are deposited on the InON:SnO2:ZnON thin film layer after step 3 by radio frequency co-sputtering to obtain ITO:ZnON transition electrode. Step 5: Deposit copper target material on ITO:ZnON transition electrode by DC sputtering to obtain source electrode and drain electrode.

2. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 1, characterized in that, The specific process of step 1 is as follows: the surface of the Si substrate with 100nm thermally grown SiO2 is placed into the plasma processing system for oxygen plasma treatment.

3. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 1, characterized in that, The specific process of step 2 is as follows: Step 2.1: At room temperature, an active layer mask is applied to the substrate and then transferred to the chamber of the RF magnetron sputtering coating instrument. An amorphous ITO target is added to the chamber, a vacuum is drawn, the RF sputtering power is set, argon gas is introduced, and the pressure regulating valve is moved to make the resistance unit of the magnetron sputtering coating instrument reach its maximum value. The ITO target baffle is opened, and after the amorphous ITO target is ignited, the ITO target baffle is closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle and the ITO target baffle are opened simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering to obtain an amorphous ITO thin film layer. Step 2.2: Remove the amorphous ITO target and add three amorphous InON, amorphous SnO2, and amorphous ZnON targets respectively into the chamber of the RF magnetron sputtering coating instrument. Evacuate the chamber, set the RF sputtering power, introduce argon gas, and move the pressure regulating valve to maximize the resistance of the magnetron sputtering coating instrument. Open the baffles for the amorphous InON, SnO2, and ZnON targets. Wait for the amorphous InON target... After the amorphous SnO2 and amorphous ZnON targets are fully ignited, the amorphous InON target baffle, the amorphous SnO2 target baffle, and the amorphous ZnON target baffle are turned off for pre-sputtering. After the pre-sputtering is completed, the amorphous InON target baffle, the amorphous SnO2 target baffle, the amorphous ZnON target baffle, and the sample baffle are turned on simultaneously, and the substrate rotation of the magnetron sputtering coating instrument is started for co-sputtering to obtain an InON:SnO2:ZnON thin film layer.

4. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 3, characterized in that, In step 2.1, the gas pressure in the chamber after evacuation is 0.85 Pa, the radio frequency sputtering power is 45 W to 50 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time is 15 min to 20 min, and the formal sputtering time is 1 min to 2 min.

5. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 3, characterized in that, In step 2.2, after evacuation, the gas pressure in the chamber is maintained at 0.85 Pa. The RF sputtering power is 45 W to 50 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time for the three targets is 15 min to 20 min, the co-sputtering time is 1 min to 5 min, and the gas pressure in the chamber is maintained at 0.85 Pa during the co-sputtering process.

6. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 1, characterized in that, In step 3, the heat treatment is carried out in an air atmosphere at a temperature of 100°C for a duration of 0.5 to 0.8 hours.

7. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 1, characterized in that, The specific process of step 4 is as follows: At room temperature, an electrode mask is placed on the InON:SnO2:ZnON thin film layer treated in step 3, and then transferred to the chamber of the magnetron sputtering coating instrument. Three copper targets, amorphous ITO targets, and amorphous ZnON targets are added to the chamber at the same time. Vacuum is drawn, the RF sputtering power is set, argon gas is introduced, and the pressure regulating valve is moved to make the resistance unit of the magnetron sputtering coating instrument reach its maximum value. The amorphous ZnON target baffle and the amorphous ITO target baffle are opened, while the copper target baffle is kept closed. After the amorphous ZnON target and the amorphous ITO target are ignited, the amorphous ZnON target baffle and the amorphous ITO target baffle are closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle, the amorphous ZnON target baffle, and the amorphous ITO target baffle are opened at the same time, and the substrate rotation of the magnetron sputtering coating instrument is started for formal sputtering to obtain the ITO:ZnON transition electrode.

8. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 7, characterized in that, In step 4, after evacuation, the gas pressure in the chamber is maintained at 1.4 Pa, the RF sputtering power is 15 W to 20 W, the argon flow rate is 20 SCCM to 25 SCCM, the pre-sputtering time is 15 min to 20 min, the gas pressure in the chamber is maintained at 1.4 Pa during the formal sputtering process, and the formal sputtering time is 1 min to 6 min.

9. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 1, characterized in that, The specific process of step 5 is as follows: At room temperature, after the ITO:ZnON transition electrode is sputtered, the amorphous ZnON target and the amorphous ITO target baffle are closed, and the gas pressure, argon flow rate and sputtering power in the chamber are kept constant. The copper target baffle is opened, and after the copper target is ignited, the copper target baffle is closed for pre-sputtering. After the pre-sputtering is completed, the sample baffle and the copper target baffle are opened at the same time, and the substrate rotation of the magnetron sputtering coating instrument is started for formal DC sputtering to obtain the copper source electrode and drain electrode.

10. The method for synergistically optimizing the performance of ITO / InON:SnO2:ZnON thin-film transistors according to claim 9, characterized in that, In step 5, the pre-sputtering time is 15-20 minutes, the formal sputtering time is 18 minutes, the formal sputtering power is 18W, and the gas pressure inside the chamber is maintained at 1.4Pa during the formal sputtering process.

Images