Semiconductor structure and method of fabricating the same
By forming a nanopillar array and a photoresist mask layer in a semiconductor structure through mechanical interlocking, the problem of photoresist spillage during ion implantation is solved, achieving high-precision and uniform ion implantation, and improving product yield and doping accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RONGXIN SEMICON (HUAIAN) CO LTD
- Filing Date
- 2026-05-20
- Publication Date
- 2026-06-19
AI Technical Summary
In semiconductor manufacturing, as device size shrinks and process requirements increase, photoresist is prone to peeling during ion implantation, leading to implantation pattern distortion, process chamber contamination, and reduced product yield. Existing methods have limited effectiveness in improving adhesion.
A nanopillar array is formed in the second region of the substrate, and the nanopillars are removed in the first region. The adhesion is enhanced by the mechanical interlock between the nanopillars and the photoresist mask layer. Ion implantation is performed using the photoresist mask layer as a mask to ensure the flatness of the substrate surface and the accuracy and uniformity of ion implantation.
It improves the photoresist's resistance to ion bombardment, ensures the accuracy and uniformity of the doping profile in the ion implantation region, improves implantation pattern distortion and product yield, and avoids photoresist delamination.
Smart Images
Figure CN122248976A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Ion implantation is a key process for achieving selective doping in semiconductor device manufacturing. In this process, photoresist is first coated onto the substrate surface, and patterned windows are formed within the photoresist using photolithography, allowing dopant ions to implant into the substrate through these windows. However, with the shrinking of device dimensions and the increasing demands of process technology, the dosage and energy of ion implantation are constantly increasing, leading to a sharp increase in the thermal and mechanical stresses on the photoresist. Under these conditions, the photoresist often experiences wrinkling, flow, or large-area detachment from the substrate (a phenomenon known in the industry as "resin peeling"). Resin peeling phenomena include... Figure 1 As shown, this results in distorted injection patterns, contamination of process chambers, and decreased product yield. For high aspect ratio or large-area patterns, edge stress concentration is particularly problematic.
[0003] Currently, conventional methods for improving photoresist adhesion mainly include: surface adhesion-enhancing treatments on the substrate (such as hexamethyldisilazane treatment) and the use of specially formulated photoresists. However, these methods all enhance adhesion by improving the chemical bonding or van der Waals forces between the photoresist and the substrate, and the improvement is limited, often yielding minimal results when faced with the extreme conditions of advanced processes. Summary of the Invention
[0004] One of the objectives of this application is to provide a semiconductor structure and its fabrication method, which can significantly improve the resistance of photoresist to ion bombardment and keep the substrate surface of the ion implantation region flat, ensure the accuracy of the ion implantation window pattern in the photoresist layer, improve the contour accuracy of the doped region and the uniformity of the doped ion distribution in the ion implantation region.
[0005] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure. The method includes: providing a substrate comprising a first region and a second region; forming a nanopillar array comprising a plurality of nanopillars and a photoresist mask layer in the second region, the photoresist mask layer covering the second region and the nanopillar array, and the photoresist mask layer having an ion implantation window exposing the first region; the substrate surface of the first region being a flat surface; and performing an ion implantation process using the photoresist mask layer as a mask, wherein dopant ions are implanted into the substrate of the first region through the ion implantation window.
[0006] Optionally, the method for forming a nanopillar array and a photoresist mask layer comprising multiple nanopillars in the second region includes: providing a substrate; forming a raw nanopillar array on the surface of the substrate, the raw nanopillar array covering the first region and the second region; forming a hard mask layer on the substrate, the hard mask layer covering the substrate and the raw nanopillar array; forming a patterned first photoresist layer on the substrate, the patterned first photoresist layer covering the second region and having a first opening exposing the first region; using the patterned first photoresist layer as a mask, etching away the hard mask layer on the first region; using the patterned first photoresist layer and the remaining hard mask layer as a mask, etching away the nanopillars on the first region, such that the substrate surface of the first region is flattened, and multiple nanopillars in the second region are retained as a nanopillar array located in the second region.
[0007] Optionally, the patterned first photoresist layer is used as the photoresist mask layer, and the first window is used as the ion implantation window.
[0008] Optionally, the method for forming a nanopillar array comprising multiple nanopillars and a photoresist mask layer in the second region further includes: after etching away the nanopillars on the first region, removing the patterned first photoresist layer; removing the remaining hard mask layer; forming a surface oxide layer on the substrate, the surface oxide layer covering the substrate and the nanopillars on the substrate; and forming a patterned second photoresist layer on the surface oxide layer, the patterned second photoresist layer covering the second region and having a second opening exposing the first region; wherein the patterned second photoresist layer serves as the photoresist mask layer, and the second opening serves as the ion implantation opening.
[0009] Optionally, an isotropic dry etching process is used to remove the nanopillars on the first region; the isotropic dry etching process uses an etching gas including xenon difluoride.
[0010] Optionally, the method for forming the photoresist mask layer includes: spin-coating photoresist on the substrate to form a photoresist layer; exposing and developing the photoresist layer to form a photoresist mask layer; and hard baking the photoresist mask layer, wherein the photoresist mask layer is irradiated with ultraviolet light during the hard baking process.
[0011] Optionally, the photoresist mask layer formation step includes hard baking; the hard baking includes a low-temperature stage and a high-temperature stage; in the low-temperature stage, the photoresist mask layer is continuously irradiated with a first ultraviolet light, the wavelength of the first ultraviolet light being greater than or equal to 300 nm and less than or equal to 400 nm, and the energy density of the first ultraviolet light being greater than or equal to 150 mJ / cm².2 And less than or equal to 250 mJ / cm 2 During the high-temperature stage, the photoresist mask layer is intermittently irradiated with pulsed second ultraviolet light, wherein the single-shot energy density of the second ultraviolet light is greater than or equal to 20 mJ / cm². 2 And less than or equal to 80 mJ / cm 2 The number of times the second ultraviolet light irradiation is greater than or equal to 3.
[0012] Optionally, during the high-temperature stage, the energy density gradient of the second ultraviolet light increases.
[0013] This application also provides a semiconductor structure. The semiconductor structure includes: a substrate comprising an adjacent first region and a second region, the substrate surface of the first region being a flat surface, and the substrate surface of the second region having a plurality of nanopillars; a photoresist mask layer covering the second region and having ion implantation windows exposing the first region, the photoresist mask layer covering the plurality of nanopillars and filling the spaces between the plurality of nanopillars.
[0014] Optionally, the semiconductor structure includes a hard mask layer located between the photoresist mask layer and the substrate, covering the second region and the top surface and sidewalls of the plurality of nanopillars; or, the semiconductor structure includes a surface oxide layer located between the photoresist mask layer and the substrate, covering the substrate and the plurality of nanopillars.
[0015] In the semiconductor structure and fabrication method provided in this application, the substrate includes a first region and a second region. Then, a nanopillar array including multiple nanopillars and a photoresist mask layer are formed in the second region. The photoresist mask layer covers the second region and the nanopillar array, and the photoresist mask layer has an ion implantation window that exposes the first region. Then, using the photoresist mask layer as a mask, an ion implantation process is performed, and dopant ions are implanted into the substrate of the first region from the ion implantation window. The photoresist mask layer of this application can form a strong mechanical interlock with multiple nanopillars on the second region. Due to the strong anchoring force between the photoresist mask layer and the multiple nanopillars, the photoresist mask layer does not collapse. Therefore, when using the photoresist mask layer as a mask to perform ion implantation on the first region, the photoresist mask layer can resist the thermal shock and stress during the ion implantation process. Moreover, the substrate surface of the first region to be ion implanted needs to be flat rather than an uneven surface with nanopillars. This avoids the problem of nanopillars blocking ion implantation into the substrate of the first region, ensuring the accuracy and stability of the pattern contour of the ion implantation window in the flat region. It helps to improve the uniformity of doped ion distribution in the ion implantation region. Doped ions can be precisely implanted into the substrate of the first region through the high-precision ion implantation window, ensuring the accuracy of the doping contour and improving the problems of pattern distortion in the ion doping region, process chamber contamination, and product yield reduction. Attached Figure Description
[0016] Figure 1 This is a SEM image showing photoresist peeling on the substrate.
[0017] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.
[0018] Figures 3 to 10 This is a schematic diagram illustrating the step-by-step process of a method for fabricating a semiconductor structure according to an embodiment of this application.
[0019] Figures 11 to 13 This is a schematic diagram illustrating the step-by-step process of a method for fabricating a semiconductor structure according to another embodiment of this application.
[0020] Figure 14 A partial SEM image of a semiconductor structure provided in an embodiment of this application.
[0021] Explanation of reference numerals in the attached figures: 100-substrate; 100a-first region; 100b-second region; 101-nanopillar; 102-surface oxide layer; 201-cesium chloride thin film; 201a-cesium chloride nanoisland structure; 202-hard mask layer; 203-first photoresist layer; 203a-patterned first photoresist layer; 203b-first window; 204-second photoresist layer; 204a-patterned second photoresist layer. Detailed Implementation
[0022] Research has shown that micro- and nanostructures (such as nanopillars and nanowires) can significantly enhance the adhesion of coating materials due to their large specific surface area and unique mechanical properties. However, combining this enhanced adhesion effect with the precision ion implantation process that requires extremely high flatness has become a technical contradiction, namely, there is a contradiction between the need for three-dimensional structures for enhanced adhesion and the need for flat two-dimensional planes for precision implantation.
[0023] To address this issue, the semiconductor structure and fabrication method proposed in this application resolve the contradiction between the need for a three-dimensional structure to enhance adhesion and the need for a flat two-dimensional plane for precise implantation. By retaining the nanopillar array in the second region of the substrate while removing the nanopillar array in the first region, the nanopillar array in the second region can be used to improve the bonding reliability between the photoresist mask layer and the substrate, effectively enhancing the photoresist mask layer's ability to resist thermal shock and stress during ion implantation, ensuring the accuracy and stability of the ion implantation window pattern contour. At the same time, precise ion implantation can be performed in the flat first region, ensuring the uniformity of doped ion distribution and the accuracy of the doped contour in the ion implantation region, thus improving the problems of implantation pattern distortion, process chamber contamination, and product yield reduction.
[0024] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.
[0025] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0026] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. (See reference...) Figure 2As shown, the method for fabricating the semiconductor structure provided in this application includes:
[0027] Step S1, providing a substrate, the substrate including a first region and a second region;
[0028] Step S2: A nanopillar array comprising multiple nanopillars and a photoresist mask layer are formed in the second region. The photoresist mask layer covers the second region and the nanopillar array, and the photoresist mask layer has an ion implantation window exposing the first region. The substrate surface of the first region is a flat surface.
[0029] Step S3: Using the photoresist mask layer as a mask, perform the ion implantation process, where doped ions are implanted into the substrate of the first region through the ion implantation window.
[0030] Example 1
[0031] Figures 3 to 10 This is a schematic diagram illustrating the step-by-step process of a method for fabricating a semiconductor structure according to an embodiment of this application. The following is in conjunction with... Figures 2 to 10 The method for fabricating the semiconductor structure provided in this embodiment will be described.
[0032] Execute step S1, refer to Figure 3 As shown, a substrate 100 is provided, which includes a first region 100a and a second region 100b.
[0033] In this embodiment, the first region 100a and the second region 100b can be two contiguous regions. The first region 100a is an ion implantation region, and in the subsequent ion implantation process, dopant ions need to be implanted into the substrate of the first region 100a; the second region 100b is a non-ion implantation region at least in step S3.
[0034] The material of substrate 100 may include silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator. In this embodiment, substrate 100 is a silicon substrate.
[0035] Execute step S2, refer to Figure 10 As shown, a nanopillar array including multiple nanopillars 101 and a photoresist mask layer are formed in the second region 100b. The photoresist mask layer covers the second region 100b and the nanopillar array, and the photoresist mask layer has an ion implantation window that exposes the first region 100a. The substrate surface of the first region 100a is a flat surface.
[0036] In this embodiment, step S2 includes sub-steps S21 to S25.
[0037] In step S21, refer to Figure 6As shown, a primitive nanopillar array comprising multiple nanopillars 101 is formed on the surface of the substrate 100, and the primitive nanopillar array covers the first region 100a and the second region 100b. Alternatively, in step S21, the formation region of the primitive nanopillar array covers the entire surface (i.e., the top surface) of the substrate 100, and nanopillars 101 are distributed in both the first region 100a and the second region 100b.
[0038] For example, cesium chloride self-assembly technology can be used to prepare nanopillar arrays, but it is not limited to this. Specifically, the method for preparing nanopillar arrays using cesium chloride self-assembly technology may include: (refer to...) Figure 3 As shown, after cleaning the substrate 100, it is placed in the vacuum deposition chamber, and a cesium chloride thin film 201 is evaporated. The cesium chloride thin film 201 can cover the entire surface of the substrate; Reference Figure 4 As shown, a humid gas is introduced into the vacuum coating chamber to develop a cesium chloride thin film. Under the action of the humid gas, the cesium chloride agglomerates, forming cesium chloride nano-island structures 201a on the substrate surface, resembling water droplets; Reference Figure 5 As shown, using the cesium chloride nanoisland structure 201a as a mask, the substrate 100 is etched using dry etching processes such as inductively coupled plasma etching, thereby transferring the pattern of the cesium chloride nanoisland structure 201a to the surface of the substrate 100, forming a nanopillar array including multiple nanopillars 101; Reference Figure 6 As shown, a substrate with cesium chloride nanoisland structures 201a on its surface is placed in water to dissolve and remove the cesium chloride nanoisland structures 201a. It should be noted that the height, diameter, and spacing of the nanopillars 101 in the nanopillar array can be adjusted as needed.
[0039] Step S22, refer to Figure 7 As shown, a hard mask layer 202 is formed on the substrate 100, which covers the substrate 100 and the original nanopillar array.
[0040] In step S22, the hard mask layer 202 integrally covers the surface of the substrate 100 and the original nanopillar array.
[0041] For example, the hard mask layer 202 can be formed by plasma-enhanced chemical vapor deposition or atomic layer deposition, so that the hard mask layer 202 can conformally cover the substrate 100 and the multiple nanopillars 101, that is, it can uniformly cover the top, sidewalls and gaps of each nanopillar 101. In other embodiments, the hard mask layer 202 can also be formed by other deposition methods.
[0042] In this embodiment, the material of the hard mask layer 202 can be silicon oxide (SiO2). In other embodiments, the material of the hard mask layer 202 can be silicon nitride (Si3N4), but is not limited thereto.
[0043] Step S23, refer to Figure 9 As shown, a patterned first photoresist layer 203a is formed on the substrate 100. The patterned first photoresist layer 203a covers the second region 100b and has a first window 203b that exposes the first region 100a.
[0044] Specifically, the method for forming the patterned first photoresist layer 203a may include: referencing Figure 8 As shown, a first photoresist layer 203 is formed by spin-coating photoresist onto a substrate 100; Reference Figure 9 As shown, the first photoresist layer 203 is exposed and developed to form a patterned first photoresist layer 203a, which covers the second region 100b and exposes the first region 100a; the patterned first photoresist layer 203a is then hard baked.
[0045] It should be noted that the patterned first photoresist layer 203a fills the spaces between the multiple nanopillars 101 in the second region 100b, forming a strong mechanical interlock. The strong anchoring force between the patterned first photoresist layer 203a and the multiple nanopillars 101 makes the patterned first photoresist layer 203a less prone to peeling during subsequent processes, effectively resisting thermal shock and stress during ion implantation. For example, the patterned first photoresist layer 203a can be a thick layer with a thickness greater than or equal to 3µm and less than or equal to 10µm. Since the multiple nanopillars 101 on the substrate 100 provide a mechanical anchoring basis for the patterned first photoresist layer 203a, the thick layer is less prone to peeling after ion implantation.
[0046] In this embodiment, the patterned first photoresist layer 203a is subsequently used as a photoresist mask layer (i.e., as a mask for ion implantation). In order to further improve the ability of the patterned first photoresist layer 203a to resist ion bombardment, during the hard baking process of the patterned first photoresist layer 203a, ultraviolet light is used to irradiate the patterned first photoresist layer 203a. In this way, the free radicals generated by the photoinitiator initiate the cross-linking reaction between the photoresist molecular chains, so that the photoresist forms a relatively stable cross-chain structure.
[0047] For example, the hard baking of the patterned first photoresist layer 203a includes a low-temperature stage and a high-temperature stage; for example, the temperature of the low-temperature stage is greater than or equal to 80°C and less than or equal to 120°C; the temperature of the high-temperature stage is greater than or equal to 120°C and less than or equal to 150°C. In the low-temperature stage, the temperature can be gradually increased, for example, at a heating rate of 0.25°C / s; in the high-temperature stage, the temperature can be maintained at the same temperature, but is not limited thereto.
[0048] For example, during the low-temperature stage, the patterned first photoresist layer 203a is continuously irradiated with a first ultraviolet light, the wavelength of which is greater than or equal to 300 nm and less than or equal to 400 nm, and the energy density of which is greater than or equal to 150 mJ / cm². 2 And less than or equal to 250 mJ / cm 2 During the high-temperature stage, the patterned first photoresist layer 203a is intermittently irradiated with pulsed second ultraviolet light, and the single-shot energy density of the second ultraviolet light is greater than or equal to 20 mJ / cm². 2 And less than or equal to 80 mJ / cm 2 The second ultraviolet light irradiation is performed at least three times. In other embodiments, the wavelengths and energies of the first and second ultraviolet light can be adjusted as needed.
[0049] It should be noted that, in the low-temperature stage, the first ultraviolet light can induce free radical cross-linking in the patterned first photoresist layer 203a to form a three-dimensional framework network, which helps to improve the ability of the photoresist layer to suppress thermal deformation; in the high-temperature stage, the thermally activated epoxy groups undergo ring-opening polymerization to fill the network gaps, and a highly cross-linked armor layer is formed on the surface of the patterned first photoresist layer 203a by the second ultraviolet light, which further improves the stability of the photoresist layer, for example, it can make the modulus of the patterned first photoresist layer 203a greater than 5 GPa.
[0050] Furthermore, during the high-temperature stage, the energy density of the second ultraviolet light can be gradually increased, which effectively prevents the photoresist from cracking due to gases generated during photoresist formation, resulting in higher pattern precision. The energy density of the second ultraviolet light can be increased by 10% to 20% per cycle. The patterned first photoresist layer 203a can be hard-baked in a vacuum or inert gas environment with an oxygen content of <10ppm.
[0051] Step S24, as follows Figure 9 As shown, using a patterned first photoresist layer 203a as a mask, the hard mask layer 202 on the first region 100a is etched away to expose the nanopillars 101 on the first region 100a. The remaining hard mask layer 202 can still cover the second region 100b and the multiple nanopillars 101 on the second region 100b.
[0052] For example, the hard mask layer 202 on the first region 100a can be removed by a dry etching process, and the gas used in the dry etching process includes, but is not limited to, CF4; the hard mask layer 202 on the first region 100a can also be removed by a wet etching process, and the etching solution used in the wet etching process can include hydrofluoric acid solution.
[0053] Step S25, refer to Figure 10As shown, using the patterned first photoresist layer 203a and the remaining hard mask layer 202 as masks, the nanopillars 101 on the first region 100a are etched away, making the substrate surface of the first region 100a flat, and retaining multiple nanopillars 101 on the second region 100b as a nanopillar array located on the second region 100b. The remaining hard mask layer 202 is the hard mask layer located on the second region 100b.
[0054] For example, an isotropic dry etching process can be used to remove the nanopillars 101 on the first region 100a. Preferably, the etching gas used in the isotropic dry etching process may include xenon difluoride (XeF2). Xenon difluoride gas can undergo a vigorous spontaneous chemical reaction with silicon to generate volatile SiF4, while the etching rate on SiO2 or Si3N4 masks is extremely slow. The etching selectivity ratio of silicon to hard mask layer 202 is as high as 1000:1 or more. This allows for the complete removal of the nanopillars 101 in the first region 100a without damaging the second region 100b protected by the remaining hard mask layer 202. In other embodiments, the etching gas used to etch the nanopillars 101 in the first region 100a can be adjusted as needed.
[0055] In this embodiment, after etching away the nanopillars 101 of the first region 100a, the substrate surface of the first region 100a can be restored to flatness. This avoids the problem of the nanopillars 101 blocking ion implantation into the substrate of the first region 100a, and helps to achieve precise ion implantation.
[0056] In this embodiment, the patterned first photoresist layer 203a is used as the photoresist mask layer, and the first window 203b is used as the ion implantation window; that is, in step S3, the reference... Figure 10 As shown, using the patterned first photoresist layer 203a and the remaining hard mask layer 202 as masks, an ion implantation process is performed, in which doped ions are implanted from the first window 203b into the substrate of the first region 100a, forming an ion-doped region in the substrate of the first region 100a.
[0057] It should be noted that in this embodiment, the patterned first photoresist layer 203a is used as the mask for removing the hard mask layer 202 of the first region 100a, and the patterned first photoresist layer 203a and the remaining hard mask layer 202 of the second region 100b are used as the mask for removing the nanopillars 101 of the first region 100a and as the mask for ion implantation of the first region 100a. This can achieve self-alignment of ion implantation, avoid the need for a second photolithography alignment and avoid alignment errors during the second photolithography alignment, which helps to improve the accuracy of ion implantation, simplify photolithography process steps, save manufacturing costs and production time.
[0058] The patterned first photoresist layer 203a can form a strong mechanical interlock with the multiple nanopillars 101 on the second region 100b. That is, the patterned first photoresist layer 203a does not fall off due to the strong anchoring force between it and the multiple nanopillars 101. Therefore, when the patterned first photoresist layer 203a is used as a mask to perform ion implantation on the first region 100a, the patterned first photoresist layer 203a can resist the thermal shock and stress during the ion implantation process, ensuring the accuracy and stability of the pattern contour of the ion implantation window. Moreover, it meets the requirement that the substrate surface of the first region, which is the ion implantation area, needs to be flat, which can realize precise ion implantation and ensure the accuracy of the ion doping region contour and the uniformity of the doped ion distribution in the ion implantation area.
[0059] In this embodiment, after the ion implantation process is completed, the patterned first photoresist layer 203a, the remaining hard mask layer 202, and the nanopillars 101 on the second region 100b can be removed.
[0060] Accordingly, this embodiment also provides a semiconductor structure, which can be fabricated using the semiconductor structure fabrication method described above. (Reference) Figure 10 As shown, the semiconductor structure includes a substrate 100 and a photoresist mask layer. The substrate 100 includes adjacent first regions 100a and second regions 100b. The substrate surface of the first region 100a is a flat surface, and the substrate surface of the second region 100b has a plurality of nanopillars 101. The photoresist mask layer covers the second region 100b and has ion implantation windows exposing the first region 100a. The photoresist mask layer covers the plurality of nanopillars 101 and fills the spaces between the nanopillars 101. In this embodiment, the photoresist mask layer is a patterned first photoresist layer 203a, and the ion implantation window is a first window 203b.
[0061] Furthermore, the semiconductor structure may also include a hard mask layer 202, which is located between the substrate 100 and the photoresist mask layer, that is, the hard mask layer 202 is located between the substrate 100 and the patterned first photoresist layer 203a, covering the second region 100b and the top surface and sidewalls of the plurality of nanopillars 101 of the second region.
[0062] Furthermore, the substrate of the first region 100a may have an ion-doped region, which corresponds to the position of the first window 203b.
[0063] Figure 14This is a partial SEM image of a semiconductor structure provided in an embodiment of this application. In the semiconductor structure provided in this embodiment, the mechanical interlocking between the photoresist mask layer and the nanopillars 101 enhances the adhesion of the photoresist mask layer to the surface of the substrate 100, and simultaneously improves the photoresist mask layer's resistance to thermal shock and stress during ion implantation, thereby achieving... Figure 14 As shown, the photoresist mask layer does not exhibit photoresist peeling during ion implantation.
[0064] Example 2
[0065] The main difference between this embodiment and Embodiment 1 is that the patterned second photoresist layer is used as a mask to perform ion implantation on the first region; the similarities between this embodiment and Embodiment 1 can be found in Embodiment 1.
[0066] Figures 11 to 13 This is a schematic diagram illustrating the step-by-step process of a method for fabricating a semiconductor structure according to another embodiment of this application. The following is in conjunction with... Figures 11 to 13 The method for fabricating the semiconductor structure in this embodiment will be described.
[0067] In this embodiment, the etching process for removing the nanopillars 101 on the first region 100a and the preceding steps can be the same as in Embodiment 1. Alternatively, in this embodiment, step S2 includes the aforementioned steps S21 to S25, and also includes the following steps S26 to S29.
[0068] Specifically, after etching away the nanopillars 101 on the first region 100a using the patterned first photoresist layer 203a and the remaining hard mask layer 202 as a mask, referencing Figure 11 As shown, in this embodiment, step S26 is performed to remove the patterned first photoresist layer 203a.
[0069] For example, an ashing process can be used to remove the patterned first photoresist layer 203a.
[0070] Perform step S27 to remove the remaining hard mask layer 202, that is, remove the hard mask layer 202 on the second region 100b.
[0071] For example, a wet etching process can be used to remove the remaining hard mask layer 202, but it is not limited thereto. For instance, the etching solution used in the wet etching process may include hydrofluoric acid.
[0072] In another embodiment of this application, after step S24, that is, after etching away the hard mask layer 202 on the first region 100a using the patterned first photoresist layer 203a as a mask, the patterned first photoresist layer 203a can be removed first, and then the remaining hard mask layer 202 can be used as a mask to etch away the nanopillars 101 on the first region 100a.
[0073] Execute step S28, refer to Figure 12 As shown, a surface oxide layer 102 is formed on the substrate 100, and the surface oxide layer 102 covers the substrate 100 and the nanopillars 101 on the substrate 100.
[0074] Specifically, the surface oxide layer 102 covers the first region 100a and the second region 100b of the substrate, meaning that the surface oxide layer 102 completely covers the top surface of the substrate 100. The surface oxide layer 102 can protect the substrate surface of the first region 100a during subsequent ion implantation processes.
[0075] For example, the surface oxide layer 102 can be formed by a thermal oxidation process performed inside a furnace tube. The material of the surface oxide layer 102 can be silicon oxide.
[0076] Execute step S29, refer to Figure 13 As shown, a patterned second photoresist layer 204a is formed on the surface oxide layer 102. The patterned second photoresist layer 204a covers the second region 100b and has a second opening 204b that exposes the first region 100a.
[0077] Specifically, the method for forming the patterned second photoresist layer 204a may include: referring to Figure 12 As shown, a second photoresist layer 204 is formed by spin-coating photoresist on a substrate 100; the second photoresist layer 204 is exposed and developed to form a patterned second photoresist layer 204a; the patterned second photoresist layer 204a is hard baked, and ultraviolet light is used to irradiate the patterned second photoresist layer 204a during the hard baking process.
[0078] In this embodiment, during the hard baking process of the patterned second photoresist layer 204a, ultraviolet light is used to irradiate the patterned second photoresist layer 204a. In this way, the free radicals generated by the photoinitiator initiate the cross-linking reaction between the photoresist molecular chains, so that the photoresist forms a more stable cross-chain structure, so that the patterned second photoresist layer 204a can better resist the ion bombardment of ion implantation.
[0079] For example, the hard baking of the patterned second photoresist layer 204a includes a low-temperature stage and a high-temperature stage; for example, the temperature of the low-temperature stage is greater than or equal to 80°C and less than or equal to 120°C; the temperature of the high-temperature stage is greater than or equal to 120°C and less than or equal to 150°C. In the low-temperature stage, the temperature can be gradually increased; in the high-temperature stage, the temperature can be maintained at the same temperature, but is not limited thereto.
[0080] For example, during the low-temperature stage, the patterned second photoresist layer 204a is continuously irradiated with a first ultraviolet light, the wavelength of which is greater than or equal to 300 nm and less than or equal to 400 nm, and the energy density of which is greater than or equal to 150 mJ / cm². 2 And less than or equal to 250 mJ / cm 2 During the high-temperature stage, the patterned second photoresist layer 204a is intermittently irradiated with pulsed second ultraviolet light, and the single-shot energy density of the second ultraviolet light is greater than or equal to 20 mJ / cm². 2 And less than or equal to 80 mJ / cm 2 The second ultraviolet light irradiation is performed at least three times. In other embodiments, the wavelengths and energies of the first and second ultraviolet light can be adjusted as needed.
[0081] In this embodiment, the patterned second photoresist layer 204a is used as the photoresist mask layer, and the second window 204b is used as the ion implantation window. That is, in this embodiment, the patterned second photoresist layer 204a is used as the ion implantation mask, so that when performing hard baking of the patterned first photoresist layer 203a, it is not necessary to use ultraviolet light to irradiate the patterned first photoresist layer 203a. Of course, if it is necessary to improve the structural stability of the patterned first photoresist layer 203a, ultraviolet light can also be used to irradiate the patterned first photoresist layer 203a.
[0082] Execute step S3, refer to Figure 13 As shown, using the patterned second photoresist layer 204a as a mask, an ion implantation process is performed, and doped ions are implanted from the second window 204b into the substrate of the first region 100a to form an ion-doped region.
[0083] It should be noted that, since the patterned second photoresist layer 204a fills the spaces between the multiple nanopillars 101 in the second region 100b to form a strong mechanical interlock, the strong anchoring force between the patterned second photoresist layer 204a and the multiple nanopillars 101 prevents the patterned second photoresist layer 204a from falling off, effectively resisting thermal shock and stress during ion implantation. In this embodiment, the patterned second photoresist layer 204a is reformed after the patterned first photoresist 203a is removed, without undergoing multiple etching processes (e.g., without etching of the hard mask layer 202 and the nanopillars 101 in the first region 100a), and is not subject to damage to the photoresist morphology or consumption caused by various gases or acids used in multiple etching processes. Therefore, there is no problem that the photoresist mask layer cannot meet the blocking requirements during ion implantation. Furthermore, in this embodiment, after removing the plurality of nanopillars 101 of the first region 100a, the patterned first photoresist layer 203a is removed and an ion implantation mask (i.e., the patterned second photoresist layer 204a) is re-formed on the substrate 100, thereby forming a surface oxide layer 102 on the substrate 100 to better protect the substrate surface of the first region 100a during the ion implantation process.
[0084] For example, the patterned second photoresist layer 204a can be a thick photoresist layer with a thickness greater than or equal to 3µm and less than or equal to 10µm. Since the multiple nanopillars 101 on the substrate 100 provide a mechanical anchoring basis for the patterned second photoresist layer 204a, the thick photoresist layer will not have a problem of photoresist peeling after ion implantation.
[0085] In this embodiment, after the ion implantation process is completed, the patterned second photoresist layer 204a, the surface oxide layer 102, and the nanopillars 101 on the second region 100b can be removed sequentially.
[0086] Accordingly, this embodiment also provides a semiconductor structure, which can be fabricated using the semiconductor structure fabrication method of this embodiment. (Reference) Figure 13 As shown, the semiconductor structure may include a substrate 100 and a photoresist mask layer; the substrate 100 includes adjacent first regions 100a and second regions 100b, the substrate surface of the first region 100a is a flat surface, and the substrate surface of the second region 100b has a plurality of nanopillars 101; the photoresist mask layer covers the second region 100b and has ion implantation windows exposing the first region 100a, and the photoresist mask layer covers the plurality of nanopillars 101 and fills the spaces between the plurality of nanopillars 101. In this embodiment, the photoresist mask layer is a patterned second photoresist layer 204a, and the ion implantation window is a second window 204b.
[0087] Furthermore, the semiconductor structure may also include a surface oxide layer 102, which is located between the substrate 100 and the patterned second photoresist layer 204a, covering the substrate 100 and a plurality of nanopillars 101.
[0088] In the semiconductor structure and fabrication method provided in this application, the provided substrate 100 includes a first region 100a and a second region 100b. Then, a nanopillar array including multiple nanopillars 101 and a photoresist mask layer are formed in the second region 100b. The photoresist mask layer covers the second region 100b and the nanopillar array, and the photoresist mask layer has an ion implantation window that exposes the first region 100a. Then, using the photoresist mask layer as a mask, an ion implantation process is performed, and doped ions are implanted into the substrate of the first region from the ion implantation window. The photoresist mask layer of this application can form a strong mechanical interlock with multiple nanopillars 101 on the second region 100b. Due to the strong anchoring force between the photoresist mask layer and the multiple nanopillars 101, the photoresist mask layer does not collapse. Therefore, when using the photoresist mask layer as a mask to perform ion implantation on the first region 100a, the photoresist mask layer can resist the thermal shock and stress during the ion implantation process. Moreover, the substrate surface of the first region 100a to be ion implanted needs to be flat rather than an uneven surface with nanopillars. This avoids the problem of nanopillars 101 blocking ion implantation into the substrate of the first region 100a, ensuring the accuracy and stability of the pattern contour of the ion implantation window in the flat region, which helps to improve the uniformity of doped ion distribution in the ion implantation region. Doped ions can be precisely implanted into the substrate of the first region 100a through the high-precision ion implantation window, ensuring the accuracy of the doping contour and improving the problems of pattern distortion in the ion doping region, process chamber contamination, and product yield reduction.
[0089] It should be noted that this instruction manual uses a progressive approach, with later descriptions focusing on the differences from earlier descriptions. Similarities and similarities between different sections can be found by referring to each other.
[0090] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of the claims of this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A nanopillar array comprising multiple nanopillars and a photoresist mask layer are formed in the second region. The photoresist mask layer covers the second region and the nanopillar array, and the photoresist mask layer has an ion implantation window that exposes the first region. The substrate surface in the first region is a flat surface; Using the photoresist mask layer as a mask, an ion implantation process is performed, in which doped ions are implanted into the substrate of the first region through the ion implantation window.
2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method for forming a nanopillar array comprising multiple nanopillars and a photoresist mask layer in the second region includes: A primitive nanopillar array comprising multiple nanopillars is formed on the surface of the substrate, the primitive nanopillar array covering the first region and the second region; and A hard mask layer is formed on the substrate, the hard mask layer covering the substrate and the original nanopillar array; A patterned first photoresist layer is formed on the substrate, the patterned first photoresist layer covering the second region and having a first opening exposing the first region; Using the patterned first photoresist layer as a mask, the hard mask layer on the first region is etched away. Using the patterned first photoresist layer and the remaining hard mask layer as a mask, the nanopillars on the first region are etched away, making the substrate surface of the first region flat, and retaining multiple nanopillars in the second region as a nanopillar array located on the second region.
3. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The patterned first photoresist layer is used as the photoresist mask layer, and the first window is used as the ion implantation window.
4. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The method for forming a nanopillar array comprising multiple nanopillars and a photoresist mask layer in the second region further includes: After the etching removes the nanopillars on the first region, the patterned first photoresist layer is removed. Remove the remaining hard mask layer; A surface oxide layer is formed on the substrate, the surface oxide layer covering the substrate and the nanopillars on the substrate; and A patterned second photoresist layer is formed on the surface oxide layer, the patterned second photoresist layer covering the second region and having a second opening exposing the first region; Wherein, the patterned second photoresist layer is used as the photoresist mask layer, and the second opening is used as the ion implantation opening.
5. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The nanopillars on the first region are removed using an isotropic dry etching process; the etching gas used in the isotropic dry etching process includes xenon difluoride.
6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method for forming the photoresist mask layer includes: A photoresist layer is formed by spin-coating photoresist onto the substrate; The photoresist layer is exposed and developed to form the photoresist mask layer; and The photoresist mask layer is hard baked, and ultraviolet light is used to irradiate the photoresist mask layer during the hard baking process.
7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The photoresist mask layer formation step includes hard baking; the hard baking includes a low-temperature stage and a high-temperature stage; in the low-temperature stage, the photoresist mask layer is continuously irradiated with a first ultraviolet light, the wavelength of the first ultraviolet light being greater than or equal to 300 nm and less than or equal to 400 nm, and the energy density of the first ultraviolet light being greater than or equal to 150 mJ / cm². 2 And less than or equal to 250 mJ / cm 2 During the high-temperature stage, the photoresist mask layer is intermittently irradiated with pulsed second ultraviolet light, wherein the single-shot energy density of the second ultraviolet light is greater than or equal to 20 mJ / cm². 2 And less than or equal to 80 mJ / cm 2 The number of times the second ultraviolet light irradiation is greater than or equal to 3.
8. The method for fabricating a semiconductor structure as described in claim 7, characterized in that, During the high-temperature stage, the energy density gradient of the second ultraviolet light increases.
9. A semiconductor structure, characterized in that, include: The substrate includes an adjacent first region and a second region, wherein the substrate surface of the first region is a flat surface and the substrate surface of the second region has a plurality of nanopillars. A photoresist mask layer covers the second region and has ion implantation windows exposing the first region, the photoresist mask layer covers a plurality of nanopillars and fills the spaces between the plurality of nanopillars.
10. The semiconductor structure as described in claim 9, characterized in that, The semiconductor structure includes a hard mask layer located between the photoresist mask layer and the substrate, covering the second region and the top surface and sidewalls of the plurality of nanopillars; or, The semiconductor structure includes a surface oxide layer located between the photoresist mask layer and the substrate, covering the substrate and the plurality of nanopillars.