Bottom-up plating of glass vias
Metallization of conductive vias in glass substrates using bottom-up electroplating technology solves the CTE mismatch-induced stress problem, improves the structural integrity of glass substrates and the reliability of multilayer integration, and reduces costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INTEL CORP
- Filing Date
- 2025-11-16
- Publication Date
- 2026-06-19
AI Technical Summary
Metallization of conductive vias (TGVs) in glass substrates presents a CTE mismatch-induced stress problem, which leads to structural integrity damage and warping. Existing technologies make it difficult to achieve multilayer integration of glass substrates efficiently and at low cost.
A bottom-up electroplating technique is employed, including subtractive etching, a modified semi-additive process, and a flowable cavity-filling material. This avoids the use of seed materials on the TGV opening sidewalls and is combined with an inner liner to alleviate CTE mismatch-induced stress and reduce processing steps.
It effectively reduces CTE mismatch-induced stress, improves the structural integrity of the glass substrate and the reliability of multilayer integration, reduces costs and increases design flexibility.
Smart Images

Figure CN122249058A_ABST