3dic package structure and method of manufacturing the same
By using hybrid bonding and damascus wiring layer technology, multiple chips are stacked together, solving the problem of high-density integration in semiconductor packaging structures. This enables efficient multi-layer memory wafer stacking and electrical connection of logic chips, improving heat dissipation performance and interconnection efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SJ SEMICONDUCTOR (JIANGYIN) CORP
- Filing Date
- 2024-12-17
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, semiconductor packaging structures are difficult to achieve high-density integration, and the density of storage electronic components is growing slowly, especially after the 3nm process node.
Multiple chips are stacked together using hybrid bonding technology, electrically connected using damascus wiring layers, and combined with TSV metal pillars and trench capacitors to achieve multi-layer memory wafer stacking and back-side power supply for logic chips. A heat dissipation metal structure is used to improve heat dissipation performance.
It effectively reduces package thickness, package structure size, transmission distance, and power consumption, making it suitable for high-density interconnects and multi-layer memory wafer stacking.
Smart Images
Figure CN122249063A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a 3DIC packaging structure and its preparation method. Background Technology
[0002] In the AI era, the larger the number of model parameters, the more data is used to train the model, the greater the computational load for training the model, and the better the corresponding model performance. In the future, the computing power demand for large models will maintain a trend of doubling every 6 months, that is, maintaining a high-speed growth rate of about 4 times per year.
[0003] As chip manufacturing processes advance, it becomes increasingly difficult to increase the number of storage electronic components in a single die, and the compound growth rate of storage electronic component density is slowing down, especially after the 3nm process node.
[0004] 3DIC (three-dimensional integrated circuit) platform is a new type of integrated circuit technology that stacks multiple chips together and interconnects them via vertical connections. 3DIC typically refers to an IC package with multiple device layers. Chip designers can optimize the integrated circuit structure by interconnecting at the scale of storage electronics and functional modules. The interconnect lengths between integrated circuits on different device layers can be reduced from the millimeter level to the micrometer level, allowing signals to propagate as quickly as those within the same integrated circuit.
[0005] Therefore, it is necessary to provide a 3DIC packaging structure and its fabrication method. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a 3DIC packaging structure and its preparation method, so as to solve the problem that it is difficult to achieve high-density integration in the semiconductor packaging structure in the prior art.
[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a 3DIC packaging structure, comprising the following steps:
[0008] A first memory wafer and a second memory wafer are provided. The first memory wafer includes a first silicon substrate, a first memory electronic element, and a first damask wiring layer, and the first damask wiring layer is electrically connected to the first memory electronic element. The second memory wafer includes a second silicon substrate, a second memory electronic element, and a second damask wiring layer, and the second damask wiring layer is electrically connected to the second memory electronic element.
[0009] The first memory wafer and the second memory wafer are hybrid bonded together, and the first damask wiring layer and the second damask wiring layer are electrically connected.
[0010] Thinning of the first silicon substrate;
[0011] A first TSV metal pillar is formed in the first silicon substrate, and the first TSV metal pillar is electrically connected to the first memory wafer;
[0012] A third damasc network layer is formed on the first silicon substrate, and the third damasc network layer is electrically connected to the first TSV metal pillar.
[0013] A logic chip is provided, the logic chip comprising a third silicon substrate, transistors, and a fourth damask wiring layer;
[0014] The logic chip is formed on the third damask wiring layer using an inverted hybrid bonding method, and the fourth damask wiring layer is electrically connected to the third damask wiring layer.
[0015] Thinning of the third silicon substrate;
[0016] An insulating layer is formed on the third damask wiring layer, the insulating layer covering the third damask wiring layer and encapsulating the logic chip;
[0017] A metal element is formed in the insulating layer, the metal element penetrating the insulating layer and electrically connected to the third damask wiring layer;
[0018] A silicon wafer is provided, the silicon wafer comprising a fourth silicon substrate, a second TSV metal pillar, a trench capacitor and a fifth damascus wiring layer, wherein the fifth damascus wiring layer is electrically connected to the second TSV metal pillar and the trench capacitor.
[0019] The silicon wafer is mixed and bonded to the insulating layer, and the fifth damascus wiring layer is electrically connected to the metal component;
[0020] Thinning the fourth silicon substrate exposes the metal component;
[0021] A redistribution layer is formed on the fourth silicon substrate, and the redistribution layer is electrically connected to the second TSV metal pillar;
[0022] Metal bumps are formed on the redistribution layer, and the metal bumps are electrically connected to the redistribution layer.
[0023] The cutting process is carried out to form a 3DIC package structure.
[0024] Optionally, the method further includes the following step to fabricate the 3DIC package structure with N > 2 stacked storage wafers:
[0025] A third memory wafer is provided, the third memory wafer including a fifth silicon substrate, a third memory electronic element and a sixth damascus wiring layer, and the sixth damascus wiring layer is electrically connected to the third memory electronic element;
[0026] The third memory wafer is bonded to the second memory wafer, and the sixth damask wiring layer is electrically connected to the second damask wiring layer.
[0027] Remove the fifth silicon substrate to expose the sixth damascus wiring layer;
[0028] The first memory wafer and the third memory wafer are hybrid bonded together, and the first damask wiring layer is electrically connected to the sixth damask wiring layer.
[0029] Optionally, the method for forming the insulating layer includes a deposition process or a spin coating process; the insulating layer includes one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate phosphosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
[0030] Optionally, the thickness of the thinned third silicon substrate is 1 to 50 μm; the thickness of the thinned fourth silicon substrate is 1 to 50 μm; and the total thickness of the insulating layer, the third damask wiring layer, the first memory wafer, the second memory wafer, the silicon wafer, and the redistribution layer is less than 100 μm.
[0031] Optionally, the second silicon substrate further comprises a heat-dissipating metal structure, and the method for forming the heat-dissipating metal structure includes through-silicon via (TSV) technology.
[0032] The present invention also provides a 3DIC package structure, the 3DIC package structure comprising:
[0033] The first memory wafer includes a first silicon substrate, a first memory electronic component, and a first damask wiring layer, wherein the first damask wiring layer is electrically connected to the first memory electronic component.
[0034] The second memory wafer includes a second silicon substrate, a second memory electronic component, and a second damask wiring layer, wherein the second damask wiring layer is electrically connected to the second memory electronic component; wherein the first memory wafer and the second memory wafer are hybrid bonded, and the first damask wiring layer is electrically connected to the second damask wiring layer.
[0035] The first TSV metal pillar penetrates the first silicon substrate and is electrically connected to the first memory wafer.
[0036] The third damascus wiring layer is located on the first silicon substrate and is electrically connected to the first TSV metal pillar.
[0037] A logic chip, comprising a third silicon substrate, transistors and a fourth damask wiring layer, wherein the logic chip is inverted and hybrid-bonded to the third damask wiring layer, and the fourth damask wiring layer is electrically connected to the third damask wiring layer.
[0038] An insulating layer is located on the third damask wiring layer, covers the third damask wiring layer, and encapsulates the logic chip;
[0039] A metal component that penetrates the insulating layer and is electrically connected to the third damask wiring layer;
[0040] A silicon wafer, wherein the silicon wafer is mixed-bonded with the insulating layer, comprising a fourth silicon substrate, a second TSV metal pillar, a trench capacitor and a fifth damascus wiring layer, wherein the fifth damascus wiring layer is electrically connected to the second TSV metal pillar and the trench capacitor, and the fifth damascus wiring layer is electrically connected to the metal component.
[0041] A redistribution layer, the redistribution layer being located on the fourth silicon substrate and electrically connected to the second TSV metal pillar;
[0042] A metal bump, the metal bump being located on the redistribution layer and electrically connected to the redistribution layer.
[0043] Optionally, M layers of memory wafers are stacked between the first memory wafer and the second memory wafer, where M ≥ 1.
[0044] Optionally, the insulating layer includes one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
[0045] Optionally, the thickness of the third silicon substrate is 1 to 50 μm; the thickness of the fourth silicon substrate is 1 to 50 μm; and the total thickness of the insulating layer, the third damask wiring layer, the first memory wafer, the second memory wafer, the silicon wafer, and the redistribution layer is less than 100 μm.
[0046] Optionally, the second silicon substrate also has a heat dissipation metal structure.
[0047] As described above, the 3DIC packaging structure and its fabrication method of the present invention achieve electrical connection by hybrid bonding of a first memory wafer and a second memory wafer through a first damask wiring layer and a second damask wiring layer; achieve electrical connection between the logic chip and the memory wafer through hybrid bonding of a third damask wiring layer and a fourth damask wiring layer; provide back-side power to the logic chip through metal components, a fifth damask wiring layer, a second TSV metal pillar, and a rewiring layer; the first TSV metal pillar prepared by thinning the first silicon substrate and the second TSV metal pillar prepared by thinning the fourth silicon substrate can be directly used as a TSV adapter board, and trench capacitors can be fabricated in the fourth silicon substrate; the second silicon substrate can be directly used as a support substrate, and further, a second silicon substrate with a heat dissipation metal structure can be provided to improve the heat dissipation performance of the 3DIC packaging structure. The 3DIC packaging structure of the present invention can effectively reduce the packaging thickness, reduce the packaging structure size, effectively shorten the transmission distance, and reduce power consumption, and is particularly suitable for high-density interconnects, and can realize the stacking of multiple memory wafers. Attached Figure Description
[0048] Figure 1 The diagram shows a schematic of the fabrication process of the 3DIC packaging structure in an embodiment of the present invention.
[0049] Figure 2 The diagram shown is a structural schematic of the first storage wafer in an embodiment of the present invention.
[0050] Figure 3 The diagram shown is a schematic representation of the structure of the first and second memory wafers after hybrid bonding in an embodiment of the present invention.
[0051] Figure 4 The diagram shown is a schematic representation of the structure of the first silicon substrate after thinning in an embodiment of the present invention.
[0052] Figure 5 The diagram shows the structure after the first TSV metal column is formed in an embodiment of the present invention.
[0053] Figure 6 The diagram shown is a structural schematic of the third damascus wiring layer after it has been formed in an embodiment of the present invention.
[0054] Figure 7 The diagram shown is a structural schematic of the bonded logic chip in an embodiment of the present invention.
[0055] Figure 8 Displayed as Figure 7 A schematic diagram of the logic chip structure.
[0056] Figure 9 The diagram shown is a schematic representation of the structure after thinning the third silicon substrate in an embodiment of the present invention.
[0057] Figure 10 The diagram shown is a schematic representation of the structure after the insulating layer is formed in an embodiment of the present invention.
[0058] Figure 11 The diagram shown is a schematic representation of the structure after the metal column is formed in an embodiment of the present invention.
[0059] Figure 12 This is a schematic diagram of the structure after the second TSV metal pillar is formed in the fourth silicon substrate in an embodiment of the present invention.
[0060] Figure 13 The diagram shows a structural schematic of a trench capacitor formed in a fourth silicon substrate according to an embodiment of the present invention.
[0061] Figure 14 The diagram shown is a structural schematic of the fifth damascus wiring layer after it has been formed in an embodiment of the present invention. Figure 15 The diagram shown is a schematic representation of the structure after the silicon wafer and the insulating layer are mixed and bonded in an embodiment of the present invention.
[0062] Figure 16 The diagram shown is a schematic representation of the structure of the fourth silicon substrate after thinning in an embodiment of the present invention.
[0063] Figure 17 The diagram shown is a structural schematic of the rewiring layer and metal bumps formed in an embodiment of the present invention.
[0064] Figure 18 The diagram shown is a schematic diagram of a 3DIC package structure with a heat dissipation metal structure in an embodiment of the present invention.
[0065] Explanation of reference numerals in the attached figures
[0066] 110 First Memory Wafer
[0067] 111 First silicon substrate
[0068] 112 First storage electronic component
[0069] 113 First Damascus Wiring Layer
[0070] 120 Second Memory Wafer
[0071] 121 Second silicon substrate
[0072] 122 Second storage electronic component
[0073] 123 Second Damascus wiring layer
[0074] 200 First TSV Metal Column
[0075] 300 Third Damascus wiring layer
[0076] 400 logic chips
[0077] 401 Third Silicon Substrate
[0078] 402 transistor
[0079] 403 Fourth Damascus Cabling Layer
[0080] 500 insulation layer
[0081] 600 metal parts
[0082] 130 silicon wafer
[0083] 131 Fourth silicon substrate
[0084] 132 Second TSV Metal Column
[0085] 133 trench capacitor
[0086] 134 Fifth Damascus wiring layer
[0087] 700 Rerouting Layer
[0088] 800 metal bumps
[0089] 900 heat dissipation metal structure Detailed Implementation
[0090] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0091] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0092] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0093] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0094] like Figure 1 This embodiment provides a method for fabricating a 3DIC package structure. A first and second memory wafer are electrically connected via hybrid bonding using a first and second damascene layer. A logic chip and the memory wafer are electrically connected via hybrid bonding using a third and fourth damascene layer. Backside power supply to the logic chip is achieved through metal components, a fifth damascene layer, a second TSV metal pillar, and a rewiring layer. The first TSV metal pillar, fabricated by thinning the first silicon substrate, and the second TSV metal pillar, fabricated by thinning the fourth silicon substrate, can be directly used as a TSV adapter board, and trench capacitors can be fabricated in the fourth silicon substrate. The second silicon substrate can be directly used as a support substrate; furthermore, a second silicon substrate with a heat dissipation metal structure can be provided to improve the heat dissipation performance of the 3DIC package structure. The 3DIC package structure of this invention can effectively reduce package thickness, reduce package size, effectively shorten transmission distance, and reduce power consumption. It is particularly suitable for high-density interconnects and can realize the stacking of multiple memory wafers.
[0095] The following is in conjunction with the instruction manual. Figures 1 to 18 The 3DIC packaging structure and its fabrication method described in this embodiment will be further introduced.
[0096] First, refer to Figure 1 and Figure 2In step S1, a first memory wafer 110 and a second memory wafer 120 are provided. The first memory wafer 110 includes a first silicon substrate 111, a first memory electronic component 112, and a first damask wiring layer 113, and the first damask wiring layer 113 is electrically connected to the first memory electronic component 112. The second memory wafer 120 includes a second silicon substrate 121, a second memory electronic component 122, and a second damask wiring layer 123, and the second damask wiring layer 123 is electrically connected to the second memory electronic component 122.
[0097] Specifically, to reduce linewidth / spacing, improve the reliability of the wiring layer, and manufacture a finer wiring layer, in this embodiment, the wiring layer electrically connected to the first storage electronic component 112 in the first storage wafer 110 adopts a damask wiring layer. That is, the dielectric layer in the first damask wiring layer 113 uses a low-k dielectric material, such as porous SiO2, fluorinated SiO2 (FSG), or fluorinated polyimide (F-PI), to avoid electrical signal leakage between lines and improve the reliability of the wiring layer. Furthermore, the selection of a damask wiring layer facilitates subsequent hybrid bonding processes, utilizing intermolecular forces to directly connect two structures with damask wiring layers face-to-face, thus cleverly avoiding various bonding intermediates such as ball / pillar implants, adapters, underfill, and leads, thereby improving packaging accuracy. The first storage electronic component 112 in the first storage wafer 110 may include, for example, storage transistors, storage magnetic tunnel junctions, and storage capacitors.
[0098] For a description of the second storage wafer 120, please refer to the first storage wafer 110. The second storage wafer 120 and the first storage wafer 110 may be of the same type or different types, which will not be elaborated here.
[0099] The first storage wafer 110 and the second storage wafer 120 may include, for example, HBM wafers. The specific type, size, thickness, etc. of the first storage wafer 110 and the second storage wafer 120 are not subject to excessive restrictions here.
[0100] Next, refer to Figure 1 and Figure 3 In step S2, the first memory wafer 110 and the second memory wafer 120 are hybrid bonded, and the first damask wiring layer 113 and the second damask wiring layer 123 are electrically connected.
[0101] Specifically, the specific process parameters for the hybrid bonding are not limited here. The hybrid bonding can achieve high-precision bonding between the first memory wafer 110 and the second memory wafer 120, thereby improving the bonding quality.
[0102] Next, refer to Figure 1 and Figure 4 Step S3 is executed to thin the first silicon substrate 111.
[0103] Specifically, the method for thinning the first silicon substrate 111 may include mechanical polishing or chemical mechanical polishing (CMP). In this embodiment, mechanical polishing is first used to coarsely polish the first silicon substrate 111 to expedite the thinning process and improve efficiency. Then, CMP is used for fine polishing to improve the flatness of the polished surface. However, the method for thinning the first silicon substrate 111 is not limited to this. Through this thinning operation, the thickness of the first memory wafer 110 can be reduced.
[0104] Next, refer to Figure 1 and Figure 5 Step S4 is executed to form a first TSV metal pillar 200 in the first silicon substrate 111, and the first TSV metal pillar 200 is electrically connected to the first storage wafer 110.
[0105] Specifically, the first silicon substrate 111 is first patterned to form a TSV trench (not shown) penetrating the first silicon substrate 111. Then, the first TSV metal pillars 200 filling the TSV trenches can be formed by electroplating, and the first TSV metal pillars 200 are electrically connected to the first memory wafer 110, such as the first memory electronic element 112 and / or the first damask wiring layer 113, thereby realizing the electrical connection between the first TSV metal pillars 200 and the first memory wafer 110. The first silicon substrate 111 with the first TSV metal pillars 200 can be considered as a TSV adapter board for subsequent electrical connections.
[0106] Next, refer to Figure 1 and Figure 6 Step S5 is executed to form a third damask wiring layer 300 on the first silicon substrate 111, wherein the third damask wiring layer 300 is electrically connected to the first TSV metal pillar 200.
[0107] Specifically, the third damascene wiring layer 300 is fabricated in the same way as the first damascene wiring layer 113, that is, the dielectric layer in the third damascene wiring layer 300 is a low dielectric constant material to reduce line width / spacing, achieve high-density interconnection, and facilitate subsequent high-precision hybrid bonding with the logic chip 400. The structure, material, and fabrication of the third damascene wiring layer 300 are not excessively limited here.
[0108] Next, refer to Figure 1 , Figure 7 and Figure 8 Step S6 is executed to provide a logic chip 400, which includes a third silicon substrate 401, a transistor 402 and a fourth damask wiring layer 403.
[0109] Specifically, the types of transistors 402 may include metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor field-effect transistors (CMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-type channel transistors, and / or n-type channel field-effect transistors. The structure and material of the fourth damascus wiring layer 403 are not detailed here; please refer to the first damascus wiring layer 113. The specific type of logic chip 400 is not excessively limited here; it may be a system-on-a-chip (SoC) chip, etc.
[0110] Next, refer to Figure 1 and Figure 8 In step S7, the logic chip 400 is formed on the third damask wiring layer 300 using an inverted hybrid bonding method, and the fourth damask wiring layer 403 is electrically connected to the third damask wiring layer 300.
[0111] Specifically, through the fourth damask wiring layer 403 and the third damask wiring layer 300, the logic chip 400 and the third damask wiring layer 300 can achieve high-precision hybrid bonding. The structure, material, and fabrication of the fourth damask wiring layer 403 are not excessively limited here.
[0112] Next, refer to Figure 1 and Figure 9 Step S8 is executed to thin the third silicon substrate 401.
[0113] Specifically, the method for thinning the third silicon substrate 401 may include mechanical polishing or chemical mechanical polishing (CMP). In this embodiment, mechanical polishing is first used to coarsely polish the third silicon substrate 401 to expedite the thinning process and improve efficiency. Then, CMP is used for fine polishing to improve the flatness of the polished surface. However, the method for thinning the third silicon substrate 401 is not limited to this. Through this thinning operation, the thickness of the logic chip 400 can be reduced.
[0114] The thickness of the thinned third silicon substrate 401 can be 1 to 50 μm, such as 1 μm, 10 μm, 25 μm, 50 μm, etc., in order to minimize the thickness of the packaging structure while meeting the requirements of subsequent process operations.
[0115] Next, refer to Figure 1 and Figure 10 In step S9, an insulating layer 500 is formed on the third damask wiring layer 300. The insulating layer 500 covers the third damask wiring layer 300 and encapsulates the logic chip 400.
[0116] The method for forming the insulating layer 500 may include a deposition process or a spin coating process. The insulating layer 500 may include an oxide-containing material, a nitrogen-containing material, a low dielectric constant material, a porous dielectric material, or a combination of the above materials. Specifically, the insulating layer 500 may include one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate phosphosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
[0117] See Figure 10 After the insulating layer 500 is formed, a thinning process can be performed to reduce the thickness of the package structure. The thinning method may include mechanical polishing or CMP. In this embodiment, mechanical polishing is first used to coarsely polish the insulating layer 500 to quickly carry out the thinning process and improve efficiency. Then, CMP is used to finely polish the insulating layer to improve the flatness of the polished surface. However, the thinning method of the insulating layer 500 is not limited to this.
[0118] Next, refer to Figure 1 and Figure 11 In step S10, a metal part 600 is formed in the insulating layer 500. The metal part 600 penetrates the insulating layer 500 and is electrically connected to the third damask wiring layer 300.
[0119] Specifically, the metal component 600 may include metal pillars or a metal structure composed of metal pillars and metal pads. The metal component 600 can be fabricated by first patterning the insulating layer 500 to form through-holes (not shown) penetrating the insulating layer 500, and then electroplating to fill the through-holes with the metal component 600, thereby electrically connecting the metal component 600 to the third damask wiring layer 300. This facilitates subsequent power supply to the back of the logic chip 400 via the metal component 600, effectively shortening the transmission distance and reducing power consumption. The specific types and structures of the metal component 600 are not excessively limited here.
[0120] Next, refer to Figure 1 and Figures 12-14 In step S11, a silicon wafer 130 is provided. The silicon wafer 130 includes a fourth silicon substrate 131, a second TSV metal pillar 132, a trench capacitor 133, and a fifth damask wiring layer 134. The fifth damask wiring layer 134 is electrically connected to the second TSV metal pillar 132 and the trench capacitor 133.
[0121] For details, please refer to Figure 12 The fourth silicon substrate 131 can be patterned first, and then metal can be filled to form the second TSV metal pillar 132, and then refer to Figure 13 The fourth silicon substrate 131 can be further patterned to form the trench capacitor 133, and then refer to [the relevant documentation]. Figure 14 The fifth damask wiring layer 134 can be formed on the surface of the fourth silicon substrate 131 so that the fifth damask wiring layer 134 is electrically connected to the second TSV metal pillar 132 and the trench capacitor 133, so as to facilitate subsequent electrical connection.
[0122] The specific materials, structures, and preparation methods of the second TSV metal pillar 132, the trench capacitor 133, and the fifth damask wiring layer 134 are not excessively limited here.
[0123] Next, refer to Figure 1 and Figure 15 In step S12, the silicon wafer 130 is mixed and bonded to the insulating layer 500, and the fifth damask wiring layer 134 is electrically connected to the metal part 600.
[0124] Next, refer to Figure 1 and Figure 16 Step S13 is performed to thin the fourth silicon substrate 131 to expose the metal element 600, so as to facilitate the subsequent electrical connection of the metal element 600.
[0125] The method for thinning the fourth silicon substrate 131 may include mechanical polishing or chemical mechanical polishing (CMP). In this embodiment, mechanical polishing is first used to coarsely polish the fourth silicon substrate 131 to expedite the thinning process and improve efficiency. Then, CMP is used for fine polishing to improve the flatness of the polished surface. However, the method for thinning the fourth silicon substrate 131 is not limited to these methods. This thinning operation can reduce the thickness of the silicon wafer 130.
[0126] The thickness of the thinned fourth silicon substrate 131 can be 1 to 50 μm, such as 1 μm, 10 μm, 25 μm, 50 μm, etc., in order to minimize the thickness of the packaging structure while meeting the requirements of subsequent process operations.
[0127] Next, refer to Figure 1 and Figure 17 Step S14 is executed to form a redistribution layer 700 on the fourth silicon substrate 131. The redistribution layer 700 is electrically connected to the second TSV metal pillar 132. No excessive limitations are placed here regarding the structure, material, and fabrication method of the redistribution layer 700.
[0128] Next, refer to Figure 1 and Figure 17 In step S15, metal bumps 800 are formed on the redistribution layer 700, and the metal bumps 800 are electrically connected to the redistribution layer 700. The specific type of metal bumps 800 can be selected as needed and is not limited here.
[0129] Next, refer to Figure 1 and Figure 17 Step S16 is executed to perform a cutting process to form a 3DIC package structure.
[0130] Specifically, the cutting process may include mechanical cutting and / or laser cutting to divide the wafer-level 3DIC package structure into multiple independently configured chip-level 3DIC package structures. The specific operation of the cutting process is not limited here.
[0131] In this embodiment, the total thickness of the insulating layer 500, the third damask wiring layer 300, the first storage wafer 110, the second storage wafer 120, the silicon wafer 130, and the redistribution layer 700 is less than 100 μm, such as 100 μm, 80 μm, 50 μm, 30 μm, etc., thereby enabling the fabrication of the small-size, high-density, and high-precision 3DIC packaging structure.
[0132] For further details, please refer to [link / reference]. Figure 18The second silicon substrate 121 may also have a heat dissipation metal structure 900, wherein the method for forming the heat dissipation metal structure 900 may include through-silicon via (TSV) technology. Preferably, the heat dissipation metal structure 900 is fabricated primarily within the second silicon substrate 121 of the provided second memory wafer 120 to avoid impacting the performance of the 3DIC package structure. The specific material and structure of the heat dissipation metal structure 900 are not limited here.
[0133] See Figures 2 to 18 The 3DIC packaging structure illustrated in this embodiment has two stacked memory wafers, namely the first memory wafer 110 and the second memory wafer 120. However, it is not limited to this. In another embodiment, the following steps can also be performed to prepare a stack of memory wafers with N=3 to prepare the 3DIC packaging structure, as follows:
[0134] After performing step S1 above, replace step S2 with the following steps, i.e., perform the following steps:
[0135] A third memory wafer (not shown) is provided, the third memory wafer including a fifth silicon substrate, a third memory electronic element and a sixth damask wiring layer, and the sixth damask wiring layer is electrically connected to the third memory electronic element;
[0136] The third memory wafer is bonded to the second memory wafer 120, and the sixth damask wiring layer is electrically connected to the second damask wiring layer 123.
[0137] Remove the fifth silicon substrate to expose the sixth damascus wiring layer;
[0138] The first memory wafer 110 and the fifth memory wafer are hybrid bonded together, and the first damask wiring layer 113 is electrically connected to the sixth damask wiring layer.
[0139] Of course, as needed, a fourth memory wafer, a fifth memory wafer, etc., can also be provided to prepare the 3DIC packaging structure of memory wafer stacks with N>2 layers, such as N being 3, 4, 5, 6, 8, etc.
[0140] See Figures 2 to 18 This embodiment also provides a 3DIC package structure, the 3DIC package structure comprising:
[0141] The first memory wafer 110 includes a first silicon substrate 111, a first memory electronic element 112 and a first damask wiring layer 113, and the first damask wiring layer 113 is electrically connected to the first memory electronic element 112.
[0142] The second memory wafer 120 includes a second silicon substrate 121, a second memory electronic element 122, and a second damask wiring layer 123, wherein the second damask wiring layer 123 is electrically connected to the second memory electronic element 122; wherein the first memory wafer 110 and the second memory wafer 120 are hybrid bonded, and the first damask wiring layer 113 is electrically connected to the second damask wiring layer 123;
[0143] The first TSV metal pillar 200 penetrates the first silicon substrate 111 and is electrically connected to the first memory wafer 110.
[0144] The third damask wiring layer 300 is located on the first silicon substrate 111 and is electrically connected to the first TSV metal pillar 200.
[0145] A logic chip 400 includes a third silicon substrate 401, a transistor 402, and a fourth damask wiring layer 403. The logic chip 400 is inverted and hybrid-bonded to the third damask wiring layer 300, and the fourth damask wiring layer 403 is electrically connected to the third damask wiring layer 300.
[0146] An insulating layer 500 is located on the third damask wiring layer 300, covers the third damask wiring layer 300, and encapsulates the logic chip 400.
[0147] Metal component 600, which penetrates the insulating layer 500 and is electrically connected to the third damask wiring layer 300;
[0148] A silicon wafer 130 is mixed-bonded with the insulating layer 500, including a fourth silicon substrate 131, a second TSV metal pillar 132, a trench capacitor 133, and a fifth damask wiring layer 134. The fifth damask wiring layer 134 is electrically connected to the second TSV metal pillar 132 and the trench capacitor 133, and the fifth damask wiring layer 134 is electrically connected to the metal part 600.
[0149] A redistribution layer 700 is located on the fourth silicon substrate 131 and is electrically connected to the second TSV metal pillar 132.
[0150] A metal bump 800 is located on the redistribution layer 700 and is electrically connected to the redistribution layer 700.
[0151] As an example, M layers of memory wafers are stacked between the first memory wafer 110 and the second memory wafer 120, where M ≥ 1, and M includes 1, 2, 3, 4, etc.
[0152] As an example, the insulating layer 500 includes one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate phosphosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
[0153] As an example, the thickness of the third silicon substrate 401 is 1 to 50 μm; the thickness of the fourth silicon substrate is 1 to 50 μm; and the total thickness of the insulating layer 500, the third damask wiring layer 300, the first memory wafer 110, the second memory wafer 120, the silicon wafer 130, and the redistribution layer 700 is less than 100 μm.
[0154] As an example, the second silicon substrate 121 also has a heat dissipation metal structure 900.
[0155] The 3DIC package structure can be prepared using the above-described preparation process, but is not limited to it. In this embodiment, the 3DIC package structure is prepared directly using the above-described preparation process. Therefore, the preparation, materials and specific structure of the 3DIC package structure can be found in the above-described preparation method for the 3DIC package structure.
[0156] In summary, the 3DIC packaging structure and its fabrication method of the present invention achieve electrical connection by hybrid bonding of the first and second memory wafers through a first and second damask wiring layer; achieve electrical connection between the logic chip and the memory wafer through hybrid bonding of a third and fourth damask wiring layer; provide back-side power to the logic chip through metal components, a fifth damask wiring layer, a second TSV metal pillar, and a rewiring layer; the first TSV metal pillar prepared by thinning the first silicon substrate and the second TSV metal pillar prepared by thinning the fourth silicon substrate can be directly used as a TSV adapter board, and trench capacitors can be fabricated in the fourth silicon substrate; the second silicon substrate can be directly used as a support substrate, and further, a second silicon substrate with a heat dissipation metal structure can be provided to improve the heat dissipation performance of the 3DIC packaging structure. The 3DIC packaging structure of the present invention can effectively reduce the packaging thickness, reduce the packaging structure size, effectively shorten the transmission distance, and reduce power consumption, and is particularly suitable for high-density interconnects, and can realize the stacking of multiple memory wafers.
[0157] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a 3DIC packaging structure, characterized in that, Includes the following steps: A first memory wafer and a second memory wafer are provided. The first memory wafer includes a first silicon substrate, a first memory electronic element, and a first damask wiring layer, and the first damask wiring layer is electrically connected to the first memory electronic element. The second memory wafer includes a second silicon substrate, a second memory electronic element, and a second damask wiring layer, and the second damask wiring layer is electrically connected to the second memory electronic element. The first memory wafer and the second memory wafer are hybrid bonded together, and the first damask wiring layer and the second damask wiring layer are electrically connected. Thinning of the first silicon substrate; A first TSV metal pillar is formed in the first silicon substrate, and the first TSV metal pillar is electrically connected to the first memory wafer; A third damasc network layer is formed on the first silicon substrate, and the third damasc network layer is electrically connected to the first TSV metal pillar. A logic chip is provided, the logic chip comprising a third silicon substrate, transistors, and a fourth damask wiring layer; The logic chip is formed on the third damask wiring layer using an inverted hybrid bonding method, and the fourth damask wiring layer is electrically connected to the third damask wiring layer. Thinning of the third silicon substrate; An insulating layer is formed on the third damask wiring layer, the insulating layer covering the third damask wiring layer and encapsulating the logic chip; A metal element is formed in the insulating layer, the metal element penetrating the insulating layer and electrically connected to the third damask wiring layer; A silicon wafer is provided, the silicon wafer comprising a fourth silicon substrate, a second TSV metal pillar, a trench capacitor and a fifth damascus wiring layer, wherein the fifth damascus wiring layer is electrically connected to the second TSV metal pillar and the trench capacitor. The silicon wafer is mixed and bonded to the insulating layer, and the fifth damascus wiring layer is electrically connected to the metal component; Thinning the fourth silicon substrate exposes the metal component; A redistribution layer is formed on the fourth silicon substrate, and the redistribution layer is electrically connected to the second TSV metal pillar; Metal bumps are formed on the redistribution layer, and the metal bumps are electrically connected to the redistribution layer. The cutting process is carried out to form a 3DIC package structure.
2. The method for fabricating the 3DIC packaging structure according to claim 1, characterized in that: The method also includes the following steps to fabricate the 3DIC package structure with N>2 stacked storage wafers: A third memory wafer is provided, the third memory wafer including a fifth silicon substrate, a third memory electronic element and a sixth damascus wiring layer, and the sixth damascus wiring layer is electrically connected to the third memory electronic element; The third memory wafer is bonded to the second memory wafer, and the sixth damask wiring layer is electrically connected to the second damask wiring layer. Remove the fifth silicon substrate to expose the sixth damascus wiring layer; The first memory wafer and the third memory wafer are hybrid bonded together, and the first damask wiring layer is electrically connected to the sixth damask wiring layer.
3. The method for fabricating the 3DIC packaging structure according to claim 1, characterized in that: The method for forming the insulating layer includes a deposition process or a spin coating process; the insulating layer includes one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate phosphosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
4. The method for fabricating the 3DIC packaging structure according to claim 1, characterized in that: The thickness of the thinned third silicon substrate is 1–50 μm; the thickness of the thinned fourth silicon substrate is 1–50 μm; the total thickness of the insulating layer, the third damask wiring layer, the first memory wafer, the second memory wafer, the silicon wafer, and the redistribution layer is less than 100 μm.
5. The method for fabricating the 3DIC packaging structure according to claim 1, characterized in that: The second silicon substrate also has a heat dissipation metal structure, and the method for forming the heat dissipation metal structure includes through-silicon via (TSV) technology.
6. A 3DIC package structure, characterized in that, The 3DIC packaging structure includes: The first memory wafer includes a first silicon substrate, a first memory electronic component, and a first damask wiring layer, wherein the first damask wiring layer is electrically connected to the first memory electronic component. The second memory wafer includes a second silicon substrate, a second memory electronic component, and a second damask wiring layer, wherein the second damask wiring layer is electrically connected to the second memory electronic component; wherein the first memory wafer and the second memory wafer are hybrid bonded, and the first damask wiring layer is electrically connected to the second damask wiring layer. The first TSV metal pillar penetrates the first silicon substrate and is electrically connected to the first memory wafer. The third damascus wiring layer is located on the first silicon substrate and is electrically connected to the first TSV metal pillar. A logic chip, comprising a third silicon substrate, transistors and a fourth damask wiring layer, wherein the logic chip is inverted and hybrid-bonded to the third damask wiring layer, and the fourth damask wiring layer is electrically connected to the third damask wiring layer. An insulating layer is located on the third damask wiring layer, covers the third damask wiring layer, and encapsulates the logic chip; A metal component that penetrates the insulating layer and is electrically connected to the third damask wiring layer; A silicon wafer, wherein the silicon wafer is co-bonded with the insulating layer, includes a fourth silicon substrate, a second TSV metal pillar, a trench capacitor, and a fifth damascus wiring layer, wherein the fifth damascus wiring layer is electrically connected to the second TSV metal pillar and the trench capacitor, and the fifth damascus wiring layer is electrically connected to the metal component; a redistribution layer, wherein the redistribution layer is located on the fourth silicon substrate and is electrically connected to the second TSV metal pillar; A metal bump, the metal bump being located on the redistribution layer and electrically connected to the redistribution layer.
7. The 3DIC packaging structure according to claim 6, characterized in that: M layers of memory wafers are stacked between the first memory wafer and the second memory wafer, where M ≥ 1.
8. The 3DIC packaging structure according to claim 6, characterized in that: The insulating layer includes one or a combination of a silicon oxide layer, a borosilicate glass layer, a phosphosilicate glass layer, a borosilicate phosphosilicate glass layer, a fluorosilicate glass layer, and a silicon oxynitride layer.
9. The 3DIC packaging structure according to claim 6, characterized in that: The thickness of the third silicon substrate is 1–50 μm; the thickness of the fourth silicon substrate is 1–50 μm; the total thickness of the insulating layer, the third damask wiring layer, the first memory wafer, the second memory wafer, the silicon wafer, and the redistribution layer is less than 100 μm.
10. The 3DIC packaging structure according to claim 6, characterized in that: The second silicon substrate also has a heat dissipation metal structure.