Capacitively tuned and locked optical modulators

Abstract

Aspects of the present disclosure include systems, methods, and device for optical modulation and optical data transmission. An optical modulator system may include a micro-ring for optical data transmission, a p-n phase shifter for modulating the optical data transmission, a capacitive phase shifter for tuning the optical data transmission. A wavelength locking mechanism can include a feedback loop to monitor an output wavelength of the micro-ring modulator and provide real-time adjustments to at least one of the p-n phase shifter and the capacitive phase shifter to keep the optical data transmission at a desired wavelength. A tunable modulator may comprise: a capacitive phase shifter region, the capacitor phase shifter region comprising a capacitor wherein a dielectric and a waveguide may be disposed between the first plate of the capacitor and the second plate of the capacitor, such that at least one of accumulation or depletion of charge on the capacitor effects a change in the refractive index of the waveguide.

Description

25-10978 / 103241.007514CAPACITIVELY TUNED AND LOCKED OPTICAL MODULATORSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 730,873, filed on December 11, 2024, which is incorporated by reference in its entirety for any and all purposes.TECHNICAL FIELD

[0002] The disclosed technology relates generally to micro-ring modulators for optical communication systems.GOVERNMENT RIGHTS

[0003] This invention was made with government support under HR0011-19-2- 0016 awarded by Department of Defense. The government has certain rights in the invention.BACKGROUND

[0004] Optical links play a key role in many applications ranging from data centers to Al systems. Such links typically consist of a light source chip, a transmitter chip (which may be cointegrated with the light source), and a receiver chip. Photonic and electronic devices within optical transmitter / receiver systems are either monolithically integrated or hybrid integrated. Although hybrid integration has the advantage of using a high performance dedicated photonic fabrication process and an advanced technology node for electronic integration, the packaging parasitic components can limit the system bandwidth and / or decrease the energy efficiency compared to the monolithic integration approach. Accordingly, there exists a need for high-speed performance and precise tuning capabilities.SUMMARY

[0005] Aspects of the present disclosure present a multi-layer multi-section micro-ring modulator (MRM) with improved optical and capacitive tuning responses and capabilities. Aspects of the present disclosure further enhance performance in optical- 1 -103241.00751414912-8179-6225.125-10978 / 103241.007514 communication systems by utilizing a novel structure comprising multiple sections with distinct functionalities. The multi-layer multi-section MRM, for example, addresses current technological limitations by. at least, combining capacitive and PN tuning mechanisms within a single device. Such structures enable improved optical response and finer control over modulation characteristics. Also provided is a tunable modulator, comprising: a capacitive phase shifter region, the capacitor phase shifter region comprising a capacitor, the capacitor comprising a first plate, a second plate, and a dielectric; and a first waveguide, the dielectric and the waveguide being disposed between the first plate of the capacitor and the second plate of the capacitor, the capacitor being arranged such that at least one of accumulation or depletion of charge on the capacitor effects a change in the refractive index of the waveguide.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates an example of a multi-layer multi-section MRM structure.

[0007] FIG. 2A illustrates an optical response of a multi-layer multi-section MRM in FIG. 1, FIG. 2B illustrates its capacitive tuning response, and FIG. 2C illustrates a measured eye diagram at 32Gb / s with BER<1E-12.

[0008] FIG. 3 illustrates a structure of the 3-section micro-ring modulator with capacitive, and two PN sections (most significant bit (MSB) and least significant bit (LSB)).

[0009] FIG. 4A illustrates an optical response of an example of the 3-section PN- capacitive micro-ring modulator for PAM-4 format. FIG. 4B illustrates its capacitive tuning, and FIG. 4C illustrates the measured PAM-4 eye diagram.

[0010] FIG. 5 illustrates a micro ring modulator (MRM) structure with p-n and capacitive sections.

[0011] FIG. 6 illustrates an optical response of an MRM (top left), MRM Capacitive tuning response (top right), capacitive wavelength shift vs. the applied voltage across the capacitive section (bottom left), and thermal wavelength shift vs. heater power (bottom right).

[0012] FIG. 7 illustrates an architecture (top) and micrograph of the chip with 8 cascaded MRMs (bottom).- 2 -103241.00751414912-8179-6225.125-10978 / 103241.007514

[0013] FIG. 8 illustrates a block diagram of the modulator driver (top left), the schematic of the positive and negative stages of the modulator driver (top right), block diagram of the DSAM unit (bottom left), and schematic of the voltage level shifter (bottom right).

[0014] FIG. 9 illustrates an optical response of the 8-ch TX after tuning (top left), the electro-optic response of the modulator driver (top right), MRM wavelength locking (bottom left), and energy efficiency versus data-rate per channel for error-free operation (bottom right).

[0015] FIG. 10 illustrates eye diagrams of all 8 channels working simultaneously (each at 32 Gb / s).

[0016] FIG. 11 illustrates a performance summary and comparison to other works with NRZ modulation scheme.

[0017] FIG. 12 illustrates a block diagram of the proposed monolithically integrated transmitter based on a 3-section PN-capacitive micro-ring modulator.

[0018] FIG. 13A illustrates a structure of the 3-section micro-ring modulator with capacitive, and two PN sections (MSB and LSB), and FIG. 13B illustrates a crosssection of the capacitive section.

[0019] FIG. 14A illustrates a measured optical transmission response of the micro-ring modulator in L-band with an FSR of 5.8 nm. FIG. 14B illustrates measured modulator optical response when both LSB and MSB are reverse biased at 0 V and 7 V, showing about 30 pm resonance redshift due to carrier depletion.

[0020] Figs. 15A-15C illustrate a measured optical transmission response of the micro-ring modulator at different applied bias voltages across the capacitive section, Vcap, for FIG. 15A Vcap > 0, FIG. 15B Vcap < 0, and FIG. 15C Capacitive wavelength tuning for different voltages across the capacitive section.

[0021] FIG. 16A illustrates a schematic of the wavelength locking and carrier tracking circuit. FIG. 16B illustrates a measured dynamic wavelength locking of the micro-ring modulator through capacitive tuning with zero static power consumption.

[0022] FIG. 17A illustrates a detailed schematic of the pre-amplifier and pseudodifferential micro-ring modulator driver. FIG. 17B illustrates the schematic of the driver N output stage, and FIG. 17C illustrates the schematic of the driver P output stage.- 3 -103241.007514X4912-8179-6225.125-10978 / 103241.007514

[0023] FIG. 18A illustrates the structure of the 2-section micro-ring modulator, FIG. 18B illustrates a top view of the ring modulator, and FIG. 18C illustrates a crosssection of the active region.

[0024] FIG. 19A illustrates a measured optical transmission response of the micro-ring modulator in L-band showing an FSR of about 4. 1 nm. FIG. 19B illustrates a measured modulator optical responses for reverse bias voltages of 0 V and 7 V. FIG. 19C illustrates a measured optical transmission response of the micro-ring modulator as a function of the heater power.

[0025] FIG. 20A illustrates a structure of the monolithic PAM-4 transmitter chip based on the 3-section micro-ring modulator and the chip microphotograph. FIG. 20B illustrates a measurement setup.

[0026] FIG. 21 A illustrates a the measured and simulated normalized electrooptic response of the modulator driver. FIG. 2 IB illustrates a measured PAM-4 eye diagram at 16 Gb / s.

[0027] FIG. 22A illustrates the measured eye-diagram of the PAM-4 modulator based on 2-section micro-ring modulator at 20 Gb / s and FIG. 22B illustrates the same at 22 Gb / s. FIG. 22C illustrates a measured NRZ eye-diagram at 11 Gb / s for the MSB section, and FIG. 22D illustrates the same for the Least Significant Bit section.

[0028] FIG. 23A illustrates measured BER vs. input optical power for VDD 1.8V. FIG. 23B illustrates measured BER vs. VDD for the modulator input optical power of 5 dBm.

[0029] FIG. 24 illustrates power aconsumption breakdown for PAM-4 optical transmitters.

[0030] FIG. 25 illustrates a comparison of Si-photonoic PAM-4 optical transmitters.DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0031] The present disclosure relates to optical modulators that can be tuned and wavelength locked to optical carriers at zero static power consumption. Such device is a core of high-speed optical links with important application sin Al systems and optical communication. As an example, thermal phase shifters can be used to tune and lock modulators to the carriers which are typically power hungry. Also, the thermal phase- 4 -103241.00751414912-8179-6225.125-10978 / 103241.007514 shifters also suffer from thermal crosstalk making the scalability for a dense network limited. Disclosed systems and methods can significantly reduce the power consumption, which is an important challenge in Al systems. For example, aspects can reduce the power consumption of tuning systems by over 1000 times and the size by a factor of 2 to 3. The techniques discussed herein can also reduce size, therefore also reducing fabrication costs and increasing scalability.

[0032] A key device in optical transmitters is the modulator. In this technology, a novel optical modulator is introduced, which enables a high energy efficiency as well as a large areal bandwidth density. The novel optical modulator includes a multi-layer multisection micro ring modulator (MRM) that allows for the implementation of the sequential capacitive tuning and locking of the micro ring modulators with zero static power consumption, while achieving a highly energy efficient wideband modulation using the ring p-n section.

[0033] FIG. 1 shows one embodiment of the multi-layer multi-section MRM structure, which consists of a p-n section, used for high-speed modulation, and is formed by creating a lateral p-n doping of the silicon waveguide. The capacitively tunable section, similar to a MOSFET gate structure, is formed by vertically overlapping silicon and polysilicon layers (separated by the thin gate oxide layer) without any change in the f oundry fabrication steps. To increase the efficiency of the capacitive tuning, the capacitive region can be extended to cover the ring coupling region. To optimize the coupling for modulation enhancement, besides the ring waveguide, the bus waveguide can also be formed by vertically stacking the polysilicon and silicon layers within the coupling region. Outside the coupling region where stacked polysilicon-silicon waveguides are transitioned to silicon only waveguides, the polysilicon layer can be tapered to minimize the insertion loss.

[0034] As an illustrative, non-limiting example of the present technology, a multi-layer multi-section MRM can be implemented for a p-n section with a radius of 7pm that constitutes 49% of the ring circumference, with laterally n-doping 33% of the silicon waveguide and p-doping the rest, and a capacitively section with radius of 5pm that constitutes 41% of the ring circumference. FIG. 2(a) shows the measured optical response of the example device, where an extinction ratio of more than lOdB and an FSR of 12.8nm is measured. The measured optical resonance shift for different bias voltages across the- 5 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 capacitive phase shifter, Vcap, is shown in FIG. 2(b) where the shift due to capacitive tuning is about 1 OOpm / V with a zero static power consumption. FIG. 2(c) show s the measured eye diagram of the example implemented multi-layer multi-section MRM, where a bit-error-rate (BER) of <1E-12 at 32Gb / s is achieved.

[0035] As another feature of the multi-layer multi-section MRM structure, a 3- section PN-capacitive micro-ring modulator for PAM-4 format, and its cross-section are shown in FIG. 3. The adiabatic bends are tapered from the coupling region to the straight section. The micro-ring resonator has two separate PN sections corresponding to the LSB and the MSB in the PAM-4 modulation format.

[0036] As an example of the device, a 3-section PN-capacitive micro-ring modulator for PAM-4 format can be implemented, wherein the length of LSB and MSB sections was set to about 11% and 22% of the ring circumference, respectively, the PN junctions offset from the w aveguide center was set to 150nm, and the gap between the edges of LSB and MSB doping sections was set to 2pm. FIG. 4(a) shows the measured optical response of the modulator and FIG. 4(b) shows the capacitive tuning of the ring modulator. FIG. 4(c) shows the measured PAM-4 eye diagram.

[0037] In an example, implementation may include a monolithically integrated Sub-63 fj / b 8-channel 256Gb / s optical transmitter with autonomous wavelength locking in 45nm CMOS SOI. Optical links play a key role in many applications ranging from data centers to Al systems. Such links typically consist of a light source chip, a transmitter chip (which may be co-integrated with the light source), and a receiver chip. Photonic and electronic devices within optical transmitter / receiver systems are either monolithically integrated or hybrid integrated. While hybrid integration has the advantage of using a high performance dedicated photonic fabrication process and an advanced technology node for electronic integration, the packaging parasitic components can limit the system bandwidth and / or decrease the energy efficiency compared to the monolithic integration approach.

[0038] Aspects of the present disclosure present an ultra-low pow er monolithically integrated 8-channel optical WDM transmitter that consists of an efficient on-chip modulator driver array, a compact capacitively tuned ring modulator array, and an on-chip autonomous electronic sequential wavelength locking system. The chip can be implemented using GlobalFoundries 45CLO CMOS SOI process. An error-free data-rate up to 32Gb / s per channel is achieved, aggregating to a total data-rate of 256Gb / s. The- 6 -103241.00751414912-8179-6225.125-10978 / 103241.007514 energy efficiency of the 8-channel transmitter chip, including the autonomous capacitive wavelength locking for all rings, is approximately 15fJ / b at 5Gb / s per channel and 63fJ / b at 32Gb / s per channel. The chip, including all electronic and photonic devices, achieves an areal bandwidth density of 13.25Tb / s / mm2.

[0039] A key feature of this design, in addition to monolithic integration, that enables a high energy efficiency as well as a large areal bandwidth density is the novel multi-layer multi-section micro ring modulator (MRM) design that allows for the implementation of the proposed sequential capacitive tuning and locking of the micro ring modulators with zero static power consumption, while achieving a highly energy efficient wideband modulation using the ring p-n section. FIG. 5 shows the structure of the implemented multi-layer multi-section MRM structure. The p-n section, used for highspeed modulation, has a radius of 71 Am and constitutes 49% of the ring circumference, and is formed by laterally n-doping 33% of the silicon waveguide and p-doping the rest. The capacitively tunable section has a radius of 51 Am and constitutes 41% of the ring circumference, and, in some instances similar to a MOSFET gate structure, is formed by vertically overlapping silicon and polysilicon layers (separated by the thin gate oxide layer) without any change in the foundry fabrication steps. To increase the efficiency of the capacitive tuning, the capacitive region is extended to cover the ring coupling region. To optimize the coupling for modulation enhancement, besides the ring waveguide, the bus waveguide can be formed by vertically stacking the polysilicon and silicon layers within the coupling region. Outside the coupling region where stacked polysilicon-silicon waveguides are transitioned to silicon only waveguides, the polysilicon layer is tapered to minimize the insertion loss. Each MRM structure within the system is simulated in Lumerical 3D FDTD and optimized for minimum round-trip loss for a given free spectral range (FSR) based on the wavelength spacing between optical carriers of 8 WDM channels. The optical response of an MRM is shown in FIG. 6 (top left), where an extinction ratio of more than lOdB and an FSR of 12.8nm is measured. FIG. 6 (top right and bottom left) also shows the measured optical resonance shift for different bias voltages across the capacitive phase shifter, Vcap. The shift due to capacitive tuning is about lOOpm / V with a zero static power consumption. The accurate modeling of the MRMs through previous tape-outs and characterization, results in the resonance wavelength of the MRMs to be close to the desired points such that capacitive tuning and locking can- 7 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 effectively compensate for process variations and typical carrier drifts. However, to account for large environmental variations, a secondary tuning mechanism through thermo-optic effect is implemented, that if needed, can be used for coarse tuning. The thermal tuning is performed using a doped silicon heater placed inside the ring structure (FIG. 5). The efficiency of the thermal tuning is 0. 17 nm / mW (bottom right of FIG. 6). Note that capacitive tuning with a zero static power consumption has about an order of magnitude larger tuning range compared to that of a reverse biased p-n junction. Also, note that thermal tuning provides a redshift of the MRM resonance wavelength, whereas the capacitive tuning results in a blueshift of the MRM resonance wavelength.

[0040] FIG. 7 (top) shows the block diagram of the implemented transmitter chip, where 8 MRMs with different circumferences (and hence different FSRs) are placed in series. Each MRM is tuned to one of the input optical carriers. An on-chip modulator driver is used to drive the p-n section of each MRM while its capacitive section is driven by an actuation channel of a dual sensing, actuation, and memory7(DSAM) unit. The other actuation channel of the DSAM unit is used to control the heater placed inside the ring, which is only used when the required wavelength tuning is outside the capacitive tuning range. FIG. 7 (botom) shows the micrograph of the transmiter chip. All electronic and photonic devices are monolithically integrated on the same chip.

[0041] The architecture of the modulator driver (top left of FIG. 8) is based on the pseudo-differential structure, where an input signal is divided into two different paths using passive level shifters and amplified using positive and negative stages. Both positive and negative stages are formed using cascaded inverters, but the negative stage has an additional stage of inverters for data flipping (top right of FIG. 8). The pseudo-differential output of the driver is connected to the ring p-n section. The devices within the driver are sized to minimize the chip power consumption while maintaining error-free operation at 32Gb / s. Two control voltages of VbN and VbP are used to bias the MRM for minimum power consumption at 32Gb / s.

[0042] The block diagram of the DSAM unit is shown in FIG. 8 (botom left). In a sequential tuning and control of the rings, one DSAM unit is selected at a time using the on-chip decoder and the voltage across the corresponding capacitive tuning section is set using a 5-bit up / down counter (serving as a 5-bit memory). The counter outputs are converted to an analog signal using a DAC. If needed, a 7 -bit DAC is set by a shift register- 8 -103241.00751414912-8179-6225.125-10978 / 103241.007514(as the second memory' module) and is used to control the MRM heater. As the ring is being capacitively tuned, 2% of the ring output is detected using the SiGe photodiode of the DSAM unit. The resulting photo-current is converted to a voltage and amplified using a trans-impedance amplifier (TIA). The TIA output (the feedback signal) is compared with a pre-set threshold voltage. The comparator output is connected to the up / down control of the counter and capacitively tunes and locks the ring response to the desired wavelength. FIG. 8 (bottom right) shows the schematic of the voltage level shifter used in the DAC driver for capacitive tuning.

[0043] The optical responses of the rings after tuning are shown in FIG. 9 (top left). Here, the spacing between the resonances is around 1.2nm (150GHz). The normalized electro-optic frequency response of the modulator driver is measured by sweeping the frequency of the driver input and photo-detecting the MRM output using a calibrated wideband photodiode and is in close agreement with the simulation results (top right of FIG. 9). The measured -3 dB bandwidth of the modulator driver is about 18GHz. FIG. 9 (bottom left) shows the capacitive ring wavelength locking demonstration, where a feedback signal (orange) detected by the photodiode and amplified using the TIA is compared with the threshold level (dashed black). As the feedback signal passes the preset threshold value, the control signal (blue), which is applied across the capacitive section of the ring, is adjusted such that the ring locks to the threshold value. While the memory' holds the control signal value, the system locks the next MRM, and the process is repeated sequentially. FIG. 9 (bottom right) shows the measured energy efficiency versus perchannel data-rate for error-free operation (BERM 0-12), where energy efficiencies (including the sequential capacitive tuning) of 15fJ / b at 5Gb / s and 63fJ / b at 32Gb / s are achieved. FIG. 10 shows the measured eye diagrams of all 8 channels of the transmitter operating simultaneously (each at 32Gb / s with BER<10-12).

[0044] The implemented system is compared with other works (that use NRZ modulation) in FIG. 11. The use of zero static-pow er capacitive tuning, and area and power optimized electronic and photonic designs in this work results in 2 to 3 times low er energy’ consumption and a much larger bandwidth density compared to the state-of-the-art. Additionally, the MRMs are autonomously locked to and track optical carriers. Furthermore, monolithic integration significantly reduces the packaging complexity and- 9 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 enables scalability of the implemented system to an optical transmitter with a large number of channels for beyond Tb / s optical links.

[0045] Addition aspects of the present disclosure provide Monolithic optical PAM-4 transmitter with autonomous carrier tracking. Aspects of the present technology can include two single channel optical PAM-4 transmitters, one based on a novel 3-section PN-capacitive micro-ring modulator with on-chip low-power driver and a near-zero power capacitive wavelength locking system and another one based on a 2-section thermally tuned PN micro-ring modulator of the similar size with the same modulator driver. In examples, the maximum error-free data-rate of 16 Gb / s and 22 Gb / s at the energy efficiency of 200 fj / b and 430 fj / b for the former and the latter transmitters are measured, respectively, and the design trade-offs are discussed.

[0046] High data-rate optical transceivers play a key role in many systems such as data centers, 5 G to XG networks, and short reach and long-haul communication links. Silicon photonics-based optical transceivers show considerable advancements in terms of density, energy efficiency, and bandwidth. Generally, optical transceivers are implemented either by hybrid integration of a photonic chip and an electronic chip or through monolithic integration of the photonic and electronic devices and blocks on the same chip. Hybrid integration offers the benefit of using a high performance dedicated photonic fabrication process and an advanced technology' node for electronic integration. Despite challenges in such a hybrid integration such as the packaging complexity and additional parasitic components (often limiting the bandwidth and increasing the crosstalk between parallel signal lines), recent advances in packaging together with utilizing state-of-the-art devices have led to excellent performance achievements. Monolithic integration offers a compact and highly scalable solution for electro-optical systems. While the performance of individual electronic and photonic devices in a hybrid-integrated optical transceiver may exceed that of the devices in a monolithically integrated transceiver, integration of all components on a single chip reduces the packaging complexity and related parasitic components, which can result in a higher available bandwidth and increased energy' efficiency of the optical transceiver.

[0047] An important performance metric for integrated optical transceivers is the areal bandwidth density (in Tb / s / mm2) indicating the data-rate per chip area. Given the available bandwidth and energy efficiency trade-off offered by a specific monolithic- 10 -103241.007514\4912-8179-6225.125-10978 / 103241.007514 electronic-photonic integration process, PAM-4 modulation can improve the areal bandwidth density at the cost of a higher required receiver input SNR for error-free operation. PAM-4 modulators based on segmented Mach-Zehnder structures have been implemented, however, despite excellent performance, their typically large footprint results in limited areal bandwidth density' and their large parasitic capacitance reduces the energy efficiency. On the other hand, utilizing carrier-depletion based silicon micro-ring modulators (as the core of optical transmitters) can result in improved areal bandwidth density by enabling realization of high bandwidth power efficient transmitters within a small chip footprint.

[0048] Aspects of the present disclosure explore PAM-4 modulation for example implementation of optical transmitters in the GlobalFoundries 90 nm CMOS SOI process. First, a PAM-4 transmitter implemented based on a novel 3-section PN-capacitive microring modulator with on-chip low-power driver and a near-zero power capacitive wavelength locking system is presented. As a point of comparison, a secondary PAM-4 transmitter was implemented, based on a conventional 2-section PN micro-ring modulator. The first system achieves an error-free (BER < 1 O'12) data-rate of 16 Gb / s at the energy efficiency of 200 fj / bit with near zero-power autonomous carrier tracking. The second system achieves an error-free data-rate of 22 Gb / s at the energy efficiency of 430 fl / bit. Note that for a conventional 2-section PN micro-ring modulator the PN LSB and most significant bit MSB sections are longer than those of the novel 3-section PN-capacitive micro-ring modulator, resulting in a higher SNR for modulated signal, which leads to a higher achievable error-free data rate. On the other hand, longer PN sections correspond to a larger PN junction capacitance, which increases the energy' consumption for a given data-rate. Furthermore, thermal tuning for the 2-section conventional micro-ring modulator introduces significant power consumption overhead compared to capacitive tuning in the proposed 3-section micro-ring modulator with zero static power consumption. Without being bound to any particular theory or embodiment, measurements suggest that for wavelength division multiplexing (WDM) links with a given high aggregate data-rate, utilizing the 3-section capacitively tuned micro-ring PAM-4 modulators may yield a significantly higher energy efficiency at a similar areal bandwidth density.

[0049] PAM-4 transmiter designs- 11 -103241.007514X4912-8179-6225.125-10978 / 103241.007514

[0050] PAM-4 transmitter based on 3-section PN-capacitive micro-ring modulator

[0051] FIG. 12 shows the block diagram of the proposed PAM-4 transmitter, where the light is coupled into the chip through the input grating coupler and is routed to a novel 3-section PN-capacitive micro-ring modulator. The PN MSB and LSB sections of the ring are driven using low power modulator drivers and modulated light is coupled out of the chip using the output grating coupler. The ring is electro-optically locked to the carrier using the wavelength locking and carrier tracking system with a near-zero static power consumption. The blocks of this transmitter are discussed next.

[0052] Three section PN-capacitive micro-ring modulator

[0053] The structure of the 3-section PN-capacitive micro-ring modulator and its cross-section are shown in Figs. 13(a) and 13(b), respectively, where the dimensions of the different segments and also the thickness of different layers for this technology process are shown. The thickness of the buried oxide layer is 2 pm. The adiabatic bends are tapered from 0.5 pm in the coupling region to 1 pm in the straight section. The micro-ring resonator has two separate PN sections corresponding to the LSB and the MSB in the PAM-4 modulation format. The length of LSB and MSB sections is about 11% and 22% of the ring circumference, respectively. The PN junctions are offset from the wav eguide center by 150 nm. The bends and coupling regions are not doped. The gap between the edges of LSB and MSB doping sections is 2 pm.

[0054] The measured normalized optical transmission spectrum of the micro-ring modulator in the L-band is shown in FIG. 14(a), where an FSR of about 5.8 nm, and a quality factor of about 6000 is observed. FIG. 14(b) show s the optical response of the modulator, where changing the reverse bias voltage (applied to both LSB and MSB sections) from 0 V to 7 V results in about 30 pm resonance shift. The measured capacitance of the LSB and MSB sections are about 5 fF and 10 fF, respectively. The cross-section of the capacitive section (on the left side of the ring in FIG. 13(a)) is shown in FIG. 13(b). The capacitive section is formed by overlapping silicon and poly silicon layers vertically separated by the thin gate oxide layer. At the overlapping region the polysilicon layer is intrinsically doped, and silicon layer is lightly N doped. The thin oxide layer blocks the DC current while not affecting the optical mode.- 12 -103241.007514\4912-8179-6225.125-10978 / 103241.007514

[0055] By setting a voltage difference between the two layers (through metal contacts), charge accumulation or depletion can be introduced into the overlapping region, changing the refractive index of the waveguide, which shifts the resonance frequency of the micro-ring modulator. FIG.s 15(a) and 15(b) show the capacitive tuning of the resonance wavelength of the micro-ring modulator, where both positive and negative bias voltages applied across the capacitive section result in a blueshift. For both negative and positive bias voltages, no DC current passes through the capacitive section. As a result, the micro-ring modulator resonance wavelength can be tune with zero static power consumption, w hich reduces the total transmitter power consumption and improves energy efficiency compared to the case that thermal tuning is adopted for wavelength locking and tracking. In addition, for a case that multiple thermally tuned modulators are used on the same chip, capacitive tuning eliminates thermal crosstalk between adjacent thermally tuned ring modulators.

[0056] The capacitive tuning response of the micro-ring modulator is shown in FIG. 15(c), where a 5 V positive (negative) bias voltage across the capacitive section, Vcap, blue-shifts the micro-ring modulator response by about 250 pm (150 pm). The difference in the amount of the resonance shift for positive and negative bias voltages can be attributed to the differences in the amount of charge accumulation for positive and negative bias voltages.

[0057] Capacitive wavelength locking and carrier tracking

[0058] The block diagram of the wavelength locking and carrier tracking circuit is shown in FIG. 16(a). A threshold level, corresponding to the desired offset between the input wavelength and the micro-ring modulator resonance w avelength, is serially transferred to a shift register serving as the local memory unit. A 4-bit digital-to-analog converter (DAC) is used to generate the analog threshold voltage, Vth, from the shift register output. A 5% directional couple is placed at the output of the micro-ring modulator to sample the ring response, which is then photo-detected using a SiGe photodiode with a responsivity of 0.9 AAV. A variable resistor is used to convert the photocurrent to the feedback voltage. Vfb. The threshold voltage, Vth, is then compared with Vfb using a comparator. The digital output of the comparator is used as the Up / Down input of a 5 -bit counter. At the rising edge of the off-chip clock signal, Clk, the counter counts up or down depending on the comparator output. The DAC driver boosts the digital- 13 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 output of the counter to 3 times the nominal digital supply voltage to increase the dynamic range of the capacitive tuning. A 5-bit DAC is used to convert the DAC driver output to an analog voltage. Vcap, which is used to tune the capacitive section of the micro-ring. FIG. 16(b) shows the measurement results for the implemented wavelength locking and carrier tracking system, where the black dashed line represents the threshold value preprogrammed to the chip and the orange line represents the output voltage, Vcap, applied to the capacitive section of the ring. The output voltage tunes the resonance frequency of the ring so that the feedback voltage Vfb (in blue) reaches the pre-set threshold voltage Vth, offset locking the micro-ring modulator to the input wavelength.

[0059] Modulator driver

[0060] The proposed high swing modulator driver design is based on pseudodifferential cascaded inverters. FIG. 17(a) shows the schematic of the pre-amplifier and the pseudo-differential micro-ring modulator driver. The driver consists of a positive stage, where its output is in-phase with its input, and a negative stage, where its output is out-of-phase with its input. The input data is amplified to logic levels using the preamplifier, which is formed using cascaded inverter stages. Note that if the input data is already at logic levels, a pre-amplifier is not required. The output of the pre-amplifier is split into two paths and routed to the driver. One path, carrying the signal IN_L, is directly connected to the first input of the positive stage as w ell as that of the negative stage, while the other path, carrying the signal IN_H, is high-pass filtered and DC level shifted using a series DC blocking capacitor and a shunt resistor and is routed to the second input of the positive stage as well as that of the negative stage.

[0061] As shown in FIG. 17(b), the negative stage of the driver is formed by stacking two cascode structures that can enable output voltage swing up to twice the VDD. FIG. 17(c) shows the schematic of the positive output stage, which is the same as the negative stage with added input inverter block (to invert the output waveform).

[0062] The micro-ring modulator section (LSB or MSB) is pseudo-differentially driven by the tw o outputs of the micro-ring modulator driver, Out_p and Out_n. Note that Out_n is AC coupled to the anode of the micro-ring section and a shunt resistor is used to set the DC voltage of the anode. Given that the DC voltage of the cathode is set by Out_p of the driver, the DC voltage at the anode can be used to adjust the region of operation of the micro-ring section.- 14 -103241.00751414912-8179-6225.125-10978 / 103241.007514

[0063] The low cutoff frequency of the circuit is set to 22.7 MHz to support a 27- 1 PRBS sequence beyond 3 Gb / s. The proposed driver can provide an output swing of close to 4VDD across a micro-ring section (LSB or MSB) at high frequencies without using negative supplies. This driver architecture is used to modulate PN junctions for both 3-section and 2-section micro-ring modulators.

[0064] PAM-4 transmitter based on thermally tuned 2-section micro-ring modulator

[0065] In a separate design and as a point of comparison, the 3-section ring modulator was replaced with a conventional thermally tuned 2-section micro-ring modulator.

[0066] FIG. 18(a) shows the structure of the implemented 2-section thermally tuned micro-ring modulator. The device is implemented on the same 90 nm CMOS SOI platform. The micro-ring has an add-drop port along with an input-through port, with the same gap of 200 nm between the ring and the bus waveguides. The ring radius, the length of the straight section (Ls) and coupling section (Lc) are 5 pm, 65 pm, and 2 pm, respectively. Adiabatic bends, similar to the ones used in the 3-section micro-ring, are used. FIG. 18(b) shows the top view of the 2-section micro-ring modulator with two lateral PN junctions for LSB and MSB sections. The cross-section of the PN junction (FIG. 18(c)) is the same as the one in the 3-section micro-ring modulator design, however, the LSB and MSB sections cover 26% and 52% of the micro-ring circumference, respectively. The bends and coupling regions are not doped. The gap between LSB and MSB doping sections is 2 pm.

[0067] The normalized optical transmission spectrum of the micro-ring modulator in the L-band, measured through a pair of grating couplers, is shown in FIG. 19(a), where an FSR of 4. 1 nm and a quality factor of 6000 are observed. FIG. 19(b) shows the optical response of the modulator, where changing the reverse bias voltage (applied to both LSB and MSB sections) from 0 V to 7 V results in about 60 pm resonance shift. The measured capacitances of the LSB and MSB sections are about 11 fF and 22 fF, respectively.

[0068] To thermally tune the 2-section micro-ring modulator, a lightly doped poly silicon resistor, serving as a heater, is placed near the straight section of the ring waveguide (see FIG. 18(a)), and can be used to redshift the micro-ring resonance- 15 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 frequency through thermo-optic effect. FIG. 19(c) shows the resonance frequency shifts of the 2-section micro-ring for different applied heater powers, where at a 31 mW heater power, a 600 pm resonance frequency shift is observed. No Si under-cuts or thermally isolating deep trenches were present on this CMOS SOI process.

[0069] Measurement results

[0070] PAM-4 transmitter with a 3-section micro-ring modulator

[0071] FIG. 20(a) shows the structure of the monolithic PAM-4 transmitter and the chip microphotograph. FIG. 20(b) shows the measurement set up, where the output of an Agilent 81642A tunable laser is amplified, polarization adjusted, and coupled into the chip through a grating coupler and is routed to the 3-section micro-ring PAM-4 modulator. The PRBS7 data generated using an SHF 12100A pattern generator is delivered to the chip using RF probes, routed to the modulator drivers driving the 3-section micro-ring modulator. The modulated light is coupled out of the chip through the output grating coupler. An Infmiium DCA-J 86100C sampling oscilloscope is used to monitor the output eye-diagram. A microcontroller and a real-time oscilloscope are used to program and monitor the on-chip wavelength locking and carrier tracking circuit, respectively.

[0072] FIG. 21 (a) shows the measured and simulated normalized electro-optic response of the on-chip driver after de-embedding the effect of the micro-ring modulator, where the measured -3dB bandwidth of about 8 GHz is in agreement with the simulation results. FIG. 21(b) shows the measured detected PAM-4 eye-diagram at 16 Gb / s, after the wavelength locking and tracking is engaged. For this measurement, the received power at the modulator input is about 5dBm. The energy efficiency of the transmitter (including the ring modulator driver) is about 200 fj / b at 16 Gb / s, which includes 100 pW power consumption of the w avelength locking and carrier tracking electronic circuit. The core area of the chip is 0. 12 mm2.

[0073] PAM-4 transmitter with a 2-section thermally tuned micro-ring modulator

[0074] As a point of reference, in another transmitter chip, the 3-section microring modulator in the transmitter chip can be replaced with a 2-section thermally tuned micro-ring modulator. The measured output eye-diagram of the second chip at 20 Gb / s and 22 Gb / s is shown in FIG. 22(a) and 22(b), respectively. The same measurement setup as the one in FIG. 20(b) (with a 40 Gb / s optical receiver with a gain of 900 V / W) w as- 16 -103241.007514\4912-8179-6225.125-10978 / 103241.007514 used. For both measurements, the received power at the modulator input is about 5dBm. The energy efficiency of the transmitter with the 2-section micro-ring modulator when the thermal wavelength tuning is off is about 430 EJ / b at 22 Gb / s, which changes to about 1.066 pj / b once the thermal micro-ring tuning is engaged.

[0075] Next, to further characterize the micro-ring modulator, the NRZ response can be measured by only providing the data to the LSB or MSB sections. FIG. 22(c) and 22(d) show the measured eye-diagram at 11 Gb / s for only MSB and only LSB sections, respectively. For these measurements, an RXM40AF photoreceiver with a conversion gain of 1800V / W was used and the optical power at the modulator input was set to 5 dBm. Note that the length of the MSB section is twice that of LSB section, which results in a higher output SNR for the case that MSB section is modulated (at the cost of increase power consumption). The modulation extinction ratio for the MSB and LSB sections are equal to 6 dB and 3 dB, respectively. FIG. 23(a) shows the BER measurement results for isolated MSB and LSB sections of the 2-section micro-ring modulator versus the modulator input optical power when the chip VDD is set to 1.8 V. In this case, LSB and MSB sections operate error-free (i.e.. BER < 10’12) for a modulator input optical power higher than 3 dBm and 4dBm, respectively. FIG. 23(b) shows the BER measurement results for isolated MSB and LSB sections of the 2-section micro-ring modulator versus the chip VDD when the input optical power to the modulator input is set to 5 dBm. The power consumption breakdown for the PAM-4 optical transmitters is presented in FIG. 24.

[0076] FIG. 25 compares the performance of the proposed PAM-4 transmitter against prior published silicon photonic PAM-4 optical transmitters. Comparing the measurements of the proposed transmitters based on 2-section and 3-section micro-ring modulators, the former achieves a higher error-free data-rate at the cost of higher power consumption. This is due to the longer length of the LSB and MSB sections in the former compared to the latter, resulting in a higher SNR. On the other hand, longer PN sections correspond to a larger PN junction capacitance resulting in a higher energy consumption. Additionally, thermal tuning in the former introduces significant power consumption overhead compared to capacitive tuning in the latter with zero static power consumption. To take the effect of the wavelength locking and carrier tracking into account, assuming that a 250 pm shift is required, the thermal tuning of the 2-section micro-ring modulator will consume an additional 14 mW corresponding to about 636 fj / b tuning energy. In this- 17 -103241.007514X4912-8179-6225.125-10978 / 103241.007514 case, for the same chip area, the 3-section capacitively tuned micro-ring PAM-4 modulator achieves an error-free data-rate of 16 Gb / s at energy efficiency of 200 fJ / b while the 2- section thermally tuned micro-ring PAM-4 modulator achieves an error-free data-rate of 22 Gb / s at energy efficiency of 1.066 pj / b, corresponding to a 37% higher data-rate at more than 5 times the energy consumption. To incorporate the proposed modulators into the next generation optical links, WDM technique can be used to scale the aggregate data rate of the system. Multiple capacitively tuned ring structures can be sequentially selected and locked to the input carriers at a zero static power consumption. The individual carriers can be modulated by micro-rings and multiplexed. For example, having 8 micro-ring modulators on two parallel bus waveguides, capacitively locked to the corresponding carriers, enables 16 simultaneous modulation channels, scaling linearly the aggregate data rate of such transmitter system up to 256 Gb / s (assuming 16 Gb / s per channel). Therefore, for WDM links with a high aggregate data-rate, utilizing the 3-section capacitively tuned micro-ring PAM-4 modulators can yield a higher energy efficiency at a similar areal bandwidth density.

[0077] Accordingly, monolithic integration of electronic and photonic devices in optical transceivers enables compact, energy efficient, and scalable optical transmitter systems. Aspects of the present disclosure demonstrate two monolithically integrated transmitter systems based on micro-ring PAM-4 modulators. The 3-section PN-capacitive micro-ring modulator offers wavelength locking and carrier tuning at near-zero energy consumption, whereas the 2-section thermally tuned PN micro-ring modulator requires substantially higher tuning energy. The maximum error-free data-rate of 16 Gb / s at the energy efficiency of 200 fj / bit was achieved for the 3-section PN-capacitive micro-ring modulator-based structure. For the transmitter chip designed based on the 2-section thermally tuned PN micro-ring modulator, a maximum error-free data-rate of 22 Gb / s at the energy efficiency of 1.066 pj / b is achieved.

[0078] Aspects

[0079] The following Aspects are illustrative only and do not serve to limit the scope of the present disclosure or the appended claims. Any part or parts of any one or more Aspects can be combined with any part or parts of any one or more other Aspects.

[0080] Aspect 1. An optical ring modulator system, comprising: an optical modulator comprising a micro-ring for optical data transmission; a p-n phase shifter for- 18 -103241.007514\4912-8179-6225.125-10978 / 103241.007514 modulating the optical data transmission; a capacitive phase shifter for tuning the optical data transmission; and a wavelength locking mechanism employing a feedback loop to monitor an output wavelength of the micro-ring modulator and provide real-time adjustments to at least one of the p-n phase shifter and the capacitive phase shifter to keep the optical data transmission at a desired wavelength.

[0081] Aspect 2. The system of Aspect 2, further comprising a resonator integrated with the optical modulator.

[0082] Aspect 3. The system of Aspect 1, further comprising a thermal tuner configured to adjust a temperature of the optical modulator.

[0083] Aspect 4. The system of Aspect 3, wherein the thermal tuner is a heater positioned inside the micro-ring.

[0084] Aspect 5. The system of Aspect 1, wherein the capacitive phase shifter is provided at a coupling region of the micro-ring.

[0085] Aspect 6. The system of Aspect 1 , wherein the capacitive phase shifter comprises overlapping silicon and polysilicon layers.

[0086] Aspect 7. The system of Aspect 1, wherein the capacitive phase shifter is positioned on a section of the micro-ring opposite the p-n phase shifter.

[0087] Aspect 8. The system of Aspect 1, wherein the p-n phase shifter comprises a lateral n-doped section and an adjacent p-doped section.

[0088] Aspect 9. The system of Aspect 1, wherein the p-n phase shifter comprises a capacitive section, a first p-n section, and a second p-n section.

[0089] Aspect 10. The system of Aspect 1, wherein the optical modulator comprises a multi-layer silicon waveguide.

[0090] Aspect 11. A tunable modulator, comprising: a capacitive phase shifter region, the capacitor phase shifter region comprising a capacitor, the capacitor comprising a first plate, a second plate, and a dielectric: and a first waveguide, the dielectric and the waveguide being disposed between the first plate of the capacitor and the second plate of the capacitor, the capacitor being arranged such that at least one of accumulation or depletion of charge on the capacitor effects a change in the refractive index of the waveguide.

[0091] Aspect 12. The tunable modulator of Aspect 11, wherein the first waveguide comprises silicon.- 19 -103241.007514X4912-8179-6225.125-10978 / 103241.007514

[0092] Aspect 13. The capacitively tunable modulator of Aspect 11, wherein the capacitive phase shifter region is comprised in a micro-ring resonator.

[0093] Aspect 14. The tunable modulator of Aspect 12. wherein the first waveguide is in optical communication with a second waveguide.

[0094] Aspect 15. The tunable modulator of Aspect 14, wherein the second waveguide is comprised in the micro-ring resonator.

[0095] Aspect 16. The tunable modulator of Aspect 11. wherein the capacitive phase shifter region is in optical communication with a further waveguide that carries an input light.

[0096] Aspect 17. The tunable modulator of Aspect 16, wherein the further waveguide carries an output light.

[0097] Aspect 18. The tunable modulator of Aspect 11. wherein one of the first plate and the second plate comprises n++ doped Si and the other of the first plate and the second plate comprises p++ PolySi.

[0098] Aspect 19. The tunable modulator of Aspect 11, wherein the tunable modulator is comprised in a communications device.

[0099] Aspect 20. The tunable modulator of Aspect 1 1, wherein the tunable modulator is comprised in a computing device.

[0100] References

[0101] H. Li et al., “22.6 A 25Gb / s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS,” ISSCC, pp. 410-411, Feb. 2015.

[0102] A. Pinnoradi and F. Aflatouni, “Monolithically Integrated Autonomous Demultiplexers with Near Zero Power Consumption for Beyond Tb / s Links,” Optical Fiber Communication Conference, paper M3I.2, 2023.

[0103] C. Sun et al., “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEEJSSC, vol. 51, no. 4, pp. 893-907, Apr. 2016.

[0104] P.-H. Chang et al.. “A 3D Integrated Energy -Efficient Transceiver Realized by Direct Bond Interconnect of Co-Designed 12 nm FinFET and Silicon Photonic Integrated Circuits,” J. Lightwave Technol., vol. 41, no. 21, pp. 6741-6755, Nov. 2023.- 20 -103241.00751414912-8179-6225.125-10978 / 103241.007514

[0105] S. Daudlin et al., “Ultra-dense 3D integrated 5.3 Tb / s / mm2 80 microdisk modulator transmitter,'’ Optical Fiber Communication Conference, paper M3I.1, 2023.

[0106] C. Levy et al., “A 3D-integrated 8X x 32 Gbps / X Silicon Photonic Microring-based DWDM Transmitter,” Custom Integrated Circuits Conference (CICC), paper 27-4. Apr. 2023.

[0107] S. Fathololoumi, H. Mahalingam, K. Nguyen, et al., “1.6Tbps Silicon Photonics Integrated Circuit for Co-Packaged Optical-IO Switch Applications,” in Optical Fiber Communication Conference (Optica Publishing Group, 2020), paper T3 H. 1.

[0108] M. Glick, N. C. Abrams, Q. Cheng, et al., “PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited],"’ J. Opt. Commun. Netw. 12(12), 443 (2020).

[0109] H. Li, G. Balamurugan, T. Kim, et al., "‘A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb / s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control,"’ IEEE J. Solid-State Circuits 56(1), 19-29 (2021).

[0110] H. Shu. L. Chang, Y. Tao, et al., “Microcomb-driven silicon photonic systems,” Nature 605(7910), 457-463 (2022).

[0111] S. Daudlin, S. Lee, D. Kilwani, et al., “Ultra-dense 3D integrated 5.3 Tb / s / mm2 80 micro-disk modulator transmitter,” in Optical Fiber Communication Conference (Optica Publishing Group, 2023), paper M3I.1.

[0112] J. Sharma, Z. Xuan, H. Li, et al.. “Silicon Photonic Microring-Based 4 x 112 Gb / s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS,” IEEE J. Solid-State Circuits 57(4), 1187-1198 (2022).

[0113] A. H. Atabaki, S. Moazeni, F. Pavanello, et al., “Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip,” Nature 556(7701), 349-354 (2018).

[0114] V. Stojanovic, R. J. Ram, M. Popovic, et al., “Monolithic silicon- photonic platforms in state-of-the-art CMOS SOI processes [Invited],"’ Opt. Express 26(10), 13106-13121 (2018).

[0115] A. Pirmoradi and F. Aflatouni, “Monolithically Integrated Autonomous Demultiplexers with Near Zero Power Consumption for Beyond Tb / s Links,” in Optical Fiber Communication Conference (Optica Publishing Group, 2023), paper M3I.2.- 21 -103241.007514X4912-8179-6225.125-10978 / 103241.007514

[0116] E. Sentieri, T. Copani, A. Paganini, et al., “12.2 A 4-Channel 200Gb / s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications / ’ in International Solid-State Circuits Conference (IEEE, 2020), pp. 210- 212.

[0117] C. Li, K. Yu, J. Rhim, et al., “A 3D-Integrated 56 Gb / s NRZ / PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter,” in BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (IEEE, 2018), pp. 32-35.

[0118] H. Li, Z. Xuan, A. Titriku, et al., “22.6 A 25Gb / s 4.4V-swing AC- coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65 nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1-3.

[0100] G. Li, X. Zheng, J. Yao, et al.. “25Gb / s IV-driving CMOS ring modulator with integrated thermal tuning,” Opt. Express 19(21), 20435-20443 (2011).

[0101] J. Sun, R. Kumar, M. Sakib, J. B. Driscoll, H. Jayatilleka, and H. Rong, “A 128 Gb / s PAM4 Silicon Microring Modulator With Integrated Thermo-Optic Resonance Tuning,” J. Lightwave Technol. 37(1), 1 10-115 (2019).

[0102] H. Yu, D. Ying, M. Pantouvaki, et al., “Trade-off between optical modulation amplitude and modulation bandwidth of silicon micro-ring modulators,” Opt. Express 22(12), 15178-15189 (2014).

[0103] P. Dong, R. Shafiiha. S. Liao, et al., “Wavelength-tunable silicon microring modulator,” Opt. Express 18(11), 10941-10946 (2010).

[0104] K. Giewont, R. Shafiiha, S. Liao, et al., “300-mm Monolithic Silicon Photonics Foundry Technology,” IEEE J. Sei. Top. Quantum Electron. 25(5), 1-11 (2019).

[0105] M. Rakowski, C. Meagher, K. Nummy, et al., “45 nm CMOS - Silicon Photonics Monolithic Technology' (45CLO) for next-generation, low power and high speed optical interconnects,” in Optical Fiber Communication Conference (Optica Publishing Group, 2020), paper T3 H.3.

[0106] H. Sepehrian, A. Yekani, L. A. Rusch, and W. Shi, “CMOS -Photonics Codesign of an Integrated DAC-Less PAM-4 Silicon Photonic Transmitter,” IEEE Trans. Circuits Syst. I 63(12), 2158-2168 (2016).- 22 -103241.007514\4912-8179-6225.125-10978 / 103241.007514

[0107] A. Roshan-Zamir, B. Wang, S. Telaprolu, et al., “A two-segment optical DAC 40 Gb / s PAM4 silicon microring resonator modulator transmitter in 65 nm CMOS,'’ in Optical Interconnects Conference (IEEE, 2017). pp. 5-6.

[0108] S. Moazeni, S. Lin, M. Wade, et al., “A 40-Gb / s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS,” IEEE J. Solid-State Circuits 52(12), 3503-3516 (2017).- 23 -103241.007514X4912-8179-6225.1

Claims

25-10978 / 103241.007514What is Claimed:

1. An optical ring modulator system, comprising: an micro-ring modulator for optical data transmission; a p-n phase shifter for modulating the optical data transmission: a capacitive phase shifter for tuning the optical data transmission; and optionally a wavelength locking mechanism employing a feedback loop to monitor an output wavelength of the micro-ring modulator and provide real-time adjustments to at least one of the p-n phase shifter and the capacitive phase shifter to maintain the optical data transmission at a desired wavelength.

2. The system of claim 1, further comprising a resonator integrated with the optical modulator.

3. The system of claim 1. further comprising a thermal tuner configured to adjust a temperature of the optical modulator.

4. The system of claim 3, wherein the thermal tuner is a heater positioned inside the micro-ring modulator.

5. The system of claim 1, wherein the capacitive phase shifter is provided at a coupling region of the micro-ring modulator.

6. The system of claim 1, wherein the capacitive phase shifter comprises superposed silicon and polysilicon layers.

7. The system of claim 1. wherein the capacitive phase shifter is positioned on a section of the micro-ring modulator opposite the p-n phase shifter.

8. The system of claim 1, wherein the p-n phase shifter comprises a lateral n-doped section and an adjacent p-doped section.

9. The system of claim 1, wherein the p-n phase shifter comprises a capacitive section, a first p-n section, and a second p-n section.- 24 -103241.007514\4912-8179-6225.125-10978 / 103241.00751410. The system of claim 1 , wherein the optical modulator comprises a multi-layer silicon waveguide.

11. A tunable modulator, comprising: a capacitive phase shifter region, the capacitor phase shifter region comprising a capacitor, the capacitor comprising a first plate, a second plate, and a dielectric; and a first waveguide, the dielectric and the waveguide being disposed between the first plate of the capacitor and the second plate of the capacitor. the capacitor being arranged such that at least one of accumulation or depletion of charge on the capacitor effects a change in the refractive index of the waveguide.

12. The tunable modulator of claim 11, wherein the first waveguide comprises silicon.

13. The capacitively tunable modulator of claim 11, wherein the capacitive phase shifter region is comprised in a micro-ring resonator.

14. The tunable modulator of claim 12, wherein the first waveguide is in optical communication with a second waveguide.

15. The tunable modulator of claim 14, wherein the second waveguide is comprised in the micro-ring resonator.

16. The tunable modulator of claim 1 1, wherein the capacitive phase shifter region is in optical communication with a further w aveguide that carries an input light.

17. The tunable modulator of claim 16, w herein the further waveguide carries an output light.- 25 -103241.007514X4912-8179-6225.125-10978 / 103241.00751418. The tunable modulator of claim 11, wherein one of the first plate and the second plate comprises n++ doped Si and the other of the first plate and the second plate comprises p++ PolySi.

19. The tunable modulator of claim 11, wherein the tunable modulator is comprised in a communications device.

20. The tunable modulator of claim 11, wherein the tunable modulator is comprised in a computing device.- 26 -103241.007514\4912-8179-6225.1

Images