Techniques for performing custom operations on data in memory

Abstract

An apparatus is provided comprising: a decoder circuit for decoding instructions of a first instruction set, wherein the decoder circuit generates control signals in response to the instructions of the first instruction set; and a processing circuit that, in response to the control signals, causes to execute operations defined by the instructions. The decoder circuit is arranged to issue control signals to the processing circuit in response to program-specified instructions of a specified memory location operand and a program operand of the first instruction set, thereby triggering a second instruction set processing unit to execute a program identified by the program operand, for performing a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand. The program includes one or more instructions of the second instruction set defining operations supported by the second instruction set processing unit.

Description

Background Technology

[0001] This technology relates to the field of data processing.

[0002] Within a data processing system, processing circuitry can be provided to execute operations defined by instructions from a given instruction set. Typically, the processing circuitry accesses a set of registers where the source data used during the operation and the resulting data generated as a result of the operation are temporarily stored. Load instructions can be executed to load data from memory into registers, store instructions can be used to store data from registers back to memory, and data processing instructions provided by the given instruction set (such as those used to define arithmetic or logical operations) can then specify one or more registers containing the source data to be operated on, and / or the registers where the generated result data is stored.

[0003] In some cases, it may be desirable to perform operations on data stored in memory without first loading the data from memory into that set of registers. Specialized instructions can be defined for this purpose, each defining a specific operation to be performed on the data in memory. However, there are usually significant constraints on the code space within any given instruction set, thus limiting the number of different instructions that can be defined. This typically means that only a relatively small number of specialized instructions can be defined to perform operations on data in memory. It is desirable to alleviate this constraint in order to allow for a wider range of operations to be performed on data stored in memory. Summary of the Invention

[0004] According to a first example arrangement, an apparatus is provided, comprising: a decoder circuit for decoding instructions of a first instruction set, wherein the decoder circuit generates a control signal in response to the instructions of the first instruction set; and a processing circuit that, in response to the control signal, causes to execute an operation defined by the instructions; wherein: the decoder circuit is arranged to issue a control signal to the processing circuit in response to a program-specified instruction of a specified memory location operand and a program operand of the first instruction set, to trigger a second instruction set processing unit to execute a program identified by the program operand, for performing a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand, the program including one or more instructions of a second instruction set defining operations supported by the second instruction set processing unit.

[0005] According to another example arrangement, a method of operating an apparatus is provided, the method comprising: employing a decoder circuit to decode instructions of a first instruction set, wherein the decoder circuit generates a control signal in response to the instructions of the first instruction set; employing a processing circuit to cause an operation defined by the instructions to be executed in response to the control signal; and arranging the decoder circuit to issue a control signal to the processing circuit in response to program-specified instructions of a specified memory location operand and a program operand of the first instruction set, thereby triggering a second instruction set processing unit to execute a program identified by the program operand to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand; wherein the program includes one or more instructions of a second instruction set defining operations supported by the second instruction set processing unit.

[0006] According to another example arrangement, a computer program including instructions, when executed by a host data processing device, controls the host data processing device to provide an instruction execution environment for executing target program code. The computer program includes: instruction decoding program logic for decoding instructions of a first instruction set, wherein the instruction decoding program logic generates control signals in response to instructions of the first instruction set; and data processing program logic that, in response to the control signals, causes the execution of operations defined by the instructions. The instruction decoding program logic is arranged to issue control signals to the data processing program logic in response to program-specified instructions of a specified memory location operand and a program operand of the first instruction set, thereby triggering a second instruction set processing program logic to execute a program identified by the program operand to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand. The program includes one or more instructions of a second instruction set defining operations supported by the second instruction set processing program logic. Such a computer program can be stored on any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductor, magnetic disk, or optical disk.

[0007] In yet another example arrangement, a computer-readable medium is provided for storing computer-readable code for manufacturing an apparatus according to the first example arrangement described above. This computer-readable storage medium may be a transient computer-readable medium or a non-transitory computer-readable medium. Attached Figure Description

[0008] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1It is a block diagram that schematically illustrates a data processing system implemented according to an example;

[0010] Figure 2 The illustration illustrates a field provided within a user-defined atomic instruction, specifically implemented according to an example.

[0011] Figure 3 This is a block diagram illustrating more details of the atomic processing unit provided according to an example implementation;

[0012] Figure 4 This is a flowchart illustrating the steps performed when decoding a user-defined atomic instruction, based on a specific example implementation.

[0013] Figure 5 A more detailed illustration of a specific implementation based on an example is provided. Figure 3 The operation of the instruction buffer of the atomic processing unit;

[0014] Figure 6 The example illustrates how instructions loaded into the instruction buffer can be decoded, based on a specific implementation of an example.

[0015] Figure 7 This is a block diagram schematically illustrating a data processing system specifically implemented according to another example; and

[0016] Figure 8 The specific implementation of the simulator is illustrated. Detailed Implementation

[0017] According to the technology described herein, an apparatus is provided having a decoder circuit for decoding instructions of a first instruction set, and specifically for generating control signals in response to decoding each instruction of the first instruction set, wherein those control signals are passed to other elements within the apparatus to trigger operations required to execute the decoded instructions. Furthermore, the apparatus has processing circuitry that, in response to the control signals, causes the execution of operations defined by those instructions. In this manner, a sequence of instructions of the first instruction set can be decoded by the decoder circuitry, and then the processing circuitry executes the operations required by the sequence of instructions.

[0018] Furthermore, according to the technology described herein, program-specified instructions are defined within a first instruction set. These program-specified instructions specify memory location operands and program operands, and decoding circuitry is arranged to issue control signals to processing circuitry in response to decoding such instructions. These control signals trigger a second instruction set processing unit to execute a program identified by the program operands. Specifically, the second instruction set processing unit then performs a program-defined sequence of operations on data accessed at a location in memory identified by the memory location operands. This program includes one or more instructions from the second instruction set defining the operations supported by the second instruction set processing unit.

[0019] In this way, a single instruction from the first instruction set can be used to perform a wide variety of custom operations on data stored in memory. Specifically, a program can be written using instructions from the second instruction set, wherein the program is identified by one of the operands of the program-specified instructions. The task of executing this program can then be offloaded to a second instruction set processing unit, which can then execute each instruction defined within the program to perform a series of operations on the data accessed in memory.

[0020] While the second instruction set can take various forms, in one example implementation, it will take the form of a dedicated instruction set containing a finite number of instructions that define the core set of operations that can be executed by the second instruction set processing unit. It is desirable to keep programs written using the instructions of the second instruction set relatively small and simple, so that they will execute in a predictable manner over a finite time period. By keeping the number of instructions provided by the second instruction set limited, instructions can be uniquely defined with a relatively small amount of code, thus allowing the entire program consisting of multiple instructions from the second instruction set to be defined by a relatively small number of bits. It has been found that, using this approach, a wide variety of useful sequences of operations can be defined by such programs, the execution of which is triggered by a single program-specified instruction from the first instruction set, thereby avoiding the need to individually encode multiple different instructions from the first instruction set to seek to define all operations expected to be performed on data stored in memory.

[0021] There are various scenarios where it can be useful to perform operations on data stored in memory rather than first loading that data into registers accessible to the processing circuitry. For example, the techniques described herein can be used to implement various offloading mechanisms where it is desirable to use a second instruction set processing unit to perform some in-memory computations. In a particular example implementation, the use of program-specified instructions can be used to execute sequences of operations atomically, which can be very useful, for example, in situations where multiple components in a data processing system share access to data. Sequences of operations executed atomically can be collectively referred to as atomic operations, and when an atomic operation is performed by a specific process within the system, no other process within the system can read or change the state read or changed during the atomic operation. Therefore, atomic operations are efficiently performed as a single step and are a type of operation that is very useful in various situations in data processing systems. Atomic operations typically implement read, modify, and write sequences, where one or more data items are read from memory, modified, and then written back to the same memory location.

[0022] Therefore, in one example implementation, the program-specified instructions are atomic instructions, specifically atomic instructions specifying program operands that will be executed to atomically perform the corresponding sequence of operations. In this implementation, the second instruction set processing unit can be considered an atomic processing unit, which is arranged to execute instructions of the second instruction set to atomically perform the sequence of operations. According to this implementation, the hardware within the system can be used to ensure atomic execution of the sequence of operations. For example, the atomic processing unit can be coupled to a specific level of cache, and a cache coherence protocol employed within the system can be used to ensure that the cache has ownership of the value data of one or more cache lines to be processed during the execution of the program by the atomic processing unit, thereby ensuring that no other entity within the system will read or modify the data while it is being processed by the atomic processing unit during program execution.

[0023] There are various ways to identify the program to be executed using program operands with program-specified instructions. For example, a program operand can identify the location in memory where the program is contained, and thus specify the program by referring to that location in memory. However, in one example embodiment, the device has a set of registers accessible to the processing circuitry, and the program-specified instructions are configured to specify the program operand by identifying at least one register from that set of registers containing the program to be executed by the second instruction set processing unit. Thus, in this embodiment, the program operand directly specifies the program, since the program is contained within one or more registers forming the program operand. This provides a particularly simple and efficient mechanism. In particular, by arranging the second instruction set to include only a relatively small set of instructions (specifically tailored to the types of operations the second instruction set processing unit might expect to execute), programs containing multiple of these instructions can be constructed, where the total program size is small enough to fit within one or a few registers. In a particular example embodiment, a 64-bit register can be provided within that set of registers, and the entire program can be contained within a single 64-bit register, or within a pair of such 64-bit registers. Therefore, when the processing circuit triggers the second instruction set processing unit to execute a program, it can read the program from one or more relevant registers and pass the program as input to the second instruction set processing unit.

[0024] This approach offers a high degree of customizability in defining the sequence of operations to be executed by the second instruction set processing unit. Specifically, the user / programmer can create a suitable program using a limited set of instructions from the second instruction set, and this program can be loaded into registers (or a pair of registers, if needed) of the register set before executing the program-specified instructions, which identify one or more registers containing the program.

[0025] In one example implementation, in addition to the previously mentioned memory location operands and program operands, the program specifying instruction may also specify at least one input value operand that identifies at least one input value to be used by the second instruction set processing unit when executing a program-defined sequence of operations. Therefore, when the processing circuitry triggers the second instruction set processing unit to execute a program, in addition to identifying the program to be executed, it may also input the one or more input values ​​specified by the input value operands to the second instruction set processing unit. Each input value operand can identify the associated input value in various ways. For example, the program specifying instruction may identify one or more input values ​​as immediate values ​​directly encoded within the instruction, or alternatively, it may identify one or more registers containing those input values. When a reference register specifies an input value, the processing circuitry may be arranged, in almost the same manner as previously discussed with respect to program operands, to access one or more associated registers to obtain the one or more input values ​​when the second instruction set processing unit is triggered to execute a program, and then provide those input values ​​to the second instruction set processing unit.

[0026] As previously mentioned, in one example implementation, the goal of the second instruction set is to provide a relatively limited set of instructions that defines the range of available operations that can be used to construct a variety of different programs executable by the second instruction set processing unit. By providing only a relatively limited set of instructions, very efficient encoding of instructions can be achieved, thus enabling the construction of the entire program using a relatively small number of bits, thereby making it possible, for example, to store the entire program in one or a pair of registers. According to this implementation, each instruction in the second instruction set can be arranged to be encoded using fewer bits than each instruction in the first instruction set.

[0027] In one example implementation, the second instruction set is a variable-length instruction set, such that the number of bits used to encode any given instruction in the second instruction set depends on the type of that given instruction. Therefore, in one example implementation, the opcode portion of an instruction in the second instruction set can be analyzed to identify the type of instruction, and once determined, the total number of bits defining the instruction is known and can be analyzed accordingly. Such methods provide particularly efficient encoding by enabling the avoidance of any redundant coding space and thus allowing the entire program to be defined in an efficient manner (e.g., allowing the entire program to be stored in a single register in some instances and in only a pair of registers in others).

[0028] The second instruction set processing unit can be located in various positions within the device. For example, the device can be arranged to be coupled to a memory system providing multi-level caches, and the second instruction set processing unit can be provided in association with one of these cache levels. In a particular example embodiment, the second instruction set processing unit is provided by processing circuitry and is arranged to perform a sequence of operations on data stored in a cache level accessible to the processing circuitry. This embodiment can be referred to as a "near" embodiment because the data is stored in a cache level relatively tightly coupled to the processing circuitry.

[0029] However, the techniques described herein are not limited to use in conjunction with this near-specific embodiment. For example, in an alternative exemplary embodiment, the processing circuitry may be arranged to be coupled to the second instruction set processing unit via interconnects, and the second instruction set processing unit may be triggered to execute a program by asserting a request on the interconnects to cause the second instruction set processing unit to perform a sequence of operations on data stored in a cache hierarchy associated with the second instruction set processing unit. In this case, the second instruction set processing unit may be located further away in the system in association with a cache hierarchy more distant from the processing circuitry (e.g., a cache hierarchy shared among multiple instances of the processing circuitry within the system). Such an embodiment may be referred to as a “far” embodiment.

[0030] Furthermore, in some example implementations, multiple instances of the second instruction set processing unit may be provided. For example, one instance may be tightly coupled to an associated instance of the processing circuitry, while another instance may be further away in the system. In such implementations, dynamic switching between the near and far implementations can be made, taking into account various factors. For instance, when deciding whether to use the near or far implementation to execute a program, the contention for data access among multiple instances of the processing circuitry system can be considered.

[0031] When multiple instances of a processing circuit periodically seek to access the same data, storing that data in a cache hierarchy shared by those instances may be more efficient. This is because it reduces the level of prying required to implement cache coherency protocols and decreases the amount of data moving between caches compared to storing data in caches more tightly coupled to instances of the processing circuit. Therefore, using a far-specific implementation may provide a higher rate of aggregated updates, resulting in better scalability, where reasonable contention is likely.

[0032] The second instruction set processing unit can be configured in various ways. However, in one example embodiment, the second instruction set processing unit includes: an instruction buffer storage device for receiving a program identified by program operands; additional decoding circuitry for analyzing the contents of the instruction buffer storage device to decode each instruction of the second instruction set provided by the program; and execution circuitry for executing the operation required for each instruction in response to control signals generated by the additional decoding circuitry. Thus, the additional decoding circuitry can be arranged to analyze a series of bits forming the program received in the instruction buffer storage device to decode each instruction of the program and send appropriate control signals to the execution circuitry to execute the required operation.

[0033] In one example embodiment, additional decoding circuitry is arranged to determine the instruction type from the opcode bits for each instruction in the second instruction set provided by the program, and to determine the total number of bits defining the instruction based on the determined instruction type. As previously mentioned, in one example embodiment, the second instruction set may be a variable-length instruction set, and therefore it is necessary to evaluate the opcode to determine the instruction type before the total number of bits used to define the instruction can be determined. In a particular example embodiment, additional decoding circuitry may be arranged to analyze the contents of the instruction buffer memory starting from the first end of the instruction buffer memory to sequentially decode each instruction of the program until it has been determined that all instructions forming the program have been decoded and executed.

[0034] The instructions provided within the second instruction set can take various forms. In one example implementation, the second instruction set includes instructions for identifying when the end of the program has been reached, and the end instruction is encoded as a sequence of bits all having the same predetermined bit values ​​(i.e., all 0s or all 1s). This significantly improves efficiency because it allows for early program termination without the program occupying the entire bit storage space within the instruction buffer memory. In particular, once the end instruction is detected, it is not necessary to evaluate the position of any remaining bits in the instruction buffer memory.

[0035] In a specific example implementation, as each instruction is decoded by additional decoding circuitry, the second instruction set processing circuitry is arranged to extend a sequence of bits forming the program by appending multiple bits with predetermined values. This approach further improves efficiency when analyzing the program within the second instruction set processing unit because it allows implicit end-of-program instructions to be incorporated into this sequence of bits. Specifically, when an instruction is decoded and the bit sequence is extended by appending multiple bits with predetermined values, a point is reached where, due to the fact that the end-of-program instruction is encoded as a complete bit sequence with those predetermined values, the additional decoding circuitry recognizes the currently analyzed bit sequence as forming the previously mentioned end-of-program instruction. This approach can be useful, for example, if there is no space in the registers used to contain the program to include an explicit end-of-program instruction. For example, if it is desired to constrain the program to fit within a single 64-bit register, it can be useful if it is not necessary to explicitly use any of these bits to identify the end-of-program instruction, and the above approach makes this possible because extending the bit sequence using the above method results in the efficient addition of the end-of-program instruction when the instruction is decoded.

[0036] The actual number of bits appended when decoding each instruction can vary depending on the specific implementation. However, in one example implementation, the number of bits appended when decoding a given instruction is equal to the total number of bits that form that given instruction.

[0037] In one example implementation, the second instruction set includes a skip instruction that causes one or more subsequent instructions in the program to be skipped when a condition defined by the skip instruction is met. This provides increased flexibility in defining the program to be executed by allowing some operations defined within the program to be executed only under certain conditions. Furthermore, by using a skip instruction that only allows forward movement through the program, rather than a more general branch instruction that can allow backward branching, the possibility of the program taking an indeterminate amount of time to complete is avoided, and effectively the possibility of the program entering an infinite loop that will never complete is avoided.

[0038] Various methods exist for maintaining sufficient state information to enable an assessment of whether the conditions defined by the skip instruction are met. In one example implementation, at least one instruction in the second instruction set is arranged, upon execution, to set one or more condition code flags depending on the result generated by the execution of that instruction. Therefore, when instructions within the program are executed, one or more of them can update the condition code flags, and the execution circuitry can then be arranged to refer to the state of the one or more condition code flags when subsequently encountering an instance of the skip instruction to determine whether the conditions defined by the skip instruction are met.

[0039] There are various ways to define the condition using a skip instruction, but in one example implementation, the condition is defined by a condition field within the encoding of the skip instruction. In implementations where the second instruction set also includes the previously mentioned end instruction, in one example implementation, the end instruction can be encoded using the same opcode bits used to identify the skip instruction, but the condition field is set to a reserved value not used to define the condition. This avoids the need for a separate explicit encoding of the end instruction, because if the decoding of the opcode bits identifies the skip instruction, but the condition field is set to a reserved value, the instruction will alternatively be treated as a end instruction by a separate decoding circuit. Additionally, in some implementations, the method supports the use of an implicit end instruction as described above when both the opcode bits used for the skip instruction and the reserved value of the condition field have the same pre-defined bit values ​​(e.g., all zeros (or actually all one in other implementations)).

[0040] In one example implementation, the second instruction set processing unit includes multiple internal registers. In one example implementation, these internal registers are different from the previously mentioned set of registers accessible to the processing circuitry, and alternatively, are registers used only by the second instruction set processing unit. However, in other implementations, the processing circuitry and the second instruction set processing unit may share access to the same set of physical registers. For example, register renaming techniques can be used to map logical registers to physical registers, and this approach can also be used to map internal register specifiers of instructions in the second instruction set to physical registers within a set of registers accessible to the processing circuitry, whereby the second instruction set processing unit then accesses those registers.

[0041] When triggered to execute a program-defined sequence of operations, the second instruction set processing unit (ISP) can be arranged to store source data obtained from a memory location identified by the memory location operand in a given internal register. The entity responsible for obtaining the source data from the memory location can take various forms. For example, where the memory location operand identifies a register (or, in some implementations, a stack pointer) in the set of registers accessible to the processing circuitry as containing the address information needed to identify the memory location, according to one example method, the processing circuitry can obtain the address information from the register (or stack pointer) and pass it to the second ISP, which then reads the source data from that memory location and stores the read source data in the given internal register. However, in a particular example implementation, the processing circuitry obtains the address information from the relevant register or stack pointer, then reads the source data itself from the desired memory location, and this source data is then passed as input to the second ISP, such that the second ISP then only needs to store the provided source data in the given internal register.

[0042] A given internal register used to store source data obtained from an identified location in memory can take various forms. For example, the internal register used can be hardwired and / or predefined, such that the same specific internal register is used to store the information each time the program is executed by the second instruction set processing unit.

[0043] As described above, after the source data is stored in a given internal register, upon completion of the operation sequence, the second instruction set processing unit can be arranged to write the result data to a location in memory identified by the memory location operand, at least if the result data differs from the source data. Therefore, the operation sequence defines a read, modify, and write operation sequence in which data is read from memory, one or more calculations are performed on that data, and then the result data is written back to the same memory location. In one example implementation, the result data is written back to the memory location regardless of whether it differs from the original source data. However, if necessary, a check can be performed by the second instruction set processing unit to determine whether the result data differs from the source data, wherein the result data is written back to the memory location only if the result data does indeed differ from the source data.

[0044] In one example implementation, an internal register different from the previously mentioned given internal register can be used to store result data generated during the execution of the program's instructions. However, in a particular example implementation, during the execution of the sequence of operations, the second instruction set processing unit is arranged such that the result data is maintained in the given internal register, thus overwriting the initial source data, at least if the result data differs from the initial source data. This can be achieved using "destructive" instructions whose results overwrite the contents of the source operand, which may be advantageous in the present case because less instruction coding space is needed to define a given instruction due to the fact that an operand information identifies both the location of the source information and the location to be used to store the result information.

[0045] As previously mentioned, in one example implementation, a program-specified instruction may specify at least one input value operand that identifies at least one input value to be used by the second instruction set processing unit when executing a program-defined sequence of operations. In this implementation, the processing circuitry may then be arranged to provide at least one input value to the second instruction set processing unit for use in at least one of a plurality of internal registers, in addition to the previously mentioned given internal registers. The second instruction set processing unit can then perform operations on such input values ​​by accessing them in its own internal registers.

[0046] There are various ways in which the at least one input value operand can identify the at least one input value. In one example implementation, a program-specified instruction is configured to specify the at least one input value operand by identifying at least one register accessible to the processing circuitry containing the at least one input value. The processing circuitry can then be arranged to read the at least one input value from the at least one register to provide it to a second instruction set processing unit. The second instruction set processing unit can then be arranged to maintain at least one output value during the execution of the operation sequence and, upon completion of the operation sequence, to provide the at least one output value to the processing circuitry for storage in the at least one register containing the at least one input value. Thus, once the operation sequence has been executed, one or more registers accessible to the processing circuitry can be updated with one or more relevant output values, and this information can then be referenced by the processing circuitry, for example, to determine the result of the program executed in response to the program-specified instruction.

[0047] In one example implementation, during the execution of the operation sequence, the second instruction set processing unit can be arranged such that the at least one output value is maintained in at least one of the multiple internal registers used to store the least one input value. Similar to the previously discussed arrangement where the result data is arranged to overwrite the source data in a given internal register, the above arrangement of maintaining the output value using the same internal register used to store the original corresponding input value can be achieved using "destructive" instructions, which allows for more efficient coding due to the reduced number of operands that need to be defined.

[0048] A specific example implementation will now be described with reference to the accompanying drawings.

[0049] Figure 1An example of a data processing apparatus 5 is illustrated schematically. It should be understood that this is only a high-level representation of a subset of the components of the apparatus, and the apparatus may include many other components not illustrated. Apparatus 5 includes processing circuitry 15 for performing data processing in response to instructions decoded by an instruction decoder (also referred to herein as decoder circuitry) 10. The instruction decoder 10 decodes instructions fetched from instruction cache 50 to generate control signals 12 for controlling the processing circuitry 15 to perform the corresponding operation represented by the instruction. The processing circuitry 15 may include one or more execution units for performing operations on values ​​stored in register 20 to generate a result value to be written back to the register. For example, the execution unit may include an arithmetic / logic unit (ALU) 25 for performing arithmetic or logical operations, a floating-point (FP) unit 34 for performing operations using floating-point operands, and other units, such as a vector processing unit (not shown), for performing vector operations on operands comprising multiple independent data elements. The processing circuitry may also include a load / store unit (also referred to herein as a memory access unit) 35 for controlling data transfer between register 20 and the memory system. In this example, the memory system includes an instruction cache 50, a Level 1 data cache 45, a Level 2 cache 55 shared between data and instructions, and main memory 60. It should be understood that other cache hierarchy structures are possible; this is merely an example.

[0050] It should be understood that other elements (not shown) may be provided in association with load / store unit 35 for controlling access to memory. For example, a memory management unit (MMU) may be provided to provide address translation functionality to support memory access triggered by load / store unit 35. The MMU may have a translation lookup buffer (TLB) for caching a subset of entries from page tables stored in memory systems 45, 55, and 60. Each page table entry may provide an address translation mapping for the corresponding address page and may also specify access control parameters, such as specifying whether the page is a read-only region or has read-and-write access permission, or specifying which privilege levels have access permission to access the page.

[0051] The instructions decoded by decoder circuit 10 are from a first instruction set, and according to the techniques described herein, the first instruction set may include program-specified instructions. Program-specified instructions specify memory location operands and program operands, and in response to decoding such instructions, decoder circuit 10 sends a control signal to processing circuit 15 to trigger a second instruction set processing unit to execute a program identified by the program operands. Therefore, the second instruction set processing unit then performs a program-defined sequence of operations on data accessed at a location in memory identified by the memory location operands. This program includes one or more instructions from a second instruction set defining the operations supported by the second instruction set processing unit.

[0052] In this way, a single instruction from the first instruction set can be used to perform a wide variety of custom operations on data stored in memory. Specifically, a program can be written using instructions from the second instruction set, wherein the program is identified by one of the operands of the program-specified instruction. In one example implementation, the program will be constrained to be relatively small, and specifically constrained to fit into one or a pair of registers in register 20, so that the program can be read from one or more associated registers and passed as input to the second instruction set processing unit. The task of executing the program can then be offloaded to the second instruction set processing unit, which can then execute each instruction defined within the program to perform a series of operations on the data accessed in memory.

[0053] Another advantage of specifying the required series of operations via program operands of instruction-specific instructions from the first instruction set is that hardware state does not need to be modified (saved and restored) during processes such as context switching. The proposed method is also virtualization-friendly. All architectural state resides in memory or in registers referenced by instructions from the first instruction set, and therefore will be handled by the operating system and hypervisor software.

[0054] The above mechanism can be used to perform various operations on data stored in memory, instead of first loading the data into register 20 accessible by processing circuitry 15. In a particular example implementation, as will be discussed herein with reference to the rest of the figures, the use of program-specified instructions can be used to perform sequences of operations atomically, such sequences of operations are also referred to herein as atomic operations. In such an implementation, as... Figure 1 As shown, the second instruction set processing unit can take the form of an atomic processing unit 40. Although atomic processing units can be located in various positions within the device, in Figure 1In the example shown, the atomic processing unit 40 is depicted as being disposed within the load / store unit 35 and arranged to perform atomic operations on data stored in the Level 1 data cache 45. This implementation may be referred to as a “near” implementation because the data operated on by the atomic processing unit is stored in a cache hierarchy tightly coupled to the processing circuitry 15, in this case, the Level 1 data cache 45 provided in association with the processing circuitry 15.

[0055] Figure 2 This is a schematic diagram illustrating the fields that can be provided within the previously mentioned program-specified instructions. In the specific embodiment described with reference to the accompanying drawings, the program specified by such instructions is used to perform the previously mentioned atomic operations, and therefore the program-specified instructions can be referred to as user-defined atomic instructions. These instructions are user-definable because a programmer can write a program whose execution will be triggered in response to decoding the user-defined atomic instructions. As previously mentioned, the program will be written using instructions from a second instruction set, and in one example embodiment, the second instruction set will take the form of a dedicated instruction set containing a limited number of instructions that define only a core set of operations, but in which the core set of operations can be combined in various different ways to enable the atomic processing unit 40 to perform a wide variety of useful atomic operations.

[0056] The user-defined atomic instruction 100 includes an opcode field 105, which is used to define the instruction as a user-defined atomic instruction and thus can be used to distinguish the instruction from other instructions in the first instruction set. The program operand field 110 then specifies the program operands. The program operands can identify the program to be executed in various ways, but as previously mentioned in an example embodiment, the program will have already been stored in one or more registers 20 accessible to the processing circuitry 15 before the user-defined atomic instruction is executed; therefore, the associated one or more registers can be identified by the program operand field 110.

[0057] Another field, 115, is used to identify the memory location operand. This provides sufficient information to identify a location in memory where data will be manipulated by the program when it executes. The memory location operand can take various forms, but in one example, it can identify register 20, whose stored data value can be used to identify the memory location, for example, by using this data value as an offset to add to the base address to identify the memory address to be accessed. In another example, the memory location operand can identify the stack pointer used to identify the memory address to be accessed.

[0058] In one example implementation, in addition to the program operand field 110 and the memory location operand field 115, one or more additional fields 120 may be provided to specify one or more input value operands. Each input value operand can be used to identify the input value to be used by the atomic processing unit 40 when executing a program-defined sequence of operations. Such input values ​​can be specified in various ways, such as by being specified as an immediate value within an instruction, or by specifying one or more registers whose contents provide those input values.

[0059] In one example implementation, a user-defined atom (UDA) instruction may take one of the following forms:

[0060] UDA <ws>、<W(s+1)>、<W(s+2)>、 <xt>、[<Xn|SP> ]

[0061] or

[0062] UDA <xs>、<X(s+1)>、<X(s+2)>、 <xt>、[<Xn|SP> ]

[0063] Up to three 32-bit registers (as indicated by the labels Ws, W(s+1), and W(s+2)) or three 64-bit registers (as indicated by the labels Xs, X(s+1), and X(s+2)) are used to specify input operands and output values, a 64-bit register Xt (or, in some instances, a register pair) is used to contain the user-defined program, and a 64-bit register Xn or the stack pointer SP is used to specify the target memory location.

[0064] Now refer to Figure 3 Block diagram description Figure 1 Further details of the illustrated atomic processing unit 40 are available in the references. Figure 1 In this particular embodiment, the atomic processing unit 40 is provided as part of the load / store unit 35 and is arranged to perform atomic operations on data stored in a Level 1 data cache 45 associated with the processing circuitry 15.

[0065] When UDA instructions are Figure 1 When the illustrated decoder circuit 10 performs decoding, this causes control signals to be issued to the processing circuit 15. In response to those control signals, the processing circuit 15 obtains a program from one or more relevant registers specified by the UDA instruction and forwards the program to the atomic processing unit 40 via path 175, where the program is stored in buffer 165 used by the decoder 150 of the atomic processing unit 40. Similarly, the processing circuit 15 obtains input operand data from any register specified by the UDA instruction as providing input operands and forwards the input operand data to the atomic processing unit via path 180, where the input operand data is stored in one or more internal registers of internal register 155 provided within the atomic processing unit 40. Additionally, the contents of the reference register Xn or the stack pointer SP are used to identify the target memory location, and the processing circuit (in one example embodiment, LSU 35) is then arranged to read the target memory location to retrieve source data at that memory location, where the retrieved source data is then provided as another input to the atomic processing unit for use in a specific internal register of that set of internal registers 155 within the atomic processing unit 40.

[0066] Subsequently, decoder circuitry 150 is arranged to analyze the program stored in buffer 165 in order to identify each individual instruction in the second instruction set that constitutes the program. (See later...) Figure 5 and Figure 6 The process will be discussed in more detail. When an instruction is decoded by decoder 150, control signals are sent to execution circuitry 160 within atomic processing unit 40 to cause the operations required by those instructions to be performed. During this process, execution circuitry 160 will access internal register 155 as needed to obtain input operands for the operations and store output values ​​generated during the execution of those operations. In a particular example implementation, the output values ​​are stored back in the same register that provided the input operands, and any resulting data generated for storage back to memory is written back to the same internal register that stored the source data from the original retrieval from memory.

[0067] At least some of the instructions in the second instruction set may be arranged such that the value of a condition code flag is set depending on the result of an operation performed when those instructions are executed, and one or more instructions may then be arranged to be conditionally executed depending on the value of one or more condition code flags when those instructions are encountered. The condition code flags may be stored in the internal storage device 170 of the atomic processing unit 40 for reference by the decoder 150 and / or execution circuitry 160 during program execution.

[0068] Figure 4 This is a flowchart illustrating the steps taken when decoding UDA instructions. As previously discussed, UDA instructions are instructions from the first instruction set and will be referenced previously. Figure 1 The decoder circuit 10 under discussion performs decoding. When such a UDA instruction is decoded at step 200, at step 205, a register containing the program, memory location indication, and any input values ​​is identified, and the processing circuit 15 is triggered to read the information and provide it to the atomic processing unit 40.

[0069] As indicated at step 210, the atomic processing unit stores any provided input values ​​in an internal register, retrieves source data from a specified memory location (as previously stated, this can be done by the atomic processing unit itself or by the LSU on behalf of the atomic processing unit), and stores the retrieved source data in another internal register (typically there is a dedicated internal register for storing such source data). Additionally, the program retrieved from one or more relevant registers in this set of registers 20 is stored in the instruction buffer 165 of the atomic processing unit 40.

[0070] At step 215, the atomic processing unit then decodes each instruction of the program and executes those instructions until the program completes. During this process, the contents of internal register 155 are updated with any result data and output values ​​generated during the execution of the relevant instructions. At step 220, the atomic processing unit then writes the result data back to the originally specified memory location and through path 185 (see...). Figure 3 The contents of the internal register used to store the initially provided input value are output as the output value, so that those output values ​​can be used to update the relevant CPU register, namely, register 20 that provided the input value.

[0071] The execution of a program by an atomic processing unit occurs atomically relative to memory, where atomicity is enforced by the underlying hardware. For example, in a typical data processing system employing a cache hierarchy, different processing units can share access to certain areas of memory, and cache coherence protocols can be used to ensure the consistency of data accessed by multiple processing units. When an atomic operation is performed in response to the previously mentioned UDA instruction, the source data is placed in the Level 1 data cache 45 when accessing it from the memory system, and the associated processing circuit 15 is recorded as having exclusive access to that data. This exclusive state is maintained while all individual operations constituting the atomic operation are executed, thus ensuring that no other processing unit can read or change the state of the data during the execution of the atomic operation.

[0072] Figure 5 The diagram schematically illustrates how the decoder 150 of an atomic processing unit 40, according to an example implementation, uses the instruction buffer 165. A program read from one or more associated registers 20 is forwarded to the atomic processing unit 40 to be stored in the instruction buffer 165. The decoder then analyzes the contents of the instruction buffer, starting from the first instruction of the identified program. In one example implementation, the second instruction set is a variable-length instruction set, and therefore the number of bits used to define any given instruction depends on the type of instruction. Thus, starting with the first instruction in the sequence, the decoder analyzes the opcode portion to identify the type of instruction, and after doing so, determines the total number of bits forming the instruction. Those total bits can then be analyzed to fully decode the instruction, for example, to identify which internal registers contain the source / input data to be used by the instruction, any conditions that must be met to execute the instruction, etc.

[0073] When each instruction is decoded, the bits that formed the instruction are discarded, and a predetermined number of bits of a predefined bit value are inserted into the instruction buffer. In one example implementation, the same number of bits as those that formed the instruction just decoded are inserted. The instruction buffer can be physically constructed in various ways, but it can be viewed as a logical implementation of a shift register, where each decoded instruction is shifted out of the register, and a corresponding number of bits of a predefined bit value are shifted into the other end of the buffer.

[0074] like Figure 5 As illustrated in the diagram, when each instruction of a program is decoded, the boundaries between the instructions that form the program are identified. Figure 5 The boundary formed between the three instructions 230, 235, and 240 is shown. The pre-bit value inserted when decoding each instruction can take many forms, but in one example, it is a logic 0 value. As will be discussed in more detail below, this can have several benefits, and specifically allows a termination instruction that identifies the end of the program to be implicitly added to the instruction sequence, which can be useful, for example, when there is insufficient space in one or more registers to specify that the program explicitly includes a termination instruction.

[0075] It should be understood that the exact instructions to be included in the second instruction set may vary depending on the specific implementation. For the sake of illustrating a particular example only, the second instruction set may include the following instructions:

[0076] 1. MOV reg1, reg2 - Move and set condition flags

[0077] 2. ADD reg1 and reg2 - add together and set condition flags.

[0078] 3. SUB reg1, reg2 - Remove and set conditional flags

[0079] 4. CMP reg1, reg2 - Compare and set conditional flags

[0080] 5. SET reg1, reg2 - Set bits (bitwise OR) and set condition flags.

[0081] 6. AND reg1, reg2 - bitwise AND setting of condition flags

[0082] 7. EOR reg1, reg2 - bitwise XOR and set condition flags

[0083] 8. SKIP cond, #count - conditionally skip instructions (when the condition is met).

[0084] 9. End (can be encoded as SKIP NEVER, especially when SKIP NEVER is encoded as 0b0000000)

[0085] In one example implementation, ALU instructions (except CMP) can be arranged to be destructive and rewrite the first register operand, thereby avoiding the need to specify the destination operand separately.

[0086] In one example implementation, internal register 155 may include four 32- or 64-bit registers, referred to herein as registers R0 through R3. In one particular implementation, register R0 is initialized with a value obtained from a target memory location, and its value is subsequently written back to that memory location upon program execution completion. Registers R1 through R3 may be initialized from scalar CPU registers specified in UDA instructions, and then updated with the values ​​of registers R1 through R3 upon program execution completion. In addition to the registers mentioned above, an implicit four-bit condition flag register may be provided to capture the condition code flags NZCV (N is set if the result of the operation is negative, Z is set if the result of the operation is zero, C is set if the operation produces a carry (or a borrow on subtraction), and V is set if the operation produces an overflow).

[0087] By making such selections of the instructions that form the second instruction set, and by providing the aforementioned internal registers, the instructions can be effectively encoded as follows:

[0088] 1.3 bits, used to encode operations;

[0089] 2.2 bits are used to encode register specifiers;

[0090] 3.4 bits are used to encode conditions, such as standard 15 Arm condition codes (preserving the NEVER condition); and

[0091] 4.3 bits are used to encode the count (the number of instructions to skip), allowing skipping from 1 to 8 instructions.

[0092] Therefore, instructions are 7 bits (ALU instructions) or 10 bits (skip) long, allowing up to 9 to 10 instructions in a 64-bit program. As previously mentioned, when an instruction is decoded, the instruction stream (program) is shifted by the corresponding number of bits (7 or 10), and in one example implementation, an equivalent number of logical zero values ​​are shifted in. The program execution ends when only zeros remain in the instruction stream. As previously discussed, in some implementations, for example, if the end instruction is encoded as all zeros, the final explicit end instruction can be omitted. In one particular implementation, this is achieved by reusing the reserved code used for skip instructions. Specifically, in one example implementation, the opcode for the skip instruction is "000", and the reserved condition code is "0000", so if the encoding "0000000" is encountered, the instruction is interpreted as an end instruction, not as a skip instruction with the condition "0000".

[0093] Figure 6 The diagram illustrates the use of this instruction set, where instruction buffer 165 contains bit sequences 250, 260, 270, 280, followed by a series of logic zero values, totaling 64 bits. Table 245 indicates the three-bit encoding for each instruction. Thus, the first instruction bit sequence 250 is interpreted as a subtraction instruction 255, where registers R2 and R0 are designated as operands. The next instruction bit sequence 260 is interpreted as a skip instruction 265. The four condition code bits "cccc" can take any valid condition, and therefore any four-bit sequence other than "0000" (as mentioned earlier, this is a reserved condition). In the specific example shown, it is assumed that the condition code specifies an "equality" condition, and the remaining three bits of the instruction identify that an instruction should be skipped if the condition is met.

[0094] The next instruction bit sequence 270 identifies the addition instruction 275, where registers R0 and R1 are designated as operands. Then, the final instruction bit sequence 280 is determined to be the sequence "0000000", and is therefore interpreted as the end instruction 285 as previously discussed, which allows the program to terminate early without needing to decode any remaining bits in the instruction buffer 165.

[0095] As mentioned above, Figure 1 The example arrangement illustrates a near-implementation of atomic processing unit 40. However, the techniques described herein are not limited to use in conjunction with this near-implementation. For example, in an alternative example embodiment, processing circuitry may be arranged to be coupled to the atomic processing unit via interconnects, and the atomic processing unit may be triggered to execute a program-defined sequence of operations on data stored in a cache hierarchy associated with the atomic processing unit by asserting a request on the interconnects. In this case, the atomic processing unit may be located further away in the system in association with a cache hierarchy further away from the processing circuitry (e.g., a cache hierarchy shared among multiple instances of processing circuitry within the system). This embodiment may be referred to as a "far" embodiment, and examples of this arrangement are shown in... Figure 7 As shown in the image.

[0096] In this example, three processing units 300, 305, and 310 are provided, each with its own LSU 325, 330, and 335, and each with its own associated Level 1 data cache 327, 332, and 337. Each processing unit is connected to main storage 320 via a system interconnect 315, and the system interconnect may have one or more additional cache tiers associated with it to cache data that can then be accessed by any of the processing units. In the example shown, a system cache 345 is present, and access to this system cache is controlled by an entity 340 referred to herein as the master node. The master node may be configured to implement a cache coherence protocol to ensure a consistent view of data within the system, and as those skilled in the art will understand, the master node may therefore be configured to issue listener requests to the Level 1 caches 327, 332, and 337 when implementing the cache coherence protocol to check what data is cached in any local Level 1 cache, and to cause coherence actions based on those checks. For example, processor 300 may want to load the data value of a cache line into its L1 data cache 327 so that it can then perform operations on the data. Requests for the data can be published to system interconnect 315, causing master node 340 to initiate some cache coherence actions to ensure that the latest version of the data is retrieved in L1 data cache 327, and to invalidate or mark the local cache copies of those processing units if they attempt to access the data, in order to identify that a coherence check should be performed to ensure that the latest version of the data is retrieved at that time.

[0097] according to Figure 7 In the example shown, atomic processing unit 350 can be associated with master node 340 to perform atomic operations on data stored in associated system cache 345. In some cases, performing operations on data in system cache 345 may be more efficient because it reduces the level of prying required to implement cache coherency protocols and the extent to which data moves between caches compared to storing data in a cache tightly coupled to one of the processing units. Therefore, performing operations on data in system cache 345 may result in a higher aggregation update rate (under contention).

[0098] When this remote implementation is adopted, if the decoder in one of the processing units 300, 305, 310 decodes the previously mentioned UDA instructions, the required program data, memory location information, and any user operand data can be collected from the relevant registers and then output to the atomic processing unit 350 within a request issued via the system interconnect 315. The atomic processing unit 350 can then execute the program in the same manner as previously described with reference to the atomic processing unit 40, but in this case, the source data stored in the system cache 345 can be processed, and any resulting data can then be written back to the system cache to overwrite the source data.

[0099] In some example implementations, the system may provide both near-concrete and far-concrete implementations of the atomic processing unit, with some atomic operations executed using the near-concrete implementation and others using the far-concrete implementation. Various factors can be considered when deciding whether to use a near-concrete or far-concrete implementation for any given atomic operation. For example, when deciding whether to use a near-concrete or far-concrete implementation to execute a program, consideration can be given to the contention for multiple instances of the processing unit accessing the source data.

[0100] The techniques described in this article can be used to enable the atomic execution of a wide variety of operations. Purely to illustrate some example use cases, three examples of programs that can be written using the specific second instruction set discussed earlier will now be discussed, where those programs are then specified as program operands of UDA instructions.

[0101] First, consider the following form of atomic addition, except for the function:

[0102] int atomic_add_unless(v, a, u)

[0103] {

[0104] if (v != u)

[0105] {

[0106] v += a;

[0107] Returns a non-zero value;

[0108] }

[0109] else / / v == u

[0110] {

[0111] Returns 0;

[0112] }

[0113] }

[0114] When using the techniques described herein, the following inputs and outputs can be specified:

[0115] enter :

[0116] R0v reads the memory operand from this location.

[0117] R1a register input operand

[0118] R2u register input operand

[0119] Register R3 is used to input operands (unused)

[0120] Output :

[0121] R0v is the memory operand written to this location.

[0122] The output value of register R1a remains unchanged.

[0123] R2res register output value

[0124] The output value of register R3 remains unchanged.

[0125] Then, the second instruction set discussed earlier can be used to write the following program to perform the above functions:

[0126] / / Subtract v from u

[0127] Subtract R2 and R0 (7 bits)

[0128] / / If diff == 0, skip instruction 1.

[0129] Skip EQ, #1 (10 bits)

[0130] / / v != u (R2 != 0), add a to v

[0131] Add R0 and R1 (7 bits)

[0132] / / Else v == u (R2 == 0)

[0133] / / End the program (fill the remaining bits with zeros)

[0134] Finish

[0135] Therefore, the resulting program size is 24 bits, which can be easily accommodated in a single register.

[0136] As a second example, consider an atomic ring buffer getter function, which is typically used by enqueue and dequeue operations. The following inputs and outputs can be specified:

[0137] enter :

[0138] The memory operand read from this location at the tail of R0

[0139] The R1HeadCap register input operands are: header index + ring buffer capacity (supports both enqueue and dequeue).

[0140] R2 requests the register input operand.

[0141] R3 minimum register input operand

[0142] Output :

[0143] The memory operand at position R0 is written to the end of the memory location.

[0144] The R1 actual register output value: The software must compare the returned actual value with the minimum value to determine whether the operation was successful (actual value >= minimum value).

[0145] The register output value requested by R2 (unchanged)

[0146] R3 minimum register output value (unchanged)

[0147] Then, the second instruction set discussed earlier can be used to write the following program to perform the atomic ring buffer acquisition function:

[0148] / / Subtract the tail: R0 from HeadCap: R1, and store it in the actual: R1

[0149] Subtract R1 and R0 (7 bits)

[0150] / / Compare the actual value with the requested value

[0151] / / If the requested value is less than the actual value, then use the requested value.

[0152] Compare R1 and R2 (7 bits)

[0153] / / If the difference is greater than 0, skip instruction 1.

[0154] Skip GT, #1 (10 bits)

[0155] Move R1 and R2 (7 bits)

[0156] / / Compare the actual value with the minimum value

[0157] Compare R1 and R3 (7 bits)

[0158] / / If the actual value is less than the minimum value, then cancel.

[0159] / / If the difference is less than 0, skip instruction 1.

[0160] Skip LT, #1 (10 bits)

[0161] / / Add the actual value to the end

[0162] Add R0 and R1 (7 bits)

[0163] / / End the program (fill the remaining bits with zeros)

[0164] Finish

[0165] Therefore, the resulting program size is 55 bits.

[0166] As a third example, the following form of Golang runtime function can be used for garbage collection (see https: / / github.com / golang / go / blob / 5b72f45dd17314af39627c2fcac0fbc099b67603 / src / runtime / mgcsweep.go#L169-L184):

[0167] for {

[0168] state := a.state.Load()

[0169] if (state&^sweepDrainedMask)-1 >= sweepDrainedMask {

[0170] Draw ("Mismatched activeSweep start / end")

[0171] }

[0172] if a.state.CompareAndSwap(state, state-1) {

[0173] return;

[0174] }

[0175] }

[0176] The following inputs and outputs can be specified:

[0177] The memory operand read from this location in state R0.

[0178] R1~sweepDrainedMask register input operands

[0179] R2const0 register is used to input operands

[0180] R3sweepDrainedMask register input operand

[0181] Output :

[0182] The R0 state is written to the memory operand at this location.

[0183] R1 result register output value: (state&^sweepDrainedMask)-1

[0184] The output value of register R2const0 remains unchanged.

[0185] The output value of the R3sweepDrainedMask register remains unchanged.

[0186] Then, the second instruction set discussed earlier can be used to write the following program to perform the above functions:

[0187] / / R1 = R0 & ~sweepDrainedMask

[0188] And R1, R0 (7 bits)

[0189] / / R1-=1

[0190] Subtract R1 and R2 (7 bits)

[0191] / / Compare R1 with sweepDrainedMask

[0192] Compare R1 and R3 (7 bits)

[0193] / / If R1 >= sweepDrainedMask, skip the update.

[0194] Skip GE, #1 (10th position)

[0195] / / R0-=1

[0196] Subtract R0 and R2 (7 bits)

[0197] / / End the program (fill the remaining bits with zeros)

[0198] Finish

[0199] Therefore, the resulting program size is 38 bits.

[0200] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0201] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0202] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0203] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0204] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transient computer-readable medium such as semiconductors, disks, or optical discs. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0205] Figure 8 Specific implementations of emulators that can be used are illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are commonly referred to as emulators, in part because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters.

[0206] Typically, the simulator implementation runs on a host processor 430, which optionally runs a host operating system 420 that supports the simulator program 410. In some arrangements, multiple simulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of simulation is given in the following literature: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0207] With respect to embodiments previously described with reference to specific hardware constructions or features, equivalent functionality may be provided in simulated embodiments by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. Where one or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 430), some simulated embodiments may utilize the host hardware where appropriate.

[0208] For example, simulator code 410 may include instruction decoding program logic 412 to decode instructions in the target code—therefore, the instruction decoding program logic may emulate the previously described instruction decoder 10. Simulator code 410 may also include register emulation program logic 414 to emulate the aforementioned register 20. The simulator program also includes data processing program logic 416 for processing instructions in the target code 400 (thus terminating the simulation processing circuit 15) and atomic processing program logic 418 for emulating the atomic processing unit 40.

[0209] The simulator program 410 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 400 (which may include application programs, operating systems, and management programs), the same as the interface of the hardware architecture modeled by the simulator program 410. Therefore, the program instructions of the target code 400 (including the aforementioned program-specific instructions (e.g., UDA instructions)) can be executed from within the instruction execution environment using the simulator program 410, enabling the host computer 430, which does not actually possess the hardware features of the aforementioned device 5, to emulate these features.

[0210] Accordingly, simulator code 410 is an example of a computer program including instructions that, when executed by a host data processing device, control the host data processing device to provide an instruction execution environment for executing target program code. The computer program includes:

[0211] Instruction decoding program logic, which decodes instructions from a first instruction set, wherein the instruction decoding program logic generates control signals in response to instructions from the first instruction set; and

[0212] Data processing program logic that, in response to control signals, causes to execute operations defined by these instructions;

[0213] in:

[0214] The instruction decoding program logic is configured to issue control signals to the data processing program logic in response to program-specified instructions of the specified memory location operand and program operand of the first instruction set, so that the second instruction set processing program logic is triggered to execute a program identified by the program operand, so as to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand, the program including one or more instructions of the second instruction set defining operations supported by the second instruction set processing program logic.

[0215] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0216] In this application, a list of features beginning with the phrase "at least one of" means that any one or more of those features may be provided independently or in combination. For example, "at least one of [A], [B], and [C]" covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0217] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.< / xt> < / xs> < / xt> < / ws>

Claims

1. An apparatus comprising: decoder circuitry to decode instructions of a first instruction set, wherein the decoder circuitry generates control signals in response to instructions of the first instruction set; and processing circuitry to cause performance of operations defined by the instructions in response to the control signals; wherein: the decode circuitry is arranged, in response to a program specified instruction of the first instruction set that specifies a memory location operand and a program operand, to issue control signals to the processing circuitry to cause a second instruction set processing unit to be triggered to execute a program identified by the program operand in order to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand, the program comprising one or more instructions of the second instruction set that define operations supported by the second instruction set processing unit.

2. The apparatus of claim 1, wherein the program specified instruction is an atomic instruction, the second instruction set processing unit is an atomic processing unit, and the sequence of operations is arranged to be performed atomically.

3. The apparatus of claim 1 or claim 2, the apparatus further comprising: a set of registers accessible to the processing circuitry; and the program specified instruction is configured to specify the program operand by identifying at least one register from the set of registers that contains the program to be executed by the second instruction set processing unit.

4. The apparatus of any preceding claim, wherein the program specified instruction further specifies at least one input value operand that identifies at least one input value to be used by the second instruction set processing unit in performing the sequence of operations defined by the program.

5. The apparatus of any preceding claim, wherein each instruction of the second instruction set is encoded using fewer bits than each instruction of the first instruction set.

6. The apparatus of any preceding claim, wherein the second instruction set is a variable length instruction set such that the number of bits used to encode any given instruction of the second instruction set depends on the type of the given instruction.

7. The apparatus of any preceding claim, wherein: the apparatus is arranged to be coupled to a memory system that provides a multi-level cache; the second instruction set processing unit is provided by the processing circuitry; and the second instruction set processing unit is arranged to perform the sequence of operations on data held in a cache level accessible to the processing circuitry.

8. The apparatus of any of claims 1 to 6, wherein: the apparatus is arranged to be coupled to a memory system that provides a multi-level cache; the processing circuitry is arranged to be coupled to the second instruction set processing unit via an interconnect, and to trigger the second instruction set processing unit to perform the program by asserting a request on the interconnect to cause the second instruction set processing unit to perform the sequence of operations on data held in a cache level associated with the second instruction set processing unit.

9. The apparatus according to any preceding claim, wherein the second instruction set processing unit comprises: An instruction buffer storage device, the instruction buffer storage device being used to receive the program identified by the program operand; An additional decoding circuit is used to analyze the contents of the instruction buffer storage device in order to decode each instruction in the second instruction set provided by the program; and An execution circuit is configured to perform the operation required for each instruction in response to a control signal generated by the additional decoding circuit.

10. The apparatus of claim 9, wherein the program is formed by a series of bits, and the additional decoding circuitry is arranged to determine the type of instruction from the opcode bits for each instruction in the second instruction set provided by the program, and to determine the total number of bits defining the instruction depending on the determined type of the instruction.

11. The apparatus of claim 10, wherein the second instruction set includes instructions for identifying when the end of the program has been reached, and the end instructions are encoded as a sequence of bits all having the same predetermined bit value.

12. The apparatus of claim 11, wherein when each instruction is decoded by the additional decoding circuitry, the second instruction set processing unit is arranged to extend the series of bits by adding a plurality of bits of the predetermined value.

13. The apparatus according to any one of claims 10 to 12, wherein the second instruction set includes a skip instruction for causing one or more subsequent instructions in the program to be skipped when a condition defined by the skip instruction is met.

14. The apparatus of claim 13, wherein at least one instruction in the second instruction set is arranged, when executed, to set one or more condition code flags depending on the result generated by the execution of the instruction, and the execution circuitry is arranged to determine, with reference to the state of the one or more condition code flags, whether the condition defined by the skip instruction is satisfied.

15. The apparatus according to claim 13 or claim 14, wherein: The condition is defined by a condition field within the encoding of the skip instruction; The second instruction set includes instructions for identifying when the end of the program has been reached; and The end instruction is encoded using the same opcodes used to identify the skip instruction, but the condition field is set to a reserved value not used to define the condition.

16. The apparatus according to any of the preceding claims, wherein: The second instruction set processing unit includes multiple internal registers; When triggered to execute the operation sequence, the second instruction set processing unit is arranged to store source data obtained from the location in memory identified by the memory location operand in a given internal register; and When the operation sequence is completed, the second instruction set processing unit is arranged to write the result data to the location in the memory identified by the memory location operand, at least when the result data is different from the source data.

17. The apparatus of claim 16, wherein the program specifying instruction specifies at least one input value operand, the at least one input value operand identifying at least one input value to be used by the second instruction set processing unit when executing the sequence of operations defined by the program, and the processing circuitry is arranged to provide the at least one input value to the second instruction set processing unit for storage in at least one internal register other than the given internal register among the plurality of internal registers.

18. The apparatus according to claim 17, wherein: The program specifies that the instructions are configured to specify the at least one input value operand by identifying at least one register accessible by the processing circuit containing the at least one input value; The processing circuitry is configured to read the at least one input value from the at least one register for supplying to the second instruction set processing unit; and The second instruction set processing unit is arranged to maintain at least one output value during the execution of the operation sequence, and is arranged to provide the at least one output value to the processing circuit for storage in the at least one register containing the at least one input value when the operation sequence is completed.

19. The apparatus of claim 18, wherein during the execution of the operation sequence, the second instruction set processing unit is arranged such that the at least one output value is maintained in the at least one internal register among the plurality of internal registers for storing the at least one input value.

20. A method of operating a device, the method comprising: A decoder circuit is employed to decode instructions of a first instruction set, wherein the decoder circuit generates control signals in response to instructions of the first instruction set; Processing circuitry is employed to execute the operation defined by the instructions in response to the control signal; and The decoding circuit is configured to send a control signal to the processing circuit in response to a program-specified instruction of a specified memory location operand and a program operand of the first instruction set, so that the second instruction set processing unit is triggered to execute a program identified by the program operand, so as to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand; The program includes one or more instructions of the second instruction set that define the operations supported by the second instruction set processing unit.

21. A computer program comprising instructions that, when executed by a host data processing device, control the host data processing device to provide an instruction execution environment for executing target program code, the computer program comprising: An instruction decoding program logic, wherein the instruction decoding program logic is used to decode instructions of a first instruction set, wherein the instruction decoding program logic generates control signals in response to instructions of the first instruction set; and Data processing program logic, which, in response to the control signal, causes to execute the operation defined by the instruction; in: The instruction decoding program logic is configured to issue a control signal to the data processing program logic in response to a program-specified instruction of a specified memory location operand and a program operand of the first instruction set, thereby triggering the second instruction set processing program logic to execute a program identified by the program operand, so as to perform a sequence of operations defined by the program on data accessed at a location in memory identified by the memory location operand, the program including one or more instructions of the second instruction set defining operations supported by the second instruction set processing program logic.

22. A computer-readable medium for storing computer-readable code for manufacturing an apparatus according to any one of claims 1 to 19.

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