A high-precision waveform controller based on FPGA and SOC architecture
By co-designing FPGA and SOC architectures, and utilizing a ping-pong architecture and weighted average algorithm, the shortcomings of traditional DDS controllers in terms of accuracy, flexibility, and real-time performance are solved, achieving seamless switching and high-speed data transmission for high-precision waveform controllers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING DAHUA RADIO INSTR FACTORY
- Filing Date
- 2026-03-11
- Publication Date
- 2026-06-23
AI Technical Summary
In the existing technology, FPGA or microprocessor-based DDS waveform controllers have many technical problems in terms of real-time performance and flexibility in high-precision waveform controllers. In the existing technology, traditional DDS controllers are usually only implemented based on FPGA or microprocessor, which makes it difficult to meet the requirements of high precision, low latency and complex interaction at the same time. They also have problems such as waveform switching delay, insufficient communication bandwidth and low data storage efficiency.
A high-precision waveform controller based on FPGA and SOC architecture is adopted, and communication control is realized through SPI/I2C or AXI/APB bus. Combined with ping-pong architecture and weighted average algorithm, the accuracy, flexibility and real-time performance of waveform generation are improved.
It significantly improves the accuracy, flexibility, and real-time performance of waveform generation, enabling seamless waveform switching and high-speed data transmission to meet the needs of high-precision applications.
Smart Images
Figure CN122260945A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to waveform control technology, and more particularly to a high-precision waveform controller based on FPGA and SOC architecture. Background Technology
[0002] In modern electronic systems, high-precision waveform generation technology is widely used in fields such as communications, radar, medical equipment, and test and measurement instruments. Direct digital frequency synthesis (DDS) technology has become one of the core technologies for waveform generation due to its advantages such as high frequency resolution and continuously adjustable phase. However, traditional DDS implementations usually rely on a single hardware platform (such as FPGA or microprocessor). Limited by hardware resources, real-time requirements, and flexibility needs, a single architecture cannot simultaneously meet the requirements of high precision, low latency, and complex interactions.
[0003] In recent years, with the development of heterogeneous computing architectures, the co-design of System-on-Chips (SoCs) and FPGAs has provided a new solution for high-performance waveform controllers. The FPGA is responsible for implementing the high-speed, high-precision DDS core logic, while the SoC is responsible for user interaction, parameter configuration, and system scheduling. Their collaborative work significantly improves the overall performance and scalability of the waveform control system. Therefore, combining the advantages of both to design a high-precision, highly flexible waveform controller has significant engineering value.
[0004] Existing technology and its limitations:
[0005] Despite the significant advantages of DDS technology in waveform synthesis, existing FPGA- or microprocessor-based DDS waveform controllers still suffer from several limitations. First, traditional DDS controllers are typically implemented solely on FPGAs or microprocessors. While FPGA solutions offer strong parallelism, they suffer from limited user interaction; microprocessor solutions, on the other hand, offer high flexibility but are limited in real-time performance and frequency resolution. For example, existing solutions using external DDS chips, while capable of basic waveform generation, fail to fully utilize the potential of SoC-FPGA co-design, leading to increased system complexity and insufficient flexibility. Furthermore, these solutions often rely on low-speed communication interfaces (such as SPI / I2C), making it difficult to meet the demands of high-speed data transmission and limiting the real-time performance of waveform switching.
[0006] In waveform switching, traditional single-BRAM architecture DDS controllers suffer from significant latency issues, failing to achieve seamless switching and struggling to support dynamic waveform updates or data simulation. While existing dual-channel DDS switching mechanisms can improve frequency agility, their architecture relies on external switching circuits, increasing hardware complexity and failing to address phase accuracy and SoC-FPGA co-design issues. Furthermore, these solutions typically employ integer approximations for frequency and phase control word calculations, leading to quantization errors in output frequency and phase, which are insufficient for high-precision applications. The nonlinearity error of the phase accumulator further degrades waveform quality, particularly noticeable in low-frequency or high-resolution scenarios.
[0007] In terms of communication architecture, existing technologies typically employ low-speed interfaces (such as SPI / UART) in their discrete SoC and FPGA designs, resulting in limited bandwidth and difficulty in meeting the demands of high-speed data transmission. While integrated solutions (such as the AXI bus) can provide higher transmission rates, their optimized designs have not yet been fully applied in the DDS field. Furthermore, waveform data storage and retrieval are inefficient, lacking dynamic switching mechanisms, leading to insufficient real-time performance. For example, in existing technologies, waveform data is usually stored in a single BRAM, requiring data reloading during switching, thus failing to achieve seamless transitions.
[0008] In summary, existing technologies have significant shortcomings in terms of high-precision waveform control, real-time switching, and communication efficiency.
[0009] In view of this, the present invention is hereby proposed. Summary of the Invention
[0010] The purpose of this invention is to provide a high-precision waveform controller based on FPGA and SOC architecture to solve the above-mentioned technical problems in the prior art.
[0011] The objective of this invention is achieved through the following technical solution:
[0012] A high-precision waveform controller based on FPGA and SOC architecture includes a SOC, FPGA and waveform implementation circuit connected in sequence.
[0013] The SoC and FPGA are either two separate chips or two chips integrated and packaged together.
[0014] If there are two independent chips, communication and control are achieved through the SPI / I2C physical bus;
[0015] If it is in the form of an integrated package, then communication control is performed using buses such as AXI / APB.
[0016] Compared with existing technologies, the high-precision waveform controller based on FPGA and SOC architecture provided by this invention significantly improves the accuracy, flexibility and real-time performance of waveform generation through ping-pong architecture, weighted averaging algorithm and high-speed bus communication. Attached Figure Description
[0017] Figure 1 A framework diagram of a high-precision waveform controller based on FPGA and SOC architecture is provided for embodiments of the present invention.
[0018] Figure 2 This is a block diagram illustrating the implementation of an embodiment of the present invention. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0020] First, the following explanations are provided for the terms that may be used in this article:
[0021] The terms “including,” “contains,” “comprising,” “having,” or other similar semantic descriptions shall be interpreted as non-exclusive inclusion.
[0022] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.
[0023] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0024] like Figure 1 As shown, a high-precision waveform controller based on FPGA and SOC architecture includes a SOC, an FPGA and a waveform implementation circuit connected in sequence.
[0025] The SoC and FPGA are either two separate chips or two chips integrated and packaged together.
[0026] If there are two independent chips, communication and control are achieved through the SPI / I2C physical bus;
[0027] If it is in the form of an integrated package, then communication control is performed using buses such as AXI / APB.
[0028] The SoC provides two functions: one for users and one for FPGAs.
[0029] First, the SoC is user-oriented and provides interactive functions, allowing users to set the frequency, starting phase angle, amplitude, and select waveforms.
[0030] Secondly, the SoC is designed for FPGA, converting the user-set frequency and starting phase angle into DDS frequency control words and phase control words respectively, and sending the frequency control words, phase control words, amplitude, and waveform to the FPGA via the bus.
[0031] The FPGA includes a DDS controller and a filter, and receives data waveform points from the SoC.
[0032] The DDS controller contains two BRAMs, implementing a ping-pong architecture for enabling user waveform switching, and the filter smooths the DDS waveform output.
[0033] The waveform implementation circuit implements the DDS waveform data sent by the FPGA, including a PID control algorithm and / or a DAC module.
[0034] The interactive functions include a touchscreen and a UART serial port;
[0035] The waveforms include sine waves, square waves, triangle waves, sawtooth waves, and custom arbitrary waveforms.
[0036] By introducing a weighted average, the accuracy of precision frequency control and phase control is improved.
[0037] In summary, the high-precision waveform controller implemented based on FPGA and SOC architecture in this embodiment of the invention significantly improves the accuracy, flexibility, and real-time performance of waveform generation through ping-pong architecture, weighted averaging algorithm, and high-speed bus communication.
[0038] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.
[0039] like Figure 1As shown, the waveform controller framework of this invention consists of three parts: a SoC (System on Chip), an FPGA (File Programmable Gate Array), and waveform implementation circuitry. The SoC and FPGA can be two independent chips or a single chip packaged together. The difference lies in the connection method for communication. If they are two independent chips, communication control can be achieved through physical buses such as SPI / I2C. If they are integrated and packaged, reliable communication control can be achieved using buses with faster transmission rates such as AXI / APB.
[0040] The SoC provides two functions: one for users and one for the FPGA. First, for users, the SoC offers interactive features (such as a touchscreen and UART serial port), allowing users to set the waveform's frequency, starting phase angle, amplitude, and select waveforms such as basic waveforms like sine, square, triangle, and sawtooth waves, as well as custom arbitrary waveforms (where the number of waveform data points must be the same as the BRAM size of the FPGA's DDS (Direct Digital Synthesis) control section). Second, for the FPGA, the SoC converts the user-set frequency and starting phase angle into DDS frequency control words and phase control words, respectively, and sends these to the FPGA via the bus.
[0041] The FPGA section consists of a DDS controller and a filter. It accepts the number of data waveform points sent from the SoC. The DDS control section contains two BRAMs to implement a ping-pong architecture, which facilitates the user's waveform switching function. The filter section smooths the DDS waveform output.
[0042] The waveform implementation circuit implements the DDS waveform data sent by the FPGA, which can be a PID (proportional-integral-derivative) control algorithm, a DAC (Digital Analog Converter) module, etc.
[0043] Example
[0044] like Figure 2As shown in the figure, a specific embodiment of the present invention is presented. As can be seen from the figure, the core control uses Xilinx's ZYNQ (full name: Zynq-7000 All Programmable SoC) heterogeneous chip, which consists of two parts: PS (Processing System) and PL (Programmable Logic). The PS part contains a dual-core ARM Cortex-A9 core. The Cortex-A9 is an application-level processor that can run embedded operating systems such as Linux, providing users with good interactive performance. The PL part is equivalent to a programmable logic board on an FPGA, based on the Xilinx 7 series FPGA architecture, providing high-speed parallel operation capabilities. Furthermore, the ZYNQ architecture uses the industry-standard AXI interface, realizing a high-bandwidth, low-latency connection between the PS and PL, fully meeting the high-speed data transmission and reception requirements between the PS and PL of the present invention.
[0045] As shown in the figure, the solution consists of three parts: control panel, ZYNQ chip, and DDS waveform realization circuit; the control panel provides interactive functions for users, who can set parameters such as waveform, frequency, phase angle, and amplitude.
[0046] The ZYNQ-PS section mainly implements the waveform data generator function. It generates user-defined DDS waveform data (typically set to an integer multiple of 360, such as 3600, 36000, etc., note: the number of points must be the same as the data size stored in BRAM) through the waveform database and custom waveforms, and sends it to DDR. It also sends user-defined parameters such as frequency, phase angle, and amplitude to the ZYNQ-PL section through the AXI bus.
[0047] The ZYNQ-PL section directly reads the data waveform from the DDR based on the AXI-DMA bus and stores it in local BRAM1 and BRAM2. Through the AXI-Lite bus, the BRAM control state machine receives the frequency control word and phase control word, and is responsible for reading waveform data from BRAM1 and BRAM2. According to the user settings, the BRAM output waveform is switched via the SWITCH module (this architecture can realize more functions, such as data simulation; while BRAM1 outputs the waveform, BRAM2 updates the waveform, thereby realizing the reading and sending of data waveforms of arbitrary length at the user end). Then, after a weighted average algorithm, the waveform is sent to the filter; after filtering, a smooth waveform is obtained and multiplied by the amplitude. Finally, the waveform is sent to the DDS waveform implementation circuit to obtain the final output waveform.
[0048] Let the DDS waveform output frequency of ZYNQ-PL be... Then we have:
[0049]
[0050] It is a frequency control word. For the system sampling rate, such as = 100ksps (kilo samples per second), where N is the BRAM storage depth.
[0051] Output frequency based on waveform High-precision frequency control words can be obtained. The conversion formula is:
[0052]
[0053] DDS waveform output frequency set by the user It needs to be converted into a frequency control word according to the above formula. .
[0054] Assuming the BRAM storage depth N is 3600, then the phase angle accuracy of the output waveform... :
[0055]
[0056] Based on this, to improve phase angle accuracy, a weighted averaging method is used to achieve high-precision phase angle control. Specifically, the implementation method is as follows: assuming the frequency control word... Let kd be a non-integer, where k and d are integer and decimal respectively; then the k and k+1 waveform data read from the BRAM are x(k) and x(k+1) respectively, and the waveform output data is calculated using the weighted average formula. :
[0057]
[0058] The above formula can be used to obtain the DDS output waveform with high-precision phase angle control.
[0059] Finally, the DDS waveform implementation circuit receives the DDS waveform data sent by the FPGA and implements it. Specifically, it can be a PID (proportional-integral-derivative) control algorithm, a DAC module, etc.
[0060] The innovation of this invention lies in:
[0061] The SoC part generates waveform data, while the FPGA part is responsible for the specific implementation of the DDS controller.
[0062] The DDS controller uses a ping-pong architecture, which can easily achieve lossless waveform switching and can perform more functions, such as data simulation, compared to a single BRAM architecture.
[0063] Introducing a weighted average can significantly improve the accuracy of both frequency control and phase control.
[0064] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.
Claims
1. A high-precision waveform controller based on FPGA and SOC architecture, characterized in that, This includes a SoC, an FPGA, and a waveform implementation circuit connected in sequence; The SoC and FPGA are either two separate chips or two chips integrated and packaged together. If there are two independent chips, communication and control are achieved through the SPI / I2C physical bus; If it is in an integrated package form, then the AXI / APB bus is used for communication control.
2. The high-precision waveform controller based on FPGA and SOC architecture according to claim 1, characterized in that, The SoC provides two functions: one for users and one for FPGAs. First, the SoC is user-oriented and provides interactive functions, allowing users to set the frequency, starting phase angle, amplitude, and select waveforms. Secondly, the SoC is designed for FPGA, converting the user-set frequency and starting phase angle into DDS frequency control words and phase control words respectively, and sending the frequency control words, phase control words, amplitude, and waveform to the FPGA via the bus.
3. The high-precision waveform controller based on FPGA and SOC architecture according to claim 2, characterized in that, The FPGA includes a DDS controller and a filter, and receives data waveform points from the SoC. The DDS controller contains two BRAMs, implementing a ping-pong architecture for enabling user waveform switching, and the filter smooths the DDS waveform output.
4. The high-precision waveform controller based on FPGA and SOC architecture according to claim 3, characterized in that, The waveform implementation circuit implements the DDS waveform data sent by the FPGA, including a PID control algorithm and / or a DAC module.
5. The high-precision waveform controller based on FPGA and SOC architecture according to claim 2, characterized in that, The interactive functions include a touchscreen and a UART serial port; The waveforms include sine waves, square waves, triangle waves, sawtooth waves, and custom arbitrary waveforms.
6. The high-precision waveform controller based on FPGA and SOC architecture according to any one of claims 1 to 5, characterized in that, By introducing a weighted average, the accuracy of precision frequency control and phase control is improved.