Method and apparatus for analyzing repairable yield of chip function modules

Abstract

The application provides a method for analyzing repairable yield of a functional module of a chip, comprising: obtaining total failed die quantities before and after repair of each functional module and design parameter values of each functional module; calculating repairable yield according to the total failed die quantities before and after repair of each functional module; for each functional module, drawing a corresponding point in a rectangular coordinate system with the design parameter value as the horizontal axis and the repairable yield as the vertical axis, linearly fitting a scatter diagram composed of the points to obtain a fitting curve; calculating absolute errors between the corresponding point of each functional module in the rectangular coordinate system and the fitting curve, and screening out abnormal points with absolute errors greater than an error threshold; if the abnormal point is located above the fitting curve, determining that the repairable yield of the functional module corresponding to the abnormal point is normal; and if the abnormal point is located below the fitting curve, determining that the repairable yield of the functional module corresponding to the abnormal point is abnormal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular, to a method and device for analyzing the repairable yield of chip functional modules. Background Art

[0002] As the functions of SoC chips become more and more, the design becomes more and more complex, and its cost is also increasing rapidly. Therefore, improving the yield of chips has become the main index for reducing chip costs and improving chip quality. Since the chip design includes a large number of functional modules with different functions, these functional modules are the key factors that affect whether the chip becomes a qualified product or a defective product. Therefore, analyzing the yield of functional modules helps to improve the yield of the final chip.

[0003] At present, only the defect density of the chip, the chip area, and the functional module area are used to estimate the yield of the chip, and there is no analysis of the repairable yield of functional modules. Summary of the Invention

[0004] The method and device for analyzing the repairable yield of chip functional modules provided by the present invention can analyze the repairable yield of chip functional modules, screen out the functional modules with abnormal repairable yield, so as to deeply analyze the functional modules with abnormal repairable yield, and provide a new analysis direction for yield improvement.

[0005] In a first aspect, the present invention provides a method for analyzing the repairable yield of chip functional modules, the method comprising: obtaining the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter value of each functional module;

[0006] Calculating the repairable yield of each functional module according to the total number of failed dies before repair and the total number of failed dies after repair of each functional module; For each functional module, drawing a corresponding point in a rectangular coordinate system with the design parameter value as the horizontal axis and the repairable yield as the vertical axis, and performing linear fitting on the scatter plot formed by each point to obtain a fitting curve; Calculating the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitting curve, and screening out the abnormal points with an absolute error greater than the error threshold; If the abnormal point is above the fitting curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is normal; if the abnormal point is below the fitting curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is abnormal.

[0007] Optionally, calculating the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair includes: subtracting the total number of failed dies after repair from the total number of failed dies before repair, dividing the difference by the total number of failed dies before repair, and obtaining the repairable yield.

[0008] Optionally, calculating the absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve includes: calculating the distance between the point corresponding to the functional module in the Cartesian coordinate system and the fitted curve to obtain the absolute error.

[0009] Optionally, the design parameter values ​​are physical area, storage size, or number of transistors.

[0010] Secondly, the present invention provides an apparatus for analyzing the repairability yield of chip functional modules, the apparatus comprising: The acquisition unit is used to acquire the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​of each functional module for each functional module. The calculation unit is used to calculate the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair. The fitting unit is used to plot the corresponding points in a rectangular coordinate system with the design parameter values ​​on the horizontal axis and the repairable yield rate on the vertical axis for each functional module, and to perform linear fitting on the scatter plot composed of each point to obtain the fitting curve. The filtering unit is used to calculate the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitted curve, and to filter out outlier points whose absolute error is greater than the error threshold. The judgment unit is used to determine that the repairable yield of the functional module corresponding to the abnormal point is normal when the abnormal point is above the fitting curve, and to determine that the repairable yield of the functional module corresponding to the abnormal point is abnormal when the abnormal point is below the fitting curve.

[0011] Optionally, it is also used to subtract the total number of failed grains after repair from the total number of failed grains before repair, and divide the difference by the total number of failed grains before repair to obtain the repairable yield.

[0012] Optionally, it is also used to calculate the distance between the point corresponding to the functional module in the rectangular coordinate system and the fitted curve to obtain the absolute error.

[0013] Optionally, the design parameter values ​​are physical area, storage size, or number of transistors.

[0014] Thirdly, the present invention provides an electronic device, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above for improving the yield of the analysis chip functional modules.

[0015] Fourthly, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the above-mentioned method for improving the yield of the analysis chip functional modules.

[0016] The method and apparatus for analyzing the repairable yield of chip functional modules provided in this invention calculate the repairable yield of each functional module based on the total number of failed dies before and after repair. A linear fit is performed on a scatter plot of points corresponding to each functional module in a Cartesian coordinate system with design parameter values ​​on the horizontal axis and repairable yield on the vertical axis to obtain a fitted curve. The absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve is calculated. Outliers with absolute errors greater than an error threshold are screened out. The positional relationship between the outlier and the fitted curve is used to determine whether the repairable yield of the corresponding functional module is abnormal. This allows for the analysis of the repairable yield of chip functional modules, screening out functional modules with abnormal repairable yields, and enabling in-depth analysis of these modules to provide new analytical directions for yield improvement. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for analyzing the repairability yield of chip functional modules according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the fitting curve obtained by linearly fitting the corresponding points of each functional module in a rectangular coordinate system with physical area as the horizontal axis and repairability yield as the vertical axis, as provided in the embodiments of the present invention. Figure 3 A table showing the correspondence between the physical area, repairable yield, and absolute error of each functional module provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of a device for analyzing the repairability of chip functional modules according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention provides a method for analyzing the repairability yield of chip functional modules, such as... Figure 1 As shown, the method includes: S11. Obtain the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​for each functional module.

[0020] S12. Calculate the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair.

[0021] S13. For each functional module, plot the corresponding points in a rectangular coordinate system with the design parameter values ​​on the horizontal axis and the repairable yield rate on the vertical axis. Perform linear fitting on the scatter plot composed of each point to obtain the fitting curve.

[0022] S14. Calculate the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitted curve, and filter out outlier points whose absolute error is greater than the error threshold.

[0023] S15. If the abnormal point is located above the fitted curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is normal; if the abnormal point is located below the fitted curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is abnormal.

[0024] The method for analyzing the repairable yield of chip functional modules provided in this invention calculates the repairable yield of each functional module based on the total number of failed dies before and after repair. It then performs linear fitting on a scatter plot of points corresponding to each functional module in a Cartesian coordinate system with design parameter values ​​on the horizontal axis and repairable yield on the vertical axis to obtain a fitted curve. The method calculates the absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve, filters out outliers with absolute errors greater than an error threshold, and determines whether the repairable yield of the corresponding functional module is abnormal based on the positional relationship between the outlier and the fitted curve. This allows for the analysis of the repairable yield of chip functional modules, filtering out functional modules with abnormal repairable yields for in-depth analysis, and providing new analytical directions for yield improvement.

[0025] The method for improving the repairability of chip functional modules according to the present invention will be described in detail below with reference to specific embodiments.

[0026] S21. Obtain the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​for each functional module.

[0027] Typically, after the wafers corresponding to each functional module are manufactured, various manufacturing defects introduced due to process variations result in a certain number of defective dies distributed across the wafer. Wafer sorting is a process where each die on the wafer is tested before packaging. A probe, as fine as a hair and made of gold wire, is attached to the testing head and contacts the pads on the die to test its electrical characteristics. Dies that fail the test are considered defective. These defective dies are then repaired, and the repaired dies undergo wafer sorting again. At this point, some defective dies pass the test, while the rest fail and remain defective even after repair.

[0028] Optionally, the design parameter values ​​can be physical area, storage size, or number of transistors, but are not limited to these.

[0029] In this embodiment, during the wafer picking test, the total number of failed dies before repair, the total number of failed dies after repair, and the physical area of ​​each functional module are obtained in the wafer corresponding to each functional module.

[0030] S22. Calculate the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair.

[0031] Specifically, the total number of failed grains before repair is subtracted from the total number of failed grains after repair, and the difference is divided by the total number of failed grains before repair to obtain the repairable yield.

[0032] S23. For each functional module, plot the corresponding points in a rectangular coordinate system with the physical area of ​​the functional module as the horizontal axis and the repairability yield as the vertical axis. Perform linear fitting on the scatter plot composed of each point to obtain the fitting curve.

[0033] like Figure 2 As shown, the physical area of ​​the functional module is the x-axis, and the repairability of the functional module is the y-axis.

[0034] In this embodiment, the formula for the fitted curve is: 0.1535057 xy-0.415747=0.

[0035] S24. Calculate the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitted curve, and filter out outlier points whose absolute error is greater than the error threshold.

[0036] Specifically, the absolute error can be obtained by calculating the distance between the point corresponding to the functional module in the Cartesian coordinate system and the fitted curve.

[0037] For example, the outlier selected is (x0, y0).

[0038] In this embodiment, the error threshold is set to 0.28.

[0039] like Figure 3 As shown, the absolute errors corresponding to functional modules 7, 8, and 21 are greater than the error threshold. Figure 2 The corresponding point in the rectangular coordinate system is an outlier.

[0040] S25. If the abnormal point is located above the fitted curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is normal; if the abnormal point is located below the fitted curve, it is determined that the repairable yield of the functional module corresponding to the abnormal point is abnormal.

[0041] Specifically, the x0 value of the selected outlier (x0, y0) can be substituted into the above fitting curve formula to calculate the y value. If the y value is less than y0, the outlier is deemed qualified and the repairable yield of the corresponding functional module is normal. If the y value is greater than y0, the outlier is deemed unqualified and the repairable yield of the corresponding functional module is abnormal.

[0042] like Figure 3 As shown, functional modules 7, 8, and 21 are in Figure 2 The corresponding point in the rectangular coordinate system shown is located below the fitted curve, indicating that the repairability yield of functional modules 7, 8, and 21 is abnormal.

[0043] The method for analyzing the repairable yield of chip functional modules provided in this invention can analyze the repairable yield of chip functional modules, screen out functional modules with abnormal repairable yield, and conduct in-depth analysis of functional modules with abnormal repairable yield, providing new analytical directions for yield improvement.

[0044] This invention also provides a device for analyzing the repairability yield of chip functional modules, such as... Figure 4 As shown, the device includes: The acquisition unit 11 is used to acquire the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​of each functional module for each functional module. The calculation unit 12 is used to calculate the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair. Fitting unit 13 is used to plot the corresponding points in a rectangular coordinate system with the design parameter values ​​on the horizontal axis and the repairable yield rate on the vertical axis for each functional module, and to perform linear fitting on the scatter plot composed of each point to obtain the fitting curve. The filtering unit 14 is used to calculate the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitted curve, and to filter out outlier points whose absolute error is greater than the error threshold. The judgment unit 15 is used to determine that the repairable yield of the functional module corresponding to the abnormal point is normal when the abnormal point is above the fitting curve; and to determine that the repairable yield of the functional module corresponding to the abnormal point is abnormal when the abnormal point is below the fitting curve.

[0045] The apparatus for analyzing the repairable yield of chip functional modules provided in this invention calculates the repairable yield of each functional module based on the total number of failed dies before and after repair. It then performs linear fitting on a scatter plot of points corresponding to each functional module in a Cartesian coordinate system with design parameter values ​​on the horizontal axis and repairable yield on the vertical axis to obtain a fitted curve. The absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve is calculated. Outliers with absolute errors greater than an error threshold are selected, and the positional relationship between the outlier and the fitted curve is used to determine whether the repairable yield of the corresponding functional module is abnormal. This allows for the analysis of the repairable yield of chip functional modules, identifying functional modules with abnormal repairable yields for in-depth analysis and providing new analytical directions for yield improvement.

[0046] Optionally, the calculation unit 12 is further configured to subtract the total number of failed grains after repair from the total number of failed grains before repair, and divide the difference by the total number of failed grains before repair to obtain the repairable yield.

[0047] Optionally, the filtering unit 14 is also used to calculate the distance between the point corresponding to the functional module in the rectangular coordinate system and the fitted curve to obtain the absolute error.

[0048] Optionally, the design parameter values ​​can be physical area, storage size, or number of transistors, but are not limited to these.

[0049] The apparatus in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be repeated here.

[0050] This invention also provides an electronic device, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above for improving the yield of the analysis chip functional modules.

[0051] This invention also provides a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the method for improving the yield of the analysis chip functional modules described above.

[0052] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for analyzing the repairability yield of chip functional modules, characterized in that, The method includes: Obtain the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​for each functional module; The repairable yield of each functional module is calculated based on the total number of failed dies before repair and the total number of failed dies after repair. For each functional module, plot the corresponding points in a Cartesian coordinate system with the design parameter values ​​on the horizontal axis and the repairable yield rate on the vertical axis. Perform linear fitting on the scatter plot composed of each point to obtain the fitting curve. Calculate the absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve, and filter out outliers whose absolute error is greater than the error threshold. If the anomaly is located above the fitted curve, the repairable yield of the functional module corresponding to the anomaly is determined to be normal; if the anomaly is located below the fitted curve, the repairable yield of the functional module corresponding to the anomaly is determined to be abnormal.

2. The method according to claim 1, characterized in that, The step of calculating the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair includes: subtracting the total number of failed dies after repair from the total number of failed dies before repair, and dividing the difference by the total number of failed dies before repair to obtain the repairable yield.

3. The method according to claim 1, characterized in that, The calculation of the absolute error between the point corresponding to each functional module in the Cartesian coordinate system and the fitted curve includes: calculating the distance between the point corresponding to the functional module in the Cartesian coordinate system and the fitted curve to obtain the absolute error.

4. The method according to any one of claims 1 to 3, characterized in that, The design parameters are physical area, storage size, or number of transistors.

5. A device for analyzing the repairability yield of chip functional modules, characterized in that, The device includes: The acquisition unit is used to acquire the total number of failed dies before repair, the total number of failed dies after repair, and the design parameter values ​​of each functional module for each functional module. The calculation unit is used to calculate the repairable yield of each functional module based on the total number of failed dies before repair and the total number of failed dies after repair. The fitting unit is used to plot the corresponding points in a rectangular coordinate system with the design parameter values ​​on the horizontal axis and the repairable yield rate on the vertical axis for each functional module, and to perform linear fitting on the scatter plot composed of each point to obtain the fitting curve. The filtering unit is used to calculate the absolute error between the point corresponding to each functional module in the rectangular coordinate system and the fitted curve, and to filter out outlier points whose absolute error is greater than the error threshold. The judgment unit is used to determine that the repairable yield of the functional module corresponding to the abnormal point is normal when the abnormal point is above the fitting curve, and to determine that the repairable yield of the functional module corresponding to the abnormal point is abnormal when the abnormal point is below the fitting curve.

6. The apparatus according to claim 5, characterized in that, The calculation unit is further configured to subtract the total number of failed grains after repair from the total number of failed grains before repair, and divide the difference by the total number of failed grains before repair to obtain the repairable yield.

7. The apparatus according to claim 5, characterized in that, The filtering unit is also used to calculate the distance between the point corresponding to the functional module in the rectangular coordinate system and the fitted curve to obtain the absolute error.

8. The apparatus according to any one of claims 5 to 7, characterized in that, The design parameters are physical area, storage size, or number of transistors.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 4.

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