A continuous resonator network computing method based on resistive memory arrays

Abstract

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductors, analog computing, and integrated circuits, and relates to a continuous resonator network computing circuit for ultradimensional computing applications. Specifically, it relates to a continuous feedback computing method based on resistive memory, including hardware implementation architecture, working principle, and design method. Background Technology

[0002] Hyperdimensional computing (HDC) is a brain-inspired vector symbolic architecture (VSA) model that uses high-dimensional hypervectors to represent various data tuples. It exhibits high robustness and scalability, and can process data in parallel, demonstrating higher computational power than traditional algorithms when dealing with large-scale information. Furthermore, compared to various traditional learning models, HDC's training process is achieved through single-pass operations on large amounts of data, providing a significant speed advantage. In recent years, it has been widely applied in machine learning, cognitive computing, and robotics, such as in text classification, biomedical signal processing, and multimodal sensor data fusion. However, its typical applications usually require hypervectors with a dimension of 10. 4 The above levels are to ensure the orthogonality requirements of the underlying algorithm. Therefore, the computational and memory resource overhead related to the retrieval, processing and manipulation of high-dimensional hypervectors cannot be ignored. In particular, when dealing with mixed signals, the problem of hypervector decomposition must be faced. The exponential computational complexity and storage overhead caused by the traversal method may directly offset the original advantages of the HDC algorithm.

[0003] Resonator network algorithms can effectively solve these problems. By constructing feedback loops and utilizing the orthogonality of the HDC algorithm itself, they can quickly converge to the correct solution in just a few dozen iterations. Furthermore, cross arrays based on resistive memory have been widely used to accelerate matrix-vector multiplication (MVM), thus providing a feasible method for accelerating resonator networks. Current solutions are limited to using resistive memory arrays to accelerate MVM operations in iterative algorithms. Operations such as nonlinear functions, input / output data conversion and transfer still require interaction with a digital computer system. This discrete iterative system does not fully utilize the advantages of analog computing and is severely limited by the computational speed of digital systems and the data transmission efficiency between systems, requiring improvement in latency, area, and power consumption. Therefore, it is essential to research a fast and efficient computational method for resonator networks. Compared to discrete iterative algorithms, continuous-time domain analog computation can reduce operational complexity and data conversion and transfer, thereby achieving hyperdimensional computation with low latency, low power consumption, and low hardware overhead. Summary of the Invention

[0004] The purpose of this invention is to develop a computational method for continuous resonator networks based on resistive memory arrays, which can greatly reduce the computational complexity and storage overhead of hypervector decomposition problems in hyperdimensional computation.

[0005] The technical solution provided by this invention is as follows:

[0006] A method for calculating a continuous resonator network based on a resistive memory array, comprising the following steps:

[0007] 1) Represented as ;in Hadama pile Equivalent to an XOR logic operation, this uses logic element circuits, taking the supervector s to be decomposed and the voltage signals corresponding to all h-1 variables (excluding itself) as inputs to achieve... Calculate and output the voltage signal;

[0008] 2) The voltage signal output in step 1) is sent to a resistive memory array for calculating matrix-matrix-vector multiplication. The resistive memory array is divided into upper and lower parts, and both parts store the codebook information X of each variable using analog conductance values. f For the upper part, the vector As the line voltage V, codebook information The simulated conductance value G is mapped onto the array, and the corresponding value is obtained in one step at the column line. The calculated current I is directly used as the column input for the lower half, thus obtaining the corresponding values ​​on the row lines of the lower half. The calculated current is converted into a current-to-voltage signal by adding an extra row of voltage divider resistors and grounding them;

[0009] 3) The voltage obtained in step 2) is compared using an operational amplifier to realize the sign function. and output The corresponding voltage signal is then fed back into the input of the logic element circuit to form a feedback loop. This loop iterates continuously until convergence, ultimately yielding a stable x. f That is, the decomposition result of the hypervector s.

[0010] Furthermore, for the n-dimensional hypervector decomposition problem involving h variables, the logic element circuit comprises h parallel sub-modules. Each sub-module contains n h-input XOR gates and n inverters. The hypervector to be decomposed, s, and h-1 variables (excluding itself) are used as the inputs to the h-input XOR gates. The outputs of the XOR gates and the inverted outputs processed by the inverters together constitute the output of the logic element section. The calculation results.

[0011] Furthermore, for the hypervector decomposition problem involving h variables, the resistive memory array comprises h parallel sub-modules, each sub-module containing... Memory array and Voltage divider resistors, where n×m f Given the supervector codebook size of each variable (f ∈ [1, h]), the voltage divider resistors are a series of (2n×1) storage devices.

[0012] Furthermore, for the n-dimensional hypervector decomposition problem containing h variables, the operational amplifier circuit contains h parallel sub-modules, each sub-module containing n operational amplifiers powered by a single power supply, whose positive and negative input terminals are sequentially connected to the 2n output rows of the lower half of the memory array, and the operational amplifiers compare the voltages input at both ends.

[0013] Furthermore, the resistive memory is a resistive switching memory, a phase-change memory, a magnetic memory, or a ferroelectric memory.

[0014] The beneficial effects of this invention are as follows:

[0015] This invention decomposes resonator network computation into three parts: logic computation, matrix-matrix-vector multiplication, and sign-based computation. It utilizes a feedback loop constructed by sequentially connecting logic elements, resistive memory arrays, and operational amplifiers for hardware implementation. The voltage corresponding to the supervector to be decomposed is used as input; after circuit stabilization, the voltage of the corresponding decomposed signal can be obtained at the output, thus realizing self-converging resonator network computation in the continuous-time domain. Compared with existing resonator network computation implementations, this invention fully leverages the performance advantages of analog computation, eliminating the need for discrete iteration and data transfer, thereby reducing hardware overhead and operational complexity, and achieving significant improvements in speed, energy efficiency, and area efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the algorithm for the continuous resonator network of this invention;

[0017] Figure 2 This is a schematic diagram of the calculation process of the continuous resonator network of the present invention;

[0018] Figure 3 This is a schematic diagram of the module connection and interaction of the continuous resonator network of the present invention;

[0019] Figure 4 This is a schematic diagram illustrating the specific working principle of the continuous calculation circuit of the present invention. Detailed Implementation

[0020] To more clearly illustrate the objectives, technical solutions, and advantages of this invention, a further detailed description is provided below in conjunction with the accompanying drawings. The description herein is merely illustrative and not intended to limit the scope of the invention.

[0021] Consider h variables Each variable is composed of several n-dimensional bipolar hypervectors. Composition, i.e., codebook Choose one hypervector from each codebook. The combination forms a supervector s, specifically represented as , where ⊙ represents the Hadamard product. Due to the orthogonal nature of the HDC underlying algorithm, the hypervector s can superimpose information from all variables without interference. In practical applications, the hypervector s corresponds to the mixed signal output from the front-end sensor or processor, which needs to be decomposed into categories corresponding to different variables (such as audio / image, etc.), that is, its corresponding number in the codebook of each variable is obtained through the hypervector s. If we use a traversal method to solve this problem, on the one hand, the computational complexity will increase exponentially with the number of variables h, and on the other hand, the overhead of storing all possible results will be unbearable.

[0022] Resonator networks are a superimposed feedback search algorithm for any variable. It can randomly generate initial solutions. Calculate using codebook The sign function is used to determine the confidence level of whether each element of the initial solution obtained after noise removal is a correct solution. This property can be preserved and better guesses can be generated. Repeated iterations This allows for rapid convergence to the correct solution. Furthermore, considering the orthogonality of the HDC algorithm, it is possible to utilize... Rewrite any variable as a superposition of other variables, such as (The same applies to other variables), allowing the iterative search process to proceed simultaneously across multiple variables. Ultimately, the resonator network algorithm can be described as follows:

[0023]

[0024]

[0025] Figure 1 It is an algorithm for continuous resonator network circuits, where each block / connection represents a storage / operation of a supervector level, i.e., containing n repetitive units or input / output paths.

[0026] Figure 2 This is the workflow of the continuous resonator network circuit of the present invention. First, the orthogonality of the HDC algorithm is utilized to... Represented as a superposition of other variables This enables simultaneous iterative search across multiple variables. Then, through continuous iteration... This process eliminates noise and allows the algorithm to converge to the correct solution. The two steps above are further decomposed into three parts: XOR logic, matrix-matrix-vector multiplication, and sign-based computation. These parts are connected end-to-end to form a feedback loop, thereby enabling one-step computation in the continuous time domain.

[0027] Figure 3 This invention relates to a continuous resonator network calculation method based on resistive memory arrays, the specific steps of which include:

[0028] 1) First calculate Hadama pile Considering that physical quantities such as voltage and conductance in the simulation calculations are all positive numbers, the {-1, 1} normal form in the original resonator network algorithm needs to be transformed into the {0, 1} normal form. At this point, the Hadamard product... This is equivalent to an XOR logic operation and can be directly implemented in hardware using XOR logic elements. Additionally, an inverter is added for inverted output to assist in the {0, 1} paradigm conversion of the subsequent resistive memory array section.

[0029] 2) Next, calculate matrix-matrix-vector multiplication. Acceleration is achieved using two resistive memory arrays, one above the other. For the upper part, the vector... As the line voltage V, codebook information X f Mapping the simulated conductance value G onto the array, we can use Kirchhoff's current law to know that: That is, the corresponding value can be obtained in one step along the column line. The calculated current I is then directly used as the column input for the lower half, thus obtaining the corresponding value in the row input of the lower half. The calculated current. In addition, an extra row of voltage divider resistors is added and grounded to achieve current-to-voltage signal conversion, which can then be used as the input to the subsequent operational amplifier section.

[0030] 3) Finally, calculate the sign function. This section is implemented using an operational amplifier powered by a single power supply. Essentially a voltage comparator, it outputs a high level ('1') if the voltage at the non-inverting input is higher than that at the inverting input, and a low level ('0') if the voltage at the non-inverting input is lower. The output voltage signals of each variable are directly used as inputs to all other modules except their own, creating a superimposed feedback loop.

[0031] Figure 4This is a schematic diagram illustrating the specific working principle of the calculation circuit, where the combination of 0 / 1 replaces the -1 / 1 representation in the original HDC algorithm. Specifically, a positive / inverting voltage input of 1 / 0 corresponds to 1 in the original algorithm, and a 0 / 1 input corresponds to -1; the same applies to the positive / inverting output. For codebook mapping, it utilizes... Figure 2 The 2×2 conductance matrix shown achieves the equivalent, that is Represents 1 in the original algorithm, Represents -1. In this equivalent case, the logic elements include XOR gates and NOT inverters, with each module taking h×n voltage signals as inputs and n positive and negative voltage signals as outputs; the resistive memory array section includes upper and lower 2n×2m... h Submodules will all include codebook information X f The analog conductance values ​​are mapped, and the two are naturally connected through column lines. The upper 2n row lines serve as input terminals, receiving n positive and negative voltage signal outputs from the logic element section. The lower 2n row lines output the MMVM calculation results as current to the voltage divider resistor and ground, thus converting them into voltage signals that can be input to the operational amplifier section. The operational amplifier, powered by a single power supply, compares the voltages at the positive and negative input terminals to realize the sign function. and output The corresponding voltage signal is then fed back into the input of the logic element circuit to form a feedback loop. This loop iterates rapidly in the continuous time domain until convergence, ultimately yielding a stable x. f That is, the decomposition result of the hypervector s.

[0032] The embodiments described above are not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A method for calculating a continuous resonator network based on a resistive memory array, comprising the following steps: 1) to be expressed as ; wherein the Hadamard product in is equivalent to an XOR logical operation, using a logic element circuit, to be decomposed into super-vectors and all voltage signals corresponding to variables other than itself as inputs, to realize computations and output voltage signals; 2) The voltage signal output in step 1) is sent to a resistive memory array for calculating matrix-matrix-vector multiplication. The resistive memory array is divided into upper and lower parts, and both parts store the codebook information of each variable using analog conductance values. For the upper part, the vector As line voltage Codebook information Using simulated conductivity values Mapping to the array, the corresponding column line is obtained in one step. The calculated current This current is directly used as the column line input for the lower half, thus obtaining the corresponding current on the row lines of the lower half. The calculated current is converted into a current-to-voltage signal by adding an extra row of voltage divider resistors and grounding them; 3) The voltage obtained in step 2) is compared using an operational amplifier to realize the sign function. and output The corresponding voltage signal is then fed back into the input of the logic element circuit to form a feedback loop. This loop iterates continuously until convergence, ultimately achieving a stable signal. That is, hypervector The decomposition results.

2. The method for calculating continuous resonator networks based on resistive memory arrays as described in claim 1, characterized in that, For including 1 variable The problem of 3D hypervector decomposition, wherein the logic element circuit includes Each of the parallel submodules contains [number] modules. indivual Input XOR gate and An inverter will decompose the hypervector into a single unit. With others besides oneself 1 variable as The input of the XOR gate, the output of the XOR gate, and the inverted output processed by the inverter together constitute the output of the logic element section. The calculation results.

3. The method for calculating continuous resonator networks based on resistive memory arrays as described in claim 1, characterized in that, For including The problem involves the hypervector decomposition of variables, and the resistive memory array circuit includes... Each of the parallel submodules contains [number] modules. Memory array and Voltage divider resistors, among which The size of the hypervector codebook for each variable .

4. The method for calculating continuous resonator networks based on resistive memory arrays as described in claim 1, characterized in that, For including 1 variable The problem of 3D hypervector decomposition, the operational amplifier circuit includes Each of the parallel submodules contains [number] modules. An operational amplifier powered by a single power supply has its positive and inverting inputs connected sequentially to the lower half of a resistive memory array. The operational amplifier has one output line and compares the voltages input at both ends.

5. The method for calculating continuous resonator networks based on resistive memory arrays as described in claim 1, characterized in that, The resistive memory is a resistive switching memory, a phase-change memory, a magnetic memory, or a ferroelectric memory.

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