Common mode calibration filter device and parameter optimization method thereof

Abstract

The present application relates to the technical field of analog integrated circuit design, and provides a common-mode calibration filtering device and a parameter optimization method thereof, the common-mode calibration filtering device comprising at least one filtering channel, each filtering channel comprising: a filter core module, an adjustable resistance array, and a digital common-mode calibration module; the filter core module has a direct current working path, and the direct current working path has a common-mode node; the input end of the digital common-mode calibration module is connected to the common-mode node, the digital common-mode calibration module is used for comparing the common-mode voltage on the common-mode node with a reference voltage, and generating a digital control signal according to the comparison result; the adjustable resistance array is connected to the direct current working path of the filter core module; the control end of the adjustable resistance array is used for receiving the digital control signal, and adjusting the equivalent resistance value of the adjustable resistance array according to the digital control signal, so as to change the direct current flowing through the direct current working path, and then correct the common-mode voltage.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, and in particular to a common-mode calibration filter device and its parameter optimization method. Background Technology

[0002] In related technologies, the stability of the output common-mode voltage directly determines the dynamic range and linearity of the signal in high-performance filter design. However, traditional solutions rely on high-precision matching of differential pairs and current mirrors to maintain common-mode balance, but device mismatch is severe under advanced processes. To eliminate residual errors, large-size devices or expensive laser trimming processes are often required. This not only increases area and cost but also cannot compensate for new mismatches caused by chip aging or stress changes, thus limiting manufacturing yield.

[0003] Secondly, existing common-mode feedback systems mostly use fixed resistor voltage dividers or reference sources, resulting in fixed feedback parameters. When faced with wide temperature ranges or process angle variations, circuit parameter drift can cause the common-mode voltage to deviate from the optimal operating point, leading to signal clipping and nonlinear distortion. Furthermore, traditional analog loops cannot reconstruct the DC path in real time for compensation.

[0004] Finally, traditional analog domain modulation is difficult to achieve high-resolution micro-step correction, is susceptible to noise interference and has the risk of overshoot, and is difficult to integrate complex digital calibration logic, thus failing to meet the flexible and precise control requirements of common-mode level in multiple modes.

[0005] Therefore, there is an urgent need for a common-mode calibration filter device and its parameter optimization method to improve the above problems. Summary of the Invention

[0006] This invention provides a common-mode calibration filter device and its parameter optimization method. This invention is used to reconstruct the DC feedback path through an adjustable resistor array to flexibly adapt to the common-mode voltage requirements at different process angles and temperatures, thereby improving the linearity and consistency of the filter.

[0007] According to a first aspect of the present invention, a common-mode calibration filter device is provided, the common-mode calibration filter device including at least one filter channel, each filter channel including: a filter core module, an adjustable resistor array, and a digital common-mode calibration module; the filter core module has a DC operating path, on which a common-mode node is provided; the input terminal of the digital common-mode calibration module is connected to the common-mode node, the digital common-mode calibration module is used to compare the common-mode voltage on the common-mode node with a reference voltage, and generate a digital control signal based on the comparison result; the adjustable resistor array is connected to the DC operating path of the filter core module; the control terminal of the adjustable resistor array is used to receive the digital control signal, and adjust the equivalent resistance value of the adjustable resistor array according to the digital control signal, so as to change the DC current flowing through the DC operating path, thereby correcting the common-mode voltage.

[0008] In one embodiment, the core module of the filter is a third-order active low-pass filter; the third-order active low-pass filter includes a Sallen & Key second-order low-pass filter, a unity-gain buffer, and a first-order filter; the output of the Sallen & Key second-order low-pass filter is connected to the input of the unity-gain buffer, and the output of the unity-gain buffer is connected to the input of the first-order filter; the unity-gain buffer is used to isolate the Sallen & Key second-order low-pass filter and the first-order filter to eliminate load effects.

[0009] In one embodiment, the Salen-Kay second-order low-pass filter employs a fully differential structure, internally integrating a signal input terminal, an input RC network, a source follower buffer, and a feedback capacitor network connected in sequence. The signal input terminal is used to acquire the input differential signal. The input RC network is connected between the signal input terminal and the input terminal of the source follower buffer, serving as the passive network foundation for the second-order low-pass filtering characteristics and coupling the input differential signal to the source follower buffer. The output terminal of the source follower buffer serves as the signal output terminal of the Salen-Kay second-order low-pass filter and provides low output impedance to drive subsequent circuits. The output terminal of the source follower buffer is connected to the input RC network through the feedback capacitor network, coupling the output signal of the source follower buffer to the input RC network to form a frequency compensation path, thereby enabling the input RC network to exhibit second-order low-pass filtering characteristics for the input differential signal.

[0010] In one embodiment, the input RC network includes: a first capacitor element, a second capacitor element, a first resistor element, and a second resistor element; the first resistor element and the second resistor element are connected in series between the signal input terminal of the Salen-Kay second-order low-pass filter and the input terminal of the source follower buffer; one end of the first capacitor element is connected to the intermediate node between the first resistor element and the second resistor element, and the other end of the first capacitor element is connected to the output terminal of the source follower buffer; the second capacitor element is connected between the two input terminals of the source follower buffer.

[0011] In one embodiment, the source follower buffer includes: a buffer core, a third resistive element, a fourth resistive element, a first diode, and a second diode; the input terminal of the buffer core is connected to the output terminal of the Salen-Kay second-order low-pass filter; the third resistive element is connected between the power supply voltage terminal and the first output terminal of the buffer core; the fourth resistive element is connected between the power supply voltage terminal and the second output terminal of the buffer core; the first diode and the second diode are connected in anti-parallel between the first output terminal and the second output terminal of the buffer core.

[0012] In one embodiment, the first-order filter includes a fifth resistive element and a third capacitive element; the fifth resistive element is connected between the signal input terminal and the output terminal of the first-order filter; the third capacitive element is connected between the output terminal of the first-order filter and ground; the first-order filter and the Salen-Kai second-order low-pass filter are cascaded through a unity-gain buffer to jointly form a third-order low-pass filter response with three poles, so as to further attenuate high-frequency noise and improve stopband rejection capability.

[0013] In one embodiment, the digital control signal includes a multi-bit tuning control word; the common-mode calibration filter further includes a signal buffer drive circuit, the input of which is connected to the digital common-mode calibration module to receive the tuning control word, and the output of which is connected to the control terminal of the adjustable resistor array; the signal buffer drive circuit includes at least two series-connected inverters, the tuning control word is converted into an internal tuning word after passing through at least two series-connected inverters, and the logic level of the internal tuning word is in phase with that of the tuning control word; the internal tuning word is used to control the resistance value of the adjustable resistor array.

[0014] In one embodiment, the common-mode calibration filter further includes: a cascaded level shifter and a common-mode decoder; the input of the level shifter is coupled to an external digital control signal source for receiving a multi-bit common-mode control word and shifting the logic level of the common-mode control word upwards; the output of the level shifter is directly coupled to the input of the common-mode decoder to transmit the logic-level-shifted common-mode control word to the common-mode decoder for decoding, thereby generating multiple pairs of complementary decoding control signals; the output of the common-mode decoder is directly coupled to the control input of the digital common-mode calibration module for transmitting the multiple pairs of complementary decoding control signals. A code control signal is applied to the digital common-mode calibration module; the digital common-mode calibration module includes multiple parallel-connected adjustment branches, each of which contains a controlled switching device. The control terminal of the controlled switching device is used to receive a corresponding pair of multiple complementary decoding control signals to turn on or off the corresponding adjustment branch; the current path terminals of the multiple parallel-connected adjustment branches are coupled to the output terminal of the third-order active low-pass filter, which is used to generate an adjustment current by turning on different numbers of adjustment branches and injecting it into the output terminal of the third-order active low-pass filter, thereby adjusting the output common-mode voltage of the third-order active low-pass filter.

[0015] In one embodiment, the third-order active low-pass filter further includes a baseband filter common-mode feedback circuit; the output of the baseband filter common-mode feedback circuit is connected to the bias control terminal of the source follower buffer, the baseband filter common-mode feedback circuit is used to detect the voltage of the common-mode node and generate a common-mode feedback adjustment signal, the common-mode feedback adjustment signal is used to adjust the quiescent operating current of the source follower buffer to stabilize the common-mode voltage; the output of the digital common-mode calibration module is connected to the control terminal of the unity-gain buffer, the digital common-mode calibration module is used to generate a digital adjustment current to calibrate the initial voltage of the common-mode node, and the baseband filter common-mode feedback circuit maintains the common-mode voltage in a dynamically stable state.

[0016] In one embodiment, the source follower buffer includes a differential input pair, a differential load circuit, and an impedance feedback network. The differential input pair includes a first input transistor and a second input transistor, with the source of the first input transistor forming a third output terminal and the source of the second input transistor forming a fourth output terminal. The impedance feedback network includes a first feedback branch and a second feedback branch. The first feedback branch includes a first compensation capacitor and a first feedback transistor connected in series. One end of the first compensation capacitor is connected to the third output terminal, and the other end of the first compensation capacitor is connected to the control terminal of the first feedback transistor. The first end of the first feedback transistor is connected to the control terminal of the load transistor corresponding to the third output terminal in the differential load circuit. The second end of the first feedback transistor is connected to a reference ground. The second feedback branch includes a second compensation capacitor and a second feedback transistor connected in series. One end of the second compensation capacitor is connected to the fourth output terminal, and the other end of the second compensation capacitor is connected to the control terminal of the second feedback transistor. The first end of the second feedback transistor is connected to the control terminal of the load transistor corresponding to the fourth output terminal in the differential load circuit. The second end of the second feedback transistor is connected to a reference ground. The impedance feedback network is configured to reduce the output impedance of the source follower buffer, and the first compensation capacitor and the second compensation capacitor are used to maintain the stability of the impedance feedback network.

[0017] According to a second aspect of the present invention, a parameter optimization method for a common-mode calibration filter is provided, for optimizing the common-mode calibration filter of any one of the first aspects, the parameter optimization method comprising: A candidate set containing various filter circuit topologies is constructed, and multi-dimensional performance simulation data of each topology in the candidate set under preset operating conditions are obtained. The multi-dimensional performance simulation data is evaluated using a machine learning model, and the target filter topology is automatically determined from the candidate set based on preset comprehensive performance indicators including common-mode rejection ratio and differential-mode to common-mode conversion gain. Based on the determined target filter topology, a search space for circuit element parameters is defined, and multiple sets of parameter combinations that satisfy the target frequency response are generated. Multi-dimensional performance simulations are performed on the multiple sets of parameter combinations, and at least two of the following are used as optimization objectives: bandwidth stability, noise performance, linearity, and chip area. The nominal parameter values ​​of the circuit elements are determined through a multi-objective optimization algorithm. Analyze the impact range of actual manufacturing process deviations on common-mode bandwidth, and determine the circuit structure and parameters of the adjustable resistor array including switchable branches based on the nominal parameter values; according to the impact range and nominal parameter values, plan the resistance range distribution and digital control mapping strategy of the adjustable resistor array. During actual operation or calibration, based on the digital control mapping strategy, the deviation between the measured common-mode bandwidth and the target common-mode bandwidth is converted into a digital control signal, and the equivalent resistance value of the adjustable resistor array is dynamically adjusted to compensate for the common-mode frequency drift caused by process deviation, thereby converging the actual common-mode bandwidth of the common-mode calibration filter device to the target common-mode bandwidth range.

[0018] In one implementation, the candidate set includes a traditional second-order Salem-Kai filter with resistor-capacitor real pole topology, a multi-feedback filter topology with additional real poles, and topology variants with different pole allocation methods or different cascade orders. Multidimensional performance simulation data is acquired, including: for each topology, designing a matching capacitor value within a given resistance range based on the target cutoff function, and performing AC characteristics, noise characteristics, and stability simulations under multiple process-voltage-temperature combinations to extract noise spectral density, linearity index, phase margin, pole distribution, and the required total capacitor area. Evaluation is performed using a machine learning model, including: using the relationship between noise and capacitance as the core analysis dimension, and comprehensively considering multiple indicators including linearity, stability, and pole distribution to construct a comprehensive evaluation system; using artificial intelligence or machine learning methods to model the input data including topology category, resistor-capacitor ratio, and pole configuration method, outputting comprehensive indicators of noise, linearity, stability, and area; prioritizing minimizing the total capacitor area while meeting low noise requirements, and using linearity and stability requirements as constraints, performing multi-objective automatic screening to determine the target filter topology with optimal comprehensive performance.

[0019] In one implementation, generating multiple sets of parameter combinations that satisfy the target frequency response and determining nominal parameter values ​​includes: defining the value range of resistors and capacitors based on the determined target filter topology, combined with process design rules and area constraints; automatically generating resistor-capacitor parameter combinations that conform to the characteristics of the target transfer function within the value range, and distributing the nominal cutoff frequencies corresponding to each parameter combination within a preset frequency band centered on the target frequency; and performing multi-dimensional performance simulations on multiple sets of parameter combinations, including: performing AC simulation, noise simulation, linearity simulation, and stability analysis under multiple process-voltage-temperature combination conditions. Analysis is performed to obtain multi-dimensional simulation data including bandwidth, group delay, integral noise within the target frequency band, second and third harmonic intercept points, and phase margin. Nominal parameter values ​​are determined through a multi-objective optimization algorithm, including: calculating the bandwidth fluctuation range and robustness measures of each index based on the multi-dimensional simulation data; constructing a multi-objective function including nominal bandwidth fit, bandwidth operating condition fluctuation rate, integral noise, harmonic intercept point, phase margin, and total capacitor area; and using the Pareto front optimization algorithm to output several non-dominated optimal solution sets, from which a set of resistor-capacitor parameters that balances performance robustness and area efficiency is selected as the nominal parameter values.

[0020] In one implementation, the planning of the resistance range distribution and digital control mapping strategy for the adjustable resistor array includes: determining the error coverage range of the nominal parameter values ​​based on the statistical deviation range of resistors and capacitors in the actual manufacturing process; constructing an adjustable resistor array or adjustable capacitor array with discrete adjustment step sizes based on the nominal parameter values, wherein the accuracy of the discrete adjustment step size is set to be less than or equal to half of the statistical deviation range to ensure that the adjustment resolution is sufficient to compensate for process fluctuations; calculating the required number and distribution pattern of resistance ranges in combination with the error coverage range and the preset frequency calibration accuracy requirements, and determining the corresponding number of digital control code bits; and establishing a mapping relationship between the digital control code and the resistance ranges to compensate for the initial frequency offset caused by process deviations to the range allowed by the frequency calibration accuracy requirements using the mapping relationship.

[0021] In one implementation, the deviation between the measured common-mode bandwidth and the target common-mode bandwidth is converted into a digital control signal. This includes: injecting a test excitation signal into the input of the common-mode calibration filter in chip initialization or calibration mode, and monitoring the frequency response characteristics of the output to obtain the measured bandwidth; calculating the difference between the measured bandwidth and the target bandwidth; if the difference exceeds a preset frequency tolerance range, reading a pre-stored digital control mapping strategy from the on-chip non-volatile memory to determine the direction and step size of the resistance adjustment; updating the digital control code according to the direction and step size, switching the switchable branch state in the adjustable resistor array, dynamically changing the equivalent time constant of the common-mode calibration filter until the measured bandwidth falls within the range allowed by the frequency calibration accuracy requirements, and saving the finally locked digital control code as the working configuration.

[0022] Compared with existing technologies, the advantages of this invention are as follows: This invention directly achieves dynamic stability of the operating point and precise compensation for process errors through closed-loop linkage of the filter core module, adjustable resistor array, and digital common-mode calibration module. The digital calibration module monitors the output common-mode level in real time and compares it with a reference value. Once it detects bias drift caused by process deviations or temperature changes, it immediately generates a control signal to drive the adjustable resistor array to change its impedance state. This physical resistance fine-tuning directly reconstructs the DC feedback network of the circuit, forcing the common-mode voltage to quickly return to the optimal linear range, thereby effectively avoiding signal dynamic range compression and nonlinear distortion caused by common-mode voltage deviation.

[0023] Simultaneously, by leveraging the high-resolution discrete adjustment characteristics of the adjustable resistor array, this invention transforms uncontrollable random analog errors into a precisely quantifiable digital control process. The system can finely correct impedance deviations in minute steps, significantly reducing the stringent dependence on the initial physical matching of devices. This allows the chip to automatically converge to the optimal operating point at different process corners, improving manufacturing yield and the circuit's environmental adaptability. Ultimately, this adaptive mechanism ensures that the filter maintains a stable DC operating point and high linearity throughout its entire lifespan without external intervention, effectively overcoming the stringent limitations of high-performance analog circuits on device physical matching with compact digital logic overhead. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a common-mode calibration filter device according to an exemplary embodiment.

[0025] Figure 2 This is a schematic diagram of an adjustable resistor array according to an exemplary embodiment.

[0026] Figure 3 This is a schematic diagram of a reference voltage generation circuit according to another exemplary embodiment.

[0027] Figure 4 This is a schematic diagram of a comparator circuit according to an exemplary embodiment.

[0028] Figure 5 This is a schematic diagram of the structure of a filter core module according to another exemplary embodiment.

[0029] Figure 6 This is a schematic diagram of a buffer drive link structure according to another exemplary embodiment.

[0030] Figure 7 This is a schematic diagram illustrating a cascaded structure of a level shifter and a common-mode decoder according to an exemplary embodiment.

[0031] Figure 8 This is a schematic diagram of the structure of a common-mode feedback circuit for a baseband filter according to another exemplary embodiment.

[0032] Figure 9 This is a schematic diagram of the structure of a digitally programmable current source array according to an exemplary embodiment.

[0033] Figure 10 This is a schematic diagram of a source follower buffer according to an exemplary embodiment.

[0034] Figure 11 This is a schematic diagram of the dynamic response characteristics of an adaptive bandwidth calibration process according to an exemplary embodiment, showing a simulated waveform.

[0035] Figure 12 This is a flowchart illustrating a parameter optimization method for a common-mode calibration filter device according to an exemplary embodiment.

[0036] Figure 13 This is a schematic diagram of a mixed-signal adaptive common-mode calibration circuit according to an exemplary embodiment.

[0037] Explanation of the reference numerals in the figure: 1. Filter core module; 2. Adjustable resistor array; 3. Digital common-mode calibration module; 11. Salen-Kai second-order low-pass filter; 12. Unity-gain buffer; 13. First-order filter. Detailed Implementation

[0038] Unless otherwise defined, the technical or scientific terms used in this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0039] like Figure 1As shown, the first embodiment of the present invention provides a common-mode calibration filter device, which includes at least one filter channel. Each filter channel includes: a filter core module 1, an adjustable resistor array 2, and a digital common-mode calibration module 3. The filter core module 1 has a DC operating path with a common-mode node on the DC operating path. The input terminal of the digital common-mode calibration module 3 is connected to the common-mode node. The digital common-mode calibration module 3 is used to compare the common-mode voltage on the common-mode node with a reference voltage and generate a digital control signal based on the comparison result. The adjustable resistor array 2 is connected to the DC operating path of the filter core module 1. The control terminal of the adjustable resistor array 2 is used to receive the digital control signal and adjust the equivalent resistance value of the adjustable resistor array 2 according to the digital control signal to change the DC current flowing through the DC operating path, thereby correcting the common-mode voltage.

[0040] In some specific embodiments, such as Figure 2 As shown, an adjustable resistor array 2 for dynamic tuning of filter bandwidth is used. By precisely switching the resistor units in the parallel branches through digital control signals, the equivalent resistance value can be continuously or steppedly adjusted. This adjustable resistor array 2 consists of multiple vertically parallel tuning branches, each containing a combination of a controlled switching network and a series resistor. For example, the leftmost branch is TUNE... <2> With iTUNE <2> The signals jointly control the CMOS transmission gate composed of MN0 and MP3. When it is turned on, the series branch of R0 and R1-R2 is connected to the main current path. The middle branch, composed of MN8 and MP6, forms a switch-like structure to control the on / off state of the series path of R3-R6. The right branch controls the connection state of the long series resistor R7-R14 through MN9 and MP7. The top of all branches is connected to node B, and the bottom is connected to node A, i.e., connected to the reference ground VSS, forming multiple selectable current paths from B to A. Among them, iTUNE <2> As an internally tuned word with buffering and timing optimization, it ensures synchronized and glitch-free switching actions; while TUNE <2> These are the original external control bits, working together to achieve reliable level shifting and enhanced drive capability. The resistance values ​​in each branch are configured with binary weights or linear gradients, such as R0 being the smallest and R14 the largest, causing the total equivalent resistance to change non-linearly or linearly with the number of active branches. This allows for precise control of the RC time constant, ultimately achieving digitally programmable tuning of the filter cutoff frequency f_c = 1 / (2πRC). This architecture is particularly suitable for baseband filtering systems requiring high resolution, low noise, and fast response, such as wireless receiver channel selection or adaptive equalizer scenarios.

[0041] like Figure 3As shown, in one specific embodiment, the reference voltage generation circuit adopts an architecture combining a current mirror and a programmable resistor network, aiming to provide a set of high-precision, dynamically configurable reference levels for the common-mode feedback system to support the precise stabilization of the filter output common-mode voltage to a target value, such as 400mV. The left side of this circuit consists of a startup and enable unit composed of MN6 to MN13 driven by a bias current source IRESU: when the enable signal iiEN is high and iEN is low, MN11 is turned on and pulls the gate of MN27 low to turn it off. Simultaneously, MP9 is activated by the EN_CMP signal to open the main current mirror branch; otherwise, the entire module is turned off to reduce static power consumption. MP29 and MP5 constitute a Cascode current mirror to ensure the stability of the mirrored current, and MP0, as the output stage PMOS transistor, provides a constant reference current $I_{ref}$ to the top of the resistor network on the right side. The right side of the circuit is the core voltage generation region, containing a multi-stage series resistor chain consisting of R6, R5, R3, R7, and R4, and topology reconstruction is performed through eight sets of bidirectional analog switches SW0–SW7; these switches are controlled by the complementary digital signal cmp_I. <1> / icmp_I <1> and cmp_Q <1> / icmp_Q <1> It can achieve two states: "straight-through" or "cross-through," thus flexibly selecting the current flow path and voltage divider nodes. For example, when cmp_I <1> When =1, SW0 closes and guides the current to the Vthh_I node through R6. SW2 / SW3 and SW4 / SW5 further control whether the intermediate tap is connected to the lower end of R5 or led out from the upper end of R3. With the switching of the connection mode of R7 / R4 to the reference ground by the bottom SW6 / SW7, different voltage division ratios can be generated at the Vthh_I and Vthh_Q nodes, thereby obtaining multiple discrete reference voltage values ​​from about 350mV to 450mV. In addition, the global bias signal cmpbias<3:0> is used to fine-tune the gate voltage of the MP11 array to adjust the total drain current of MP0, thus achieving coarse adjustment. nbias assists in setting the bias point of MN28 to stabilize the tail current. The finally generated Vthh_I and Vthh_Q are used as common-mode reference inputs for the in-phase and positive-mode channels, respectively. They are fed into the BBFILT_CMFB comparator and compared differentially with the measured common-mode voltage cmp / cmn. The resulting error signal then drives the aforementioned programmable current source array to perform closed-loop calibration, ensuring that the system can maintain excellent common-mode accuracy under PVT changes.

[0042] like Figure 4As shown, in one specific embodiment, the comparator circuit adopts a high-gain differential input single-ended output architecture, specifically designed for high-speed and accurate comparison of the sampled real-time common-mode voltage with preset upper and lower reference voltages. The core of this circuit consists of a differential input pair composed of PMOS transistors MP22 and MP24, whose gates receive the analog signals to be compared. Their sources are connected to a cross-coupled tail current structure composed of NMOS transistors MN1 and MN12. This structure not only provides bias current but also accelerates the switching process through a positive feedback mechanism. When a small voltage difference occurs at the input, an avalanche response is triggered, rapidly pushing the internal node potential to its limit. The output stage is driven by a push-pull inverter composed of PMOS transistors MP10 and MP3 and NMOS transistors MN7 and MN4, ensuring that the final output has sufficient driving capability and a complete logic swing, allowing direct input to subsequent digital calibration logic. The circuit's operating state is strictly controlled by the enable signals EN and iEN. When EN is high and iEN is low, the left-side NMOS transistor MN8 is turned on to activate the tail current path, while the top PMOS transistor MP0 is turned on to power the upper load, allowing the comparator to enter normal operating mode. Conversely, the main current path is shut down to significantly reduce static power consumption. Furthermore, the internal bias node ib can be used to fine-tune the tail current to optimize the trade-off between speed and power consumption, while the power supply VDD and ground VSS provide a stable operating voltage for the entire circuit. With this dynamic latch structure, the comparator possesses self-regenerative characteristics, enabling decision-making within nanoseconds and effectively suppressing common-mode interference and offset voltage. As the core sensing element in the common-mode feedback system, it continuously monitors the filter output level and immediately triggers correction when a deviation from the target value is detected, thereby achieving adaptive closed-loop common-mode stability control.

[0043] In one embodiment, the filter core module 1 is a third-order active low-pass filter; the third-order active low-pass filter includes a Salen-Kay second-order low-pass filter 11, a unity-gain buffer 12, and a first-order filter 13; the output terminal of the Salen-Kay second-order low-pass filter 11 is connected to the input terminal of the unity-gain buffer 12, and the output terminal of the unity-gain buffer is connected to the input terminal of the first-order filter; the unity-gain buffer is used to isolate the Salen-Kay second-order low-pass filter and the first-order filter to eliminate load effects, and is used to suppress high-frequency noise and improve the correction accuracy of common-mode voltage.

[0044] like Figure 5As shown, in one specific embodiment, the core filter module 1 is a third-order active low-pass filter, whose circuit architecture consists of a Salen-Kai second-order low-pass filter 11, a unity-gain buffer 12, and a first-order RC filter cascaded sequentially. The signal flow is as follows: the input signal first enters the Salen-Kai second-order low-pass filter 11 for preliminary filtering. This stage of the circuit generates a pair of conjugate complex poles through a specific feedback network of resistors and capacitors, forming the main amplitude-frequency roll-off of the filter. Subsequently, the signal after second-order filtering enters the unity-gain buffer 12. This buffer plays a crucial role in impedance isolation in the circuit. Its high input impedance characteristic avoids the load effect on the quality factor of the preceding Salen-Kai second-order low-pass filter, preventing pole shift and frequency response peaking. At the same time, its low output impedance characteristic can strongly drive the subsequent load. Immediately afterwards, the buffered signal is connected in series to the first-order filter 13, which is composed of resistors and capacitors. This stage of the circuit generates a real pole. Through this cascaded approach, the complex poles generated by the Salen-Kay second-order low-pass filter and the real poles generated by the first-order network are superimposed in the frequency domain, jointly constructing a third-order Butterworth low-pass frequency response curve with a steep roll-off characteristic. This design not only effectively suppresses high-frequency switching noise and clock feedthrough interference, significantly improving the signal-to-noise ratio of the output signal, but also provides a clean and stable DC or low-frequency component for subsequent common-mode voltage detection, thereby eliminating the impact of high-frequency ripple on common-mode detection accuracy and ensuring that the mixed-signal common-mode calibration circuit can accurately lock the common-mode voltage within the target range.

[0045] In one embodiment, the Salen-Kay second-order low-pass filter 11 employs a fully differential structure, internally integrating a signal input terminal, an input RC network, a source follower buffer, and a feedback capacitor network connected in sequence. The signal input terminal is used to acquire the input differential signal. The input RC network is connected between the signal input terminal and the input terminal of the source follower buffer, serving as the passive network foundation for the second-order low-pass filtering characteristics and coupling the input differential signal to the source follower buffer. The output terminal of the source follower buffer serves as the signal output terminal of the Salen-Kay second-order low-pass filter 11, providing low output impedance to drive subsequent circuitry. The output terminal of the source follower buffer is connected to the input RC network via the feedback capacitor network, coupling the output signal of the source follower buffer to the input RC network to form a frequency compensation path, thereby enabling the input RC network to exhibit second-order low-pass filtering characteristics for the input differential signal. At least one of the resistive element in the input RC network and the capacitive element in the feedback capacitor network is an adjustable element to match the frequency response of the digital common-mode calibration module 3.

[0046] like Figure 5As shown, in one specific embodiment, the filter core module 1 adopts a fully differential architecture to achieve excellent common-mode rejection performance. Its circuit structure specifically includes a Salen-Kay second-order low-pass filter 11, a unity-gain buffer 12, and a first-order RC low-pass filter cascaded in sequence. First, the input differential signal VINP / VINN enters the Salen-Kay second-order low-pass filter 11. This stage of the circuit consists of an input RC network, a source follower buffer BBFILT_SF, and a feedback capacitor network. The input RC network, as the basis for passive filtering, couples the signal to the input of the source follower buffer. The feedback capacitor network, such as C1 and C2, is connected between the output of the source follower buffer and the intermediate node of the input RC network. By introducing a positive feedback path, a frequency compensation mechanism is constructed, thereby enabling the entire front-end circuit to exhibit standard second-order low-pass filtering characteristics. To adapt to different process angles or operating frequencies, the resistors in the input RC network, such as R1, R2, R4, and R5, and the capacitors in the feedback capacitor network are configured as adjustable components. These components are controlled by digital control signals such as iTUNE, which can dynamically adjust the resistance or capacitance values ​​to accurately match and correct the cutoff frequency and frequency response of the filter. Subsequently, the signal after second-order filtering is transmitted to the subsequent circuit, which includes a unity-gain buffer 12 and a first-order RC low-pass filter composed of resistor R12 and capacitor C0 connected in series. The unity-gain buffer 12 plays a crucial role in impedance isolation here. Utilizing its high input impedance and low output impedance characteristics, it effectively eliminates the load effect of the subsequent RC network on the quality factor of the preceding second-order filter, ensuring the stability of the complex pole positions. Finally, a real pole is superimposed on the first-order RC network in the frequency domain, which, together with the two complex poles of the preceding stage, synthesizes a third-order low-pass frequency response with a steep roll-off characteristic. Ultimately, a clean and stable common-mode voltage vcm is extracted from across capacitor C0 for subsequent high-precision common-mode calibration.

[0047] like Figure 5As shown, in some examples, the differential inputs INP and INN of the first-stage source follower buffer BBFILT_SF are coupled to an RC filter node consisting of adjustable resistors R2 and R5 and a fixed capacitor C5, respectively. These are further connected in parallel to the upper ends of two sets of 8-bit digitally controllable capacitor arrays C1 and C2, with their lower ends uniformly connected to the reference ground VSS. This allows for dynamic adjustment of the equivalent capacitance to ground of the node via digital code to calibrate the filter cutoff frequency. The differential outputs OUTP and OUTN of this stage directly drive the corresponding inputs INP and INN of the subsequent buffer module BBFILT_BUF, while simultaneously being connected via adjustable pull-down resistors. Resistors R3 and R6 are connected to ground potential to set the DC operating point, and the output signal is fed back to the common-mode control nodes cmpdn and cmmdn through a small-capacity controllable capacitor C6 to form a stable common-mode loop. After receiving the signal from the previous stage, the differential output terminals VOUTP and VOUTN of the second-stage buffer module are not only biased to the power rail through pull-up / pull-down resistors R10 and R11 to establish the output common-mode level, but also provide overvoltage protection through clamping diodes D0 / ID1. Finally, a stable common-mode voltage Vcm is extracted through a low-pass network composed of resistor R12 and capacitor C0, realizing a complete signal chain processing from high-precision filtering to strong driving capability.

[0048] In one embodiment, the input RC network includes: a first capacitor element, a second capacitor element, a first resistor element, and a second resistor element; the first resistor element and the second resistor element are connected in series between the signal input terminal of the Salen-Kay second-order low-pass filter 11 and the input terminal of the source follower buffer; one end of the first capacitor element is connected to the intermediate node between the first resistor element and the second resistor element, and the other end of the first capacitor element is connected to the output terminal of the source follower buffer; the second capacitor element is connected between the two input terminals of the source follower buffer.

[0049] like Figure 5As shown, in one specific embodiment, the input RC network of the Salen-Kay second-order low-pass filter 11 is specifically composed of a first resistor element, a second resistor element, a first capacitor element, and a second capacitor element. The number of the first resistor element, the second resistor element, and the first capacitor element is two each. The first resistor elements R1 / R4 and the second resistor elements R2 / R5 are connected in series, and the two second resistor elements R2 and R5 are respectively connected to the two input terminals INP and INN of the source follower buffer BBFILT_SF. One end of the first capacitor element C1 / C2 is connected to the intermediate node between the first and second resistor elements, and the other end is connected to the output terminal OUTP / OUTN of the source follower buffer BBFILT_SF. The source follower buffer BBFILT_SF is also connected to the first channel positive-phase side stable bias node stb1a and the first channel anti-phase side stable bias node stb1b. The second capacitor element C5 is connected between the two input terminals INP and INN of the source follower buffer BBFILT_SF. By coupling the output signal of the source follower buffer BBFILT_SF to the node between the first and second resistor elements, a positive feedback loop is formed, thereby changing the pole distribution of the network and making the entire input RC network, together with the source follower buffer, exhibit second-order low-pass filtering characteristics.

[0050] In some examples, the second capacitor element is configured to connect between the intermediate node between the second resistor element and the input of the source follower buffer and the reference ground. Specifically, this second capacitor element manifests as two adjustable capacitor arrays driven by digital control signals C1<7:0> and C2<7:0>, or equivalently as the parasitic capacitance at the buffer input. C1<7:0> and C2<7:0>, as 8-bit digital control codes, precisely regulate the on / off state of the switching units in the corresponding capacitor array through binary weighting, thereby continuously fine-tuning the equivalent capacitance to ground value of that node. This digital adjustment mechanism can dynamically compensate for capacitance fluctuations caused by process variations, and, in conjunction with the second resistor element, precisely set the time constant of the filter network, ultimately achieving automated calibration and performance optimization of the filter's frequency response, ensuring that the measured bandwidth strictly falls within the preset accuracy tolerance range.

[0051] In one embodiment, the source follower buffer includes: a buffer core, a third resistor element, a fourth resistor element, a first diode, and a second diode; the input terminal of the buffer core is connected to the output terminal of the Salen-Kay second-order low-pass filter 11; the third resistor element is connected between the power supply voltage terminal and the first output terminal of the buffer core; the fourth resistor element is connected between the power supply voltage terminal and the second output terminal of the buffer core; the first diode and the second diode are connected in anti-parallel between the first output terminal and the second output terminal of the buffer core.

[0052] In one specific embodiment, the source follower buffer includes a buffer core BBFILT_BUF, a third resistor R10, a fourth resistor R11, a first diode D0, and a second diode D1. The input terminal of the buffer core BBFILT_BUF is connected to the output terminal of the Saleen-Kay second-order low-pass filter 11. The third resistor R10 is connected between the power supply voltage terminal and the first output terminal of the buffer core BBFILT_BUF, and the fourth resistor R11 is connected between the power supply voltage terminal and the second output terminal of the buffer core BBFILT_BUF, together forming the load network of the differential output. The buffer core BBFILT_BUF is also connected to the second channel positive-inverting side stable bias node stb2a and the second channel anti-inverting side stable bias node stb2b. The first diode D0 and the second diode D1 are connected in reverse parallel between the first output terminal OUTP and the second output terminal OUTN of the buffer core BBFILT_BUF, forming a bidirectional clamping structure to limit the differential output voltage swing and provide overvoltage protection, ensuring the safety and stability of the subsequent circuit.

[0053] In one embodiment, the first-order filter 13 includes a fifth resistive element and a third capacitive element; the fifth resistive element is connected between the signal input terminal and the output terminal of the first-order filter 13; the third capacitive element is connected between the output terminal of the first-order filter 13 and ground; the first-order filter 13 and the Salen-Kay second-order low-pass filter 11 are cascaded through a unity-gain buffer 12 to jointly form a third-order low-pass filter response with three poles, so as to further attenuate high-frequency noise and improve stopband rejection capability.

[0054] In one specific embodiment, the first-order filter 13 is composed of a fifth resistor element R12 and a third capacitor element C0. The fifth resistor element R12 is connected in series between the signal input terminal and the output terminal of the first-order filter 13, while the third capacitor element C0 is connected in parallel between the output terminal of the first-order filter 13 and the reference ground, thus forming a standard RC low-pass network structure. This first-order filter 13 does not operate independently but is cascaded with the Saleen-Kay second-order low-pass filter 11 through a preceding unity-gain buffer 12. The unity-gain buffer 12 plays a crucial impedance isolation role here, eliminating the loading effect of the subsequent RC network on the quality factor of the preceding second-order filter. In the frequency domain, the preceding Saleen-Kay second-order low-pass filter 11 provides a pair of conjugate complex poles, while the current first-order filter 13 provides a real pole; the three together synthesize a third-order low-pass filter response with three poles. This cascaded architecture significantly improves the roll-off slope of the filter in the high-frequency band, enabling it to more effectively attenuate high-frequency noise and enhance stopband rejection, ultimately outputting a high-purity common-mode voltage VCM.

[0055] In one embodiment, the digital control signal includes a multi-bit tuning control word; the common-mode calibration filter further includes a signal buffer drive circuit, the input of which is connected to the digital common-mode calibration module 3 to receive the tuning control word, and the output of which is connected to the control terminal of the adjustable resistor array 2; the signal buffer drive circuit includes at least two series-connected inverters, and the tuning control word is converted into an internal tuning word after passing through at least two series-connected inverters, so that the logic level of the internal tuning word is consistent with that of the tuning control word; the internal tuning word is used to control the resistance value of the adjustable resistor array 2.

[0056] like Figure 6 As shown, in one specific implementation, FTUNE <2> FTUNE<1:0> is the original multi-bit tuning control word from the digital common-mode calibration circuit, serving as the initial input signal for the entire buffer drive link; the input of the first-stage inverter BBFILT_INV is used to receive this FTUNE signal, and its output is used to generate and transmit the intermediate signal nFTUNE after the first-stage inversion. <2> The input of the second-stage inverter BBFILT_INV is used to receive the aforementioned intermediate nFTUNE signal. After being inverted again, its output is used to generate the internal tuning word iFTUNE, which is in phase with the original FTUNE logic. <2> The signal is then compared with iFTUNE<1:0>; subsequently, the iFTUNE signal is further passed to subsequent driver stages or latch structures, ultimately generating iiFTUNE. <2> With iiFTUNE<1:0>, where iiFTUNE <2> The iiFTUNE<1:0> terminal is specifically used to output the final digital control signal, which has been buffered and shaped through multiple stages and has stronger driving capability, to the switch control terminal of the adjustable resistor array 2, so as to accurately drive the resistor network to achieve digital fine-tuning of the filter cutoff frequency or gain characteristics.

[0057] In one embodiment, the common-mode calibration filtering device further includes: a cascaded level shifter and a common-mode decoder; the input of the level shifter is coupled to an external digital control signal source for receiving a multi-bit common-mode control word and shifting the logic level of the common-mode control word upwards; the output of the level shifter is directly coupled to the input of the common-mode decoder to transmit the logic-level-shifted common-mode control word to the common-mode decoder for decoding, thereby generating multiple pairs of complementary decoding control signals; the output of the common-mode decoder is directly coupled to the control input of the digital common-mode calibration module 3 for transmitting the multiple pairs of complementary decoding control signals. A control signal is applied to the digital common-mode calibration module 3. The digital common-mode calibration module 3 includes multiple parallel-connected adjustment branches. Each adjustment branch contains a controlled switching device. The control terminal of the controlled switching device is used to receive a corresponding pair of complementary decoded control signals to turn on or off the corresponding adjustment branch. The current path terminals of the multiple parallel-connected adjustment branches are coupled to the output terminal of the third-order active low-pass filter. This is used to generate an adjustment current by turning on different numbers of adjustment branches and injecting it into the output terminal of the third-order active low-pass filter, thereby adjusting the output common-mode voltage of the third-order active low-pass filter.

[0058] like Figure 7As shown, in one specific embodiment, the common-mode calibration filter further integrates a cascaded level shifter BBFILT_LS and a common-mode decoder BBFILT_CMD_ENCODER to construct a complete and robust digital-to-analog control link. Specifically, the VDD1V terminal of the level shifter BBFILT_LS is used to receive an external low-voltage power supply, such as 1.0V, and its IN terminal is used to receive a multi-bit common-mode control word CM<2:0> from an external digital control source. This module integrates a 1.8V level conversion structure to safely shift the input signal from the low-voltage domain to the chip's internal standard voltage domain. The chip's internal standard voltage domain is powered by VDD and VSS to ensure the reliability of subsequent circuit driving. The converted signal is output from its OUT terminal and directly coupled to the input terminal of the common-mode decoder BBFILT_CMD_ENCODER. Subsequently, the common-mode decoder BBFILT_CMD_ENCODER decodes the input CM<2:0> under its VDD / VSS power supply, generating six sets of complementary decoding control signals, namely y<6:0> and its inverse signal ny<6:0>, which are sent out from the corresponding output ports. These multiple pairs of complementary signals are applied to the control input of the digital common-mode calibration circuit (not shown in the figure), where each pair of y and ny precisely controls a controlled switching device such as a CMOS transmission gate or differential pair in a parallel regulation branch, dynamically turning on or off the corresponding branch according to the decoding result. The current path terminals of all regulation branches are coupled to the output node of the third-order active low-pass filter. By changing the number of conducting branches, the regulation current is linearly injected or extracted, thereby finely raising or lowering the output common-mode potential, realizing stable closed-loop calibration of the DC operating point of the filter output.

[0059] In one embodiment, the third-order active low-pass filter further includes a baseband filter common-mode feedback circuit; the output of the baseband filter common-mode feedback circuit is connected to the bias control terminal of the source follower buffer, the baseband filter common-mode feedback circuit is used to detect the voltage of the common-mode node and generate a common-mode feedback adjustment signal, the common-mode feedback adjustment signal is used to adjust the static operating current of the source follower buffer to stabilize the common-mode voltage; the output of the digital common-mode calibration module 3 is connected to the control terminal of the unity-gain buffer 12, the digital common-mode calibration module 3 is used to generate a digital adjustment current to calibrate the initial voltage of the common-mode node, and the baseband filter common-mode feedback circuit maintains the common-mode voltage in a dynamically stable state.

[0060] like Figure 8As shown, in one specific embodiment, the third-order active low-pass filter also integrates a dedicated baseband filter common-mode feedback circuit BBFILT_CMFB, whose core function is to dynamically detect and stabilize the output common-mode node voltage. The VDD and VSS terminals of this module are used to connect to the positive and negative power rails to establish the operating bias; the cmp and cmn terminals serve as a differential sensing input pair, directly coupled to the common-mode node of the filter output, sampling the current common-mode level in real time and comparing it with an internal reference. Based on the comparison result, the common-mode feedback circuit BBFILT_CMFB generates an analog common-mode feedback adjustment signal at its pbias terminal. This signal is directly connected to the bias control terminal of the source follower buffer, dynamically adjusting the static operating current of the buffer through a closed-loop negative feedback mechanism, thereby suppressing common-mode drift caused by process, temperature, or load changes and ensuring long-term stability of the output DC operating point. Meanwhile, the output of the digital common-mode calibration module 3 is connected to the control terminal of the unity-gain buffer 12 to inject digital adjustment current for coarse adjustment of the initial voltage of the common-mode node; the common-mode feedback circuit BBFILT_CMFB performs fine adjustment and dynamic maintenance tasks on this basis, and the two work together to realize a two-layer common-mode management architecture of "digital pre-calibration + analog closed-loop stability control". In addition, the common-mode feedback circuit BBFILT_CMFB also receives multiple sets of control signals from the upstream decoder: the nbias terminal is used to receive the global bias enable or mode selection signal, the y<6:0> and iy<6:0> terminals receive positive and negative digital weight control words respectively, which are used to configure the quantization step or gain coefficient of the internal current source, thereby flexibly setting the feedback loop strength or compensation range; the cmpdn and cmndn terminals are redundant or test reserved interfaces for external forced pull-down / pull-up of the common-mode node or diagnostic mode triggering. Overall, the common-mode feedback circuit BBFILT_CMFB constructs a high-precision and robust common-mode voltage stabilization system through a triple mechanism of analog sensing, digital configuration, and dynamic adjustment, providing a clean and stable DC operating environment for subsequent cascaded circuits.

[0061] like Figure 9As shown, in one example, the third-order active low-pass filter further integrates a digitally programmable current source array for fine calibration and dynamic compensation of the common-mode voltage. The current source structure adopts a symmetrical differential architecture: the upper part consists of PMOS transistors MP10–MP20 forming a multi-stage cascode current mirror and bias network, where the gate of MP10 receives the common-mode positive terminal signal cmp from the filter output, and transistors such as MP18 and MP13 act as mirror loads to provide a stable high-impedance output path; the lower part consists of seven parallel current source branches MN9–MN26 controlled by NMOS switches, each consisting of a main switch such as MN9 and a tail current source such as MN12 connected in series. Their conduction state is independently driven by a pair of complementary digital control signals y and iy (i=0~6). When y=1 and iy=0, the corresponding branch is configured in current sink mode, drawing (sinking) charge from the output node; otherwise, it is configured in current source mode, injecting (source / injecting) charge into the output node, thereby achieving bidirectional regulation capability.

[0062] In another example, the global bias voltages pbias and nbias are used to set the reference current magnitudes on the PMOS and NMOS sides, respectively, determining the quantization unit (LSB) of the current adjustment step, ensuring calibration resolution down to the microampere or even nanoampere level. All branches are connected to VSS at the bottom and to the filter output common-mode node via a switching node at the top, ultimately synthesizing the net adjustment current I_adj = Σ(k_i × I_LSB), where k_i ∈ {-1, 0, +1}, supporting fine-tuning of the common-mode voltage in any direction and with any step size. I_LSB is the reference current unit determined by the bias voltages nbias / pbias and the unit-size NMOS / PMOS transistor. Furthermore, the cmpdn and cmndn ports are reserved as test or redundant interfaces, which can be used for externally forcibly pulling the common-mode level low or triggering diagnostic modes. The programmable current source array works in conjunction with the aforementioned baseband filter common-mode feedback circuit BBFILT_CMFB: the former is responsible for the initial coarse adjustment and static offset elimination during the power-on or reset phase, while the latter is responsible for the dynamic closed-loop stability control during operation. Together, they construct a dual-layer common-mode management mechanism of "digital pre-calibration + analog fine adjustment", which significantly improves the robustness and long-term stability of the system under PVT changes. It is particularly suitable for high-speed data converters or wireless receiver front-end applications with stringent DC accuracy requirements.

[0063] In one embodiment, the source follower buffer includes a differential input pair, a differential load circuit, and an impedance feedback network. The differential input pair includes a first input transistor and a second input transistor, with the source of the first input transistor forming a third output terminal and the source of the second input transistor forming a fourth output terminal. The impedance feedback network includes a first feedback branch and a second feedback branch. The first feedback branch includes a first compensation capacitor and a first feedback transistor connected in series. One end of the first compensation capacitor is connected to the third output terminal, and the other end of the first compensation capacitor is connected to the control terminal of the first feedback transistor. The first end of the first feedback transistor is connected to the control terminal of the load transistor corresponding to the third output terminal in the differential load circuit. The second end of the first feedback transistor is connected to a reference ground. The second feedback branch includes a second compensation capacitor and a second feedback transistor connected in series. One end of the second compensation capacitor is connected to the fourth output terminal, and the other end of the second compensation capacitor is connected to the control terminal of the second feedback transistor. The first end of the second feedback transistor is connected to the control terminal of the load transistor corresponding to the fourth output terminal in the differential load circuit. The second end of the second feedback transistor is connected to a reference ground. The impedance feedback network is configured to reduce the output impedance of the source follower buffer, and the first compensation capacitor and the second compensation capacitor are used to maintain the stability of the impedance feedback network.

[0064] like Figure 10As shown, in one embodiment, the source follower buffer adopts a fully differential architecture, with its core consisting of a differential input pair, a differential load circuit, and an impedance feedback network. The differential input pair includes PMOS transistors serving as the first input transistor MP17 and the second input transistor MP18. Their sources are directly led out to form the third output terminal OUTP and the fourth output terminal OUTN, respectively, while their drains are pulled down to ground through the first tail current source transistor MN0 and the second tail current source transistor MN1. The gates of MN0 and MN1 jointly receive the control signal from the bias voltage input terminal IB10U to set the quiescent operating current. The operating state of the source follower buffer is controlled by the enable signal input terminal EN, which drives the enable control transistor groups MP2 and MP16 to connect or disconnect the power supply and bias path. The differential load circuit consists of the first pull-up load transistor MP11 and the second pull-up load transistor MP15, which are connected between the power supply and the output terminal, respectively. Their gate potentials are determined by internal bias nodes stba and stbb, and the establishment of these bias nodes depends on the diode-connected first bias transistor MP12 and the second bias transistor MP10. To significantly reduce output impedance, the source follower buffer incorporates an impedance feedback network with two symmetrical branches: the first feedback branch consists of a first feedback resistor R3, a first compensation capacitor C0, and a first feedback transistor MN7 connected in series. The signal from the third output terminal OUTP is coupled to the control terminal of the first feedback transistor MN7 via the first feedback resistor R3 and the first compensation capacitor C0, thereby adjusting the gate drive of the corresponding load transistor. The second feedback branch is completely symmetrical, consisting of a second feedback resistor R4, a second compensation capacitor C12, and a second feedback transistor MN6. It couples the signal from the fourth output terminal OUTN to adjust the control terminal of the load transistor on the other side. In this structure, the feedback resistors R3 and R4 act as isolation and damping resistors to prevent high-frequency oscillations, while the first and second compensation capacitors ensure the phase margin of the feedback loop. Both work together to maintain the stability of the impedance feedback network, ultimately achieving low output impedance and high stability buffer drive performance.

[0065] This embodiment verifies the robustness and performance of the common-mode calibration device under extreme process, voltage, and temperature conditions using multi-dimensional circuit simulation data. The simulation test environment comprehensively covers three standard process corner combinations: slow, typical, and fast, and is verified within the full industrial temperature range of -40°C to 110°C and a power supply fluctuation range of 1.674V to 1.926V. Linearity testing uses 0.9MHz and 1.1MHz dual-tone signals close to the target bandwidth, with input amplitude covering the maximum differential swing expected by the DVFS (Dynamic Voltage and Frequency Scaling) monitoring link to ensure reliability under large signal dynamic range. Regarding key performance indicators, the total quiescent current consumption of the system is controlled between 0.5mA and 1.2mA, with the filter buffer stage accounting for the majority of power consumption, while the output buffer and comparator modules achieve low-power optimization. Frequency response testing showed that before tuning, the circuit bandwidth was distributed between 0.8MHz and 1.25MHz due to PVT. However, after enabling 3-bit programmable resistor array calibration, the bandwidth was precisely converged to the 0.9MHz to 1.1MHz range, successfully locking the center frequency at 1MHz with an error controlled within ±10%. Within the target passband, the AC gain stabilized near 0dB, with an attenuation of approximately -3dB at the cutoff frequency, and the overall amplitude-frequency response was smooth and peakless. In terms of noise performance, the input reference noise in the 10kHz to 1MHz band remained on the order of tens of nV / √Hz, fully meeting the accuracy requirements for weak signal detection.

[0066] Before calibration or during the initial stages of environmental abrupt changes, the output common-mode voltage may exhibit significant drift. However, after the calibration logic is activated, the circuit rapidly injects or extracts charge via a digitally controlled current source, forcing the output voltage to converge and be strictly locked within a safe window of 350mV to 450mV (target value 400mV ± 50mV). Even under power supply jumps or drastic temperature changes, the system can recover quickly, verifying the efficiency of the calibration algorithm. Furthermore, two-tone testing shows that both second- and third-order intercept points meet high linearity requirements, with nonlinear distortion far below the system tolerance. Multi-channel matching testing shows minimal gain and bandwidth mismatch, and an inter-channel crosstalk suppression ratio better than -90dB. Finally, AC small-signal analysis confirms that both the filter's main loop and the output buffer stage have sufficient phase margins of 50° to 80°, ensuring that the system has no risk of self-oscillation in DVFS closed-loop applications.

[0067] like Figure 11As shown, the simulation waveforms intuitively demonstrate the bandwidth adjustment process and convergence characteristics of the mixed-signal adaptive calibration circuit under different process angles. The horizontal axis in the figure is defined as Tune, representing the number of discrete iteration steps executed by the calibration algorithm. The upper vertical axis is labeled M, corresponding to the three upper curves BW_tt, BW_ff, and BW_ss, representing the bandwidth values ​​of the circuit under Typical-Typical, Fast-Fast, and Slow-Slow process angles, in MHz. The lower vertical axis is labeled k, corresponding to the three lower curves deriv(BW_tt), deriv(BW_ff), and deriv(BW_ss), representing the derivative of the bandwidth as a function of the number of calibration steps, i.e., the rate of change, in kHz / step or a relevant scaling unit. In the initial stage of the simulation, i.e., the Tune value is between 0 and 3, the circuit bandwidth shows a slow upward trend under different process angles as the number of calibration steps increases. The bandwidth is highest under the Fast-Fast angle and lowest under the Slow-Slow angle, consistent with process deviation characteristics. However, around a Tune value of 3, the bandwidth experienced a sudden drop, with a sharp negative peak appearing simultaneously on the derivative curve. This indicates that the calibration logic performed a significant parameter reconfiguration at this moment, causing a momentary decrease in bandwidth. Subsequently, within the Tune value range of 4 to 5, the bandwidth experienced a brief trough before rapidly recovering and entering a stable state, with the derivative curve also returning to a lower level. Particularly after the Tune value exceeded 5, the three bandwidth curves flattened out and maintained a specific proportional relationship, indicating that the calibration circuit had successfully locked the operating point, eliminating some of the performance differences caused by PVT. This waveform fully records the entire process from bandwidth ramp-up to logic reset to steady-state locking, confirming that the calibration mechanism can effectively manage the frequency response characteristics of the circuit.

[0068] like Figure 12 As shown, the second embodiment of the present invention provides a parameter optimization method for a common-mode calibration filter device, used to optimize the common-mode calibration filter device in any of the above embodiments. The parameter optimization method includes the following steps S1-S4: S1. Construct a candidate set containing various filter circuit topologies, obtain multi-dimensional performance simulation data of each topology in the candidate set under preset operating conditions; use a machine learning model to evaluate the multi-dimensional performance simulation data, and automatically determine the target filter topology from the candidate set based on preset comprehensive performance indicators including common-mode rejection ratio and differential-mode to common-mode conversion gain.

[0069] S2. Based on the determined target filter topology, define the search space for circuit element parameters and generate multiple sets of parameter combinations that satisfy the target frequency response. Perform multi-dimensional performance simulation on multiple sets of parameter combinations, and use at least two of the following as optimization objectives: bandwidth stability, noise performance, linearity, and chip area. Determine the nominal parameter values ​​of the circuit elements through a multi-objective optimization algorithm.

[0070] S3. Analyze the impact range of actual manufacturing process deviations on common-mode bandwidth. Using nominal parameter values ​​as the design benchmark, determine the circuit structure and parameters of the adjustable resistor array containing switchable branches. Based on the impact range and nominal parameter values, plan the resistance range distribution and digital control mapping strategy of the adjustable resistor array.

[0071] S4, during actual operation or calibration, based on the digital control mapping strategy, converts the deviation between the measured common-mode bandwidth and the target common-mode bandwidth into a digital control signal, dynamically adjusts the equivalent resistance value of the adjustable resistor array, thereby compensating for the common-mode frequency drift caused by process deviation, and converging the actual common-mode bandwidth of the common-mode calibration filter device to the target common-mode bandwidth range.

[0072] like Figure 13 As shown, in one specific embodiment, the optimization method is implemented by a mixed-signal adaptive common-mode calibration circuit. This circuit addresses the issue that the DC output level of the front-end amplifier link, such as the DVFS monitoring front-end amplifier bbamp, is fixed at a relatively high value of approximately 700 to 900 mV. Furthermore, after being transmitted through multiple source followers MN0, MP0, and MN1, the overall output common-mode drift can reach ±150 mV due to process, voltage, and temperature fluctuations. A closed-loop correction scheme with a target level of 400 mV ± 50 mV is proposed. This circuit architecture employs a multi-stage source follower and programmable current source working in a collaborative mode: the input signal bbamp is first transmitted to the intermediate node through the first-stage source follower composed of the left-side NMOS transistor MN0, and then coupled to the core regulation unit via resistor R0; the right-side NMOS transistor MN1 serves as the second-stage source follower, its gate driven by the intermediate node voltage, ultimately outputting the calibrated common-mode voltage bbfiltout from its source, achieving a buffer characteristic of high-impedance input and low-impedance output, ensuring that load changes do not affect the stability of the front-end circuit.

[0073] The core regulation mechanism of the circuit relies on digitally controllable pull-up PMOS current source I4 and pull-down NMOS current source I6, as well as a feedback network composed of auxiliary current sources such as I0, I1, and I3 and PMOS transistor MP0. The current amplitudes of I4 and I6 can be adjusted in fixed steps within the range of 0 to tens of μA, directly fine-tuning the DC potential by injecting or extracting charge into the output node. I0 and I4 are connected between the power supply and the intermediate node to raise the level, while I3 and I6 are connected to the reference ground to provide a pull-down path, forming a voltage divider-current hybrid regulation structure in conjunction with R0 and R1. MP0, as a key regulation element, has its gate controlled by the intermediate node voltage, its drain connected to ground (gnd), and its source connected to the lower end of R0, forming a local negative feedback loop: when the output common-mode voltage is too high, MP0 conducts more strongly to increase the pull-down current, forcing the voltage to drop; conversely, it weakens conduction to allow the voltage to rise, thus achieving automatic balancing. All current sources support digital programmable control, which can dynamically adjust the injected or extracted current according to system requirements, achieving multi-level calibration capability that combines coarse and fine adjustment.

[0074] To achieve closed-loop control, the circuit uses a resistor divider network with an RC low-pass filter at the output to sample the common-mode voltage in real time and filter out high-frequency ripple. The sampled voltage is then fed into a dual-threshold window comparator for decision-making. The upper limit reference voltage is set to approximately 450mV, including a hysteresis range of 445 to 455mV; the lower limit reference voltage is set to approximately 350mV, also including a hysteresis range of 345 to 355mV. The comparison results are encoded as cmp_IL and cmp_QL, indicating whether the current common-mode state has exceeded the limits. Digital control logic, such as a state machine or counter, executes a progressive adjustment strategy based on the comparator output: when the detected common-mode voltage is below 350mV, the pull-up current code is gradually increased or the pull-down current code is decreased; when it is above 450mV, the operation is reversed; if it is within the 350 to 450mV safety window, the current codeword is locked, and the circuit enters a sustain mode. Each adjustment changes only one bit or one minimum step unit to avoid abrupt disturbances to the signal path. The calibration cycle is designed to be about 10μs or longer per channel, which can track slowly changing environmental parameters without affecting the dynamic response within the baseband signal bandwidth.

[0075] The entire system consists of an analog front-end, including a sampling network, a reference voltage generator, a high-speed comparator, and a programmable current mirror array, and a digital back-end, including a decoder, a state machine, and registers. Compared to traditional all-analog common-mode feedback architectures, this system offers significant advantages such as precisely definable target levels, flexible step size configuration, and online update support for calibration strategies. By combining AI-aided design methods, it can also jointly optimize the reference voltage ratio, current source size, code width resolution, and convergence algorithm based on simulation data, achieving an optimal balance between speed, noise, stability, and power consumption. This ultimately enables high-precision, robust, and low-power adaptive common-mode stabilization, ensuring that the subsequent analog-to-digital converter and comparator always operate in the linear region, thereby improving the overall receiver sensitivity and dynamic range. This model is not only applicable to the baseband filter back-end but can also be extended to other analog modules requiring common-mode stability, exhibiting good process compatibility and temperature robustness.

[0076] In one implementation, the candidate set includes a traditional second-order Salem-Kai filter with resistor-capacitor real pole topology, a multi-feedback filter topology with additional real poles, and topology variants with different pole allocation methods or different cascade orders. Multidimensional performance simulation data is acquired, including: for each topology, designing a matching capacitor value within a given resistance range based on the target cutoff function, and performing AC characteristics, noise characteristics, and stability simulations under multiple process-voltage-temperature combinations to extract noise spectral density, linearity index, phase margin, pole distribution, and the required total capacitor area. Evaluation is performed using a machine learning model, including: using the relationship between noise and capacitance as the core analysis dimension, and comprehensively considering multiple indicators including linearity, stability, and pole distribution to construct a comprehensive evaluation system; using artificial intelligence or machine learning methods to model the input data including topology category, resistor-capacitor ratio, and pole configuration method, outputting comprehensive indicators of noise, linearity, stability, and area; prioritizing minimizing the total capacitor area while meeting low noise requirements, and using linearity and stability requirements as constraints, performing multi-objective automatic screening to determine the target filter topology with optimal comprehensive performance.

[0077] In one implementation, the candidate set encompasses traditional second-order Salem-Key filters with resistor-capacitor real pole topologies, multi-feedback filters with additional real poles, and various topology variants with different pole allocation methods or cascade orders. The process of acquiring multidimensional performance simulation data is carried out for each topology. First, a matching capacitor value is designed within a given resistance range based on the target cutoff function. Then, AC characteristics, noise characteristics, and stability simulations are performed under multiple process-voltage-temperature combinations to extract key parameters such as noise spectral density, linearity index, phase margin, pole distribution, and the required total capacitor area. Based on this, when evaluating using a machine learning model, the relationship between noise and capacitance is used as the core analysis dimension, and a comprehensive evaluation system is constructed by comprehensively considering multiple indicators such as linearity, stability, and pole distribution. This system uses artificial intelligence or machine learning methods to model input data including topology type, resistor-capacitor ratio, and pole configuration, outputting comprehensive indicators of noise, linearity, stability, and area. The final selection strategy prioritizes low noise and minimizes the total capacitor area, while also satisfying linearity and stability requirements. Through a multi-objective automatic selection mechanism, the target filter topology with the best overall performance is determined.

[0078] In one implementation, generating multiple sets of parameter combinations that satisfy the target frequency response and determining nominal parameter values ​​includes: defining the value range of resistors and capacitors based on the determined target filter topology, combined with process design rules and area constraints; automatically generating resistor-capacitor parameter combinations that conform to the characteristics of the target transfer function within the value range, and distributing the nominal cutoff frequencies corresponding to each parameter combination within a preset frequency band centered on the target frequency; and performing multi-dimensional performance simulations on multiple sets of parameter combinations, including: performing AC simulation, noise simulation, linearity simulation, and stability analysis under multiple process-voltage-temperature combination conditions. Analysis is performed to obtain multi-dimensional simulation data including bandwidth, group delay, integral noise within the target frequency band, second and third harmonic intercept points, and phase margin. Nominal parameter values ​​are determined through a multi-objective optimization algorithm, including: calculating the bandwidth fluctuation range and robustness measures of each index based on the multi-dimensional simulation data; constructing a multi-objective function including nominal bandwidth fit, bandwidth operating condition fluctuation rate, integral noise, harmonic intercept point, phase margin, and total capacitor area; and using the Pareto front optimization algorithm to output several non-dominated optimal solution sets, from which a set of resistor-capacitor parameters that balances performance robustness and area efficiency is selected as the nominal parameter values.

[0079] In one implementation, the process of generating multiple sets of parameter combinations that satisfy the target frequency response and determining nominal parameter values ​​first involves defining the value ranges of resistors and capacitors based on the determined target filter topology, combined with process design rules and area constraints. Then, within this value range, resistor-capacitor parameter combinations that conform to the characteristics of the target transfer function are automatically generated, ensuring that the nominal cutoff frequencies corresponding to each combination are distributed within a preset frequency band centered on the target frequency. Next, multi-dimensional performance simulations are performed on the generated parameter combinations, i.e., AC simulation, noise simulation, linearity simulation, and stability analysis are executed under multiple process-voltage-temperature combinations, thereby obtaining multi-dimensional simulation data including bandwidth, group delay, integral noise within the target frequency band, second and third harmonic cutoff points, and phase margin. Finally, the nominal parameter values ​​are determined through a multi-objective optimization algorithm. Specifically, based on the multi-dimensional simulation data mentioned above, the fluctuation range of the bandwidth and the robustness measure of each index are calculated. A multi-objective function is constructed that covers nominal bandwidth fit, bandwidth operating condition fluctuation rate, integral noise, harmonic intercept point, phase margin, and total capacitor area. The Pareto front optimization algorithm is used to output several non-dominated optimal solution sets, and a set of resistor-capacitor parameters that can balance performance robustness and achieve optimal area efficiency are selected as the final nominal parameter values.

[0080] In one implementation, the planning of the resistance range distribution and digital control mapping strategy for the adjustable resistor array includes: determining the error coverage range of the nominal parameter values ​​based on the statistical deviation range of resistors and capacitors in the actual manufacturing process; constructing an adjustable resistor array or adjustable capacitor array with discrete adjustment step sizes based on the nominal parameter values, wherein the accuracy of the discrete adjustment step size is set to be less than or equal to half of the statistical deviation range to ensure that the adjustment resolution is sufficient to compensate for process fluctuations; calculating the required number and distribution pattern of resistance ranges in combination with the error coverage range and the preset frequency calibration accuracy requirements, and determining the corresponding number of digital control code bits; and establishing a mapping relationship between the digital control code and the resistance ranges to compensate for the initial frequency offset caused by process deviations to the range allowed by the frequency calibration accuracy requirements using the mapping relationship.

[0081] In one implementation, the process of planning the resistance range distribution and digital control mapping strategy of the adjustable resistor array is as follows: First, based on the statistical deviation range of resistors and capacitors in the actual manufacturing process, the error coverage range of the nominal parameter values ​​is determined; then, using the nominal parameter values ​​as a reference, an adjustable resistor array or adjustable capacitor array with discrete adjustment step sizes is constructed, and the accuracy of the discrete adjustment step size is set to be less than or equal to half of the statistical deviation range to ensure that the adjustment resolution is sufficient to compensate for process fluctuations; next, combining the error coverage range and the preset frequency calibration accuracy requirements, the required number of resistance ranges and their distribution patterns are calculated, and the corresponding number of digital control code bits is determined accordingly; finally, a mapping relationship between the digital control code and the resistance ranges is established, and this mapping relationship is used to compensate the initial frequency offset caused by process deviations to the range allowed by the frequency calibration accuracy requirements.

[0082] In one implementation, the deviation between the measured common-mode bandwidth and the target common-mode bandwidth is converted into a digital control signal. This includes: injecting a test excitation signal into the input of the common-mode calibration filter in chip initialization or calibration mode, and monitoring the frequency response characteristics of the output to obtain the measured bandwidth; calculating the difference between the measured bandwidth and the target bandwidth; if the difference exceeds a preset frequency tolerance range, reading a pre-stored digital control mapping strategy from the on-chip non-volatile memory to determine the direction and step size of the resistance adjustment; updating the digital control code according to the direction and step size, switching the switchable branch state in the adjustable resistor array, dynamically changing the equivalent time constant of the common-mode calibration filter until the measured bandwidth falls within the range allowed by the frequency calibration accuracy requirements, and saving the finally locked digital control code as the working configuration.

[0083] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0084] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. A common-mode calibration filter device, characterized in that, The common-mode calibration filter device includes at least one filter channel, and each filter channel includes: a filter core module, an adjustable resistor array, and a digital common-mode calibration module; The filter core module has a DC operating path, and the DC operating path has a common-mode node; The input terminal of the digital common-mode calibration module is connected to the common-mode node. The digital common-mode calibration module is used to compare the common-mode voltage on the common-mode node with the reference voltage and generate a digital control signal based on the comparison result. The adjustable resistor array is connected to the DC operating path of the filter core module; the control terminal of the adjustable resistor array is used to receive the digital control signal and adjust the equivalent resistance value of the adjustable resistor array according to the digital control signal to change the DC current flowing through the DC operating path, thereby correcting the common mode voltage.

2. The common-mode calibration filter device according to claim 1, characterized in that, The core module of the filter is a third-order active low-pass filter; The third-order active low-pass filter includes a Salen-Kai second-order low-pass filter, a unity-gain buffer, and a first-order filter; the output of the Salen-Kai second-order low-pass filter is connected to the input of the unity-gain buffer, and the output of the unity-gain buffer is connected to the input of the first-order filter; the unity-gain buffer is used to isolate the Salen-Kai second-order low-pass filter and the first-order filter to eliminate load effects.

3. The common-mode calibration filter device according to claim 2, characterized in that, The Salen-Kay second-order low-pass filter adopts a fully differential structure, which integrates a signal input terminal, an input RC network, a source follower buffer, and a feedback capacitor network connected in sequence. The signal input terminal is used to acquire the input differential signal; The input RC network is connected between the signal input terminal and the input terminal of the source follower buffer, and is used to construct the passive network basis of the second-order low-pass filter characteristics, and couple the input differential signal to the source follower buffer; The output of the source follower buffer serves as the signal output of the Salen-Kay second-order low-pass filter and is used to provide low output impedance to drive subsequent circuits. The output terminal of the source follower buffer is connected to the input RC network through the feedback capacitor network, which is used to couple the output signal of the source follower buffer to the input RC network to form a frequency compensation path, so that the input RC network exhibits second-order low-pass filtering characteristics for the input differential signal. Wherein, at least one of the resistive element in the input RC network and the capacitive element in the feedback capacitor network is an adjustable element to match the frequency response of the Salen-Kai second-order low-pass filter adjusted by the digital common-mode calibration module.

4. The common-mode calibration filter device according to claim 3, characterized in that, The input RC network includes: a first capacitor element, a second capacitor element, a first resistor element, and a second resistor element; The first resistor and the second resistor are connected in series between the signal input terminal of the Salen-Kay second-order low-pass filter and the input terminal of the source follower buffer; One end of the first capacitor element is connected to the intermediate node between the first resistor element and the second resistor element, and the other end of the first capacitor element is connected to the output terminal of the source follower buffer; The second capacitor element is connected between the two input terminals of the source follower buffer.

5. The common-mode calibration filter device according to claim 3, characterized in that, The source follower buffer includes: a buffer core, a third resistive element, a fourth resistive element, a first diode, and a second diode; The input terminal of the buffer core is connected to the output terminal of the Salen-Kay second-order low-pass filter; the third resistor is connected between the power supply voltage terminal and the first output terminal of the buffer core; the fourth resistor is connected between the power supply voltage terminal and the second output terminal of the buffer core; the first diode and the second diode are connected in reverse parallel between the first output terminal and the second output terminal of the buffer core.

6. The common-mode calibration filter device according to claim 2, characterized in that, The first-order filter includes a fifth resistive element and a third capacitive element; The fifth resistor element is connected between the signal input terminal and the output terminal of the first-order filter. The third capacitor element is connected between the output of the first-order filter and the reference ground. The first-order filter and the Salen-Kai second-order low-pass filter are cascaded through the unity-gain buffer to jointly form a third-order low-pass filter response with three poles.

7. The common-mode calibration filter device according to claim 1, characterized in that, The digital control signal includes a multi-bit tuning control word; the common-mode calibration filter also includes a signal buffer drive circuit, the input of which is connected to the digital common-mode calibration module to receive the tuning control word, and the output of which is connected to the control terminal of the adjustable resistor array. The signal buffer drive circuit includes at least two inverters connected in series. The tuning control word is converted into an internal tuning word after passing through the at least two inverters connected in series, and the logic level of the internal tuning word is in phase with that of the tuning control word. The internal tuning word is used to control the resistance value of the adjustable resistor array.

8. The common-mode calibration filter device according to claim 2, characterized in that, The common-mode calibration filter device further includes: a cascaded level shifter and a common-mode decoder; The input of the level shifter is coupled to an external digital control signal source to receive a multi-bit common-mode control word and shift the logic level of the common-mode control word upwards. The output of the level shifter is directly coupled to the input of the common-mode decoder to transmit the common-mode control word after logic level shifting to the common-mode decoder for decoding, thereby generating multiple pairs of complementary decoding control signals. The output of the common-mode decoder is directly coupled to the control input of the digital common-mode calibration module, and is used to apply the multiple pairs of complementary decoding control signals to the digital common-mode calibration module. The digital common-mode calibration module includes multiple parallel-connected adjustment branches, each of which contains a controlled switch device. The control terminal of the controlled switch device is used to receive a corresponding pair of the multiple pairs of complementary decoding control signals to turn on or off the corresponding adjustment branch. The current path terminals of the multiple parallel-connected adjustment branches are coupled to the output terminal of the third-order active low-pass filter, which is used to generate an adjustment current by turning on different numbers of the adjustment branches and injecting it into the output terminal of the third-order active low-pass filter, thereby adjusting the output common-mode voltage of the third-order active low-pass filter.

9. The common-mode calibration filter device according to claim 3, characterized in that, The third-order active low-pass filter also includes a baseband filter common-mode feedback circuit; The output terminal of the baseband filter common-mode feedback circuit is connected to the bias control terminal of the source follower buffer. The baseband filter common-mode feedback circuit is used to detect the voltage of the common-mode node and generate a common-mode feedback adjustment signal. The common-mode feedback adjustment signal is used to adjust the static operating current of the source follower buffer to stabilize the common-mode voltage. The output of the digital common-mode calibration module is connected to the control terminal of the unity-gain buffer. The digital common-mode calibration module is used to generate a digital adjustment current to calibrate the initial voltage of the common-mode node. The baseband filter common-mode feedback circuit maintains the common-mode voltage in a dynamically stable state.

10. The common-mode calibration filter device according to claim 9, characterized in that, The source follower buffer includes a differential input pair, a differential load circuit, and an impedance feedback network; The differential input pair includes a first input transistor and a second input transistor, the source of the first input transistor forms a third output terminal, and the source of the second input transistor forms a fourth output terminal; The impedance feedback network includes a first feedback branch and a second feedback branch; The first feedback branch includes a first compensation capacitor and a first feedback transistor connected in series. One end of the first compensation capacitor is connected to the third output terminal, and the other end of the first compensation capacitor is connected to the control terminal of the first feedback transistor. The first end of the first feedback transistor is connected to the control terminal of the load transistor corresponding to the third output terminal in the differential load circuit. The second end of the first feedback transistor is connected to reference ground. The second feedback branch includes a second compensation capacitor and a second feedback transistor connected in series. One end of the second compensation capacitor is connected to the fourth output terminal, and the other end of the second compensation capacitor is connected to the control terminal of the second feedback transistor. The first end of the second feedback transistor is connected to the control terminal of the load transistor corresponding to the fourth output terminal in the differential load circuit. The second end of the second feedback transistor is connected to reference ground. The impedance feedback network is configured to reduce the output impedance of the source follower buffer, and the first compensation capacitor and the second compensation capacitor are used to maintain the stability of the impedance feedback network.

11. A method for optimizing the parameters of a common-mode calibration filter, used to optimize the common-mode calibration filter according to any one of claims 1 to 10, characterized in that, The parameter optimization methods include: A candidate set containing various filter circuit topologies is constructed, and multi-dimensional performance simulation data of each topology in the candidate set under preset operating conditions is obtained. The multi-dimensional performance simulation data is evaluated using a machine learning model, and the target filter topology is automatically determined from the candidate set based on preset comprehensive performance indicators including common-mode rejection ratio and differential-mode to common-mode conversion gain. Based on the determined target filter topology, a search space for circuit element parameters is defined, and multiple sets of parameter combinations that satisfy the target frequency response are generated. Multi-dimensional performance simulations are performed on the multiple sets of parameter combinations, and at least two of the following are used as optimization objectives: bandwidth stability, noise performance, linearity, and chip area. The nominal parameter values ​​of the circuit elements are determined by a multi-objective optimization algorithm. The influence range of actual manufacturing process deviations on common-mode bandwidth is analyzed. Based on the nominal parameter values, the circuit structure and parameters of the adjustable resistor array containing switchable branches are determined. According to the influence range and the nominal parameter values, the resistance range distribution and digital control mapping strategy of the adjustable resistor array are planned. During actual operation or calibration, based on the digital control mapping strategy, the deviation between the measured common-mode bandwidth and the target common-mode bandwidth is converted into a digital control signal, and the equivalent resistance value of the adjustable resistor array is dynamically adjusted to compensate for the common-mode frequency drift caused by process deviation, thereby converging the actual common-mode bandwidth of the common-mode calibration filter device to the target common-mode bandwidth range.

12. The parameter optimization method according to claim 11, characterized in that, The candidate set includes a traditional second-order Salem-Kai filter with resistor-capacitor real pole topology, a multi-feedback filter with additional real pole topology, and topology variants with different pole allocation methods or different cascade orders. The acquisition of multidimensional performance simulation data includes: for each topology, designing a matching capacitor value within a given resistance range based on the target cutoff function, and performing AC characteristics, noise characteristics, and stability simulations under multiple process-voltage-temperature combinations, extracting noise spectral density, linearity index, phase margin, pole distribution, and the required total capacitor area; The evaluation using machine learning models includes: taking the relationship between noise and capacitance as the core analysis dimension, and comprehensively considering multiple indicators including linearity, stability, and pole distribution to construct a comprehensive evaluation system. Artificial intelligence or machine learning methods are used to model the input data, which includes topology category, resistance-to-capacitance ratio, and pole configuration, and output comprehensive indicators of noise, linearity, stability, and area. Minimizing the total capacitor area under the premise of low noise is the primary objective, and meeting the requirements of linearity and stability is the constraint. Multi-objective automatic screening is performed to determine the target filter topology with the best comprehensive performance.

13. The parameter optimization method according to claim 11, characterized in that, The process of generating multiple sets of parameter combinations that satisfy the target frequency response and determining nominal parameter values ​​includes: Based on the determined target filter topology, the range of values ​​for resistors and capacitors is defined in combination with process design rules and area constraints; Within the specified value range, a resistance-capacitor parameter combination that conforms to the characteristics of the target transfer function is automatically generated, and the nominal cutoff frequencies corresponding to each parameter combination are distributed within a preset frequency band centered on the target frequency. Multi-dimensional performance simulations are performed on multiple sets of parameter combinations, including: performing AC simulation, noise simulation, linearity simulation and stability analysis under multiple process-voltage-temperature combination conditions, thereby obtaining multi-dimensional simulation data including bandwidth, group delay, integral noise in the target frequency band, second and third harmonic intercept points, and phase margin. The nominal parameter values ​​are determined by a multi-objective optimization algorithm, including: calculating the bandwidth fluctuation range and robustness measures of each index based on the multi-dimensional simulation data; constructing a multi-objective function that includes nominal bandwidth fit, bandwidth operating condition fluctuation rate, integral noise, harmonic intercept point, phase margin, and total capacitor area; and using the Pareto front optimization algorithm to output several non-dominated optimal solution sets, from which a set of resistor-capacitor parameters that balances performance robustness and area efficiency are selected as the nominal parameter values.

14. The parameter optimization method according to claim 11, characterized in that, The planning of the resistance range distribution and digital control mapping strategy for the adjustable resistor array includes: Based on the statistical deviation range of resistance and capacitance in actual manufacturing processes, the error coverage range of nominal parameter values ​​is determined. Based on the nominal parameter values, an adjustable resistor array or adjustable capacitor array with discrete adjustment step size is constructed. The accuracy of the discrete adjustment step size is set to be less than or equal to half of the statistical deviation range to ensure that the adjustment resolution is sufficient to compensate for process fluctuations. Based on the error coverage range and the preset frequency calibration accuracy requirements, calculate the required number and distribution of resistance ranges, and determine the corresponding number of digital control code bits; establish a mapping relationship between the digital control code and the resistance ranges, so as to use the mapping relationship to compensate the initial frequency offset caused by process deviations to the range allowed by the frequency calibration accuracy requirements.

15. The parameter optimization method according to claim 11, characterized in that, The step of converting the deviation between the measured common-mode bandwidth and the target common-mode bandwidth into a digital control signal includes: In chip initialization or calibration mode, a test excitation signal is injected into the input of the common-mode calibration filter, and the frequency response characteristics of the output are monitored to obtain the measured bandwidth. Calculate the difference between the measured bandwidth and the target bandwidth. If the difference exceeds the preset frequency tolerance range, read the pre-stored digital control mapping strategy from the on-chip non-volatile memory to determine the direction and step size of the resistance adjustment. The digital control code is updated according to the direction and step size, the switchable branch state in the adjustable resistor array is switched, the equivalent time constant of the common mode calibration filter is dynamically changed until the measured bandwidth falls within the range allowed by the frequency calibration accuracy requirement, and the finally locked digital control code is saved as the working configuration.

Images