Low noise misadjustment calibration comparator and successive approximation register analog-to-digital converter
By designing a low-noise offset calibration comparator and utilizing the collaborative work of the differential input module, latch storage module, offset calibration module, and logic control module to dynamically adjust the compensation current, the problems of high comparator noise and input offset voltage are solved, achieving high-precision and low-power signal decision.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LINGYANGE SEMICONDUCTOR, INC
- Filing Date
- 2026-05-27
- Publication Date
- 2026-06-23
AI Technical Summary
The comparators in the existing technology have high noise, which makes it difficult to meet the signal decision requirements of medium and high precision SAR ADCs. At the same time, the inherent input offset voltage of the comparator can easily lead to signal decision deviation and affect the conversion accuracy.
Design a low-noise offset calibration comparator, including a differential input module, a latch storage module, an offset calibration module, and a logic control module. Through closed-loop coordination between the offset calibration module and the logic control module, the compensation current is dynamically adjusted to offset the input offset voltage.
It effectively improves the accuracy of signal decision-making, meets the accuracy requirements of medium- and high-precision SAR ADCs, and eliminates the need for an additional preamplifier, making it suitable for the low-power consumption requirements of portable devices.
Smart Images
Figure CN122268366A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of circuit technology, and in particular to a low-noise offset calibration comparator and a successive approximation register-type analog-to-digital converter. Background Technology
[0002] In the signal conversion chain of a Successive Approximation Register Analog-to-Digital Converter (SAR ADC), the comparator, as the core decision unit in the field of pulse signal processing, is the core device used to realize the conversion of analog signals to digital signals. Its performance directly determines the conversion accuracy, response speed and noise suppression capability of the SAR ADC.
[0003] In related technologies, the comparators used in analog-to-digital converters have relatively high noise, making it difficult to meet the signal decision requirements of medium-to-high precision SAR ADCs. At the same time, the inherent input offset voltage of the comparator can easily lead to signal decision deviation, affecting the conversion accuracy. Summary of the Invention
[0004] To overcome the problems existing in related technologies, this disclosure provides a low-noise offset calibration comparator and a successive approximation register-type analog-to-digital converter.
[0005] According to a first aspect of the present disclosure, a low-noise offset calibration comparator is provided for use in a successive approximation register-type analog-to-digital converter, the comparator comprising: The differential input module is used to receive differential input signals and convert them into differential voltage signals; The lock storage module has its input terminal connected to the output terminal of the differential input module, which is used to amplify the differential voltage signal and generate a digital output signal; An offset calibration module, the output of which is connected to the compensation terminal of the differential input module, is used to dynamically adjust the compensation current to offset the input offset voltage of the comparator; The logic control module has its input terminal connected to the output terminal of the lock storage module and its output terminal connected to the control terminal of the offset calibration module. It is used to control the working state of the offset calibration module bit by bit according to the digital output signal.
[0006] In some embodiments, the differential input module includes a differential input transistor pair, a tail current source, a clock reset transistor pair, and a compensation current transistor pair; The two control terminals of the differential input transistor pair are the differential input signal receiving terminals of the comparator. The two input terminals are respectively connected to the two output nodes of the differential input module, and the two output terminals are connected to the tail current source. The control terminal of the tail current source is controlled by a clock signal. Its input terminal is connected to the output terminal of the differential input transistor pair, and its output terminal is grounded. It is used to provide bias current for the differential input transistor pair. The two control terminals of the clock reset transistor pair are controlled by the clock signal, the two input terminals are connected to the power supply, and the two output terminals are connected one-to-one with the two output nodes of the differential input module, which are used to reset the two output nodes to the power supply voltage of the power supply respectively. The two input terminals of the compensation current transistor pair are connected one-to-one with the two input terminals of the differential input transistor pair, and the two output terminals are respectively connected to the common connection node of the differential input transistor pair and the tail current source to inject compensation current into the differential input module; the control terminal of one transistor in the compensation current transistor pair is connected to a fixed reference voltage, and the control terminal of the other transistor serves as the compensation terminal of the differential input module and is connected to the output terminal of the offset calibration module.
[0007] In some embodiments, the latch storage module includes a cross-coupled latch unit, a dynamic input transistor pair, and a node reset transistor pair; The two control terminals of the dynamic input transistor pair are connected one-to-one with the two output nodes of the differential input module. Both input terminals are connected to the power supply. The two output terminals are connected one-to-one with the two latch input nodes of the cross-coupled latch unit, which are used to provide dynamic bias current for the cross-coupled latch unit. The cross-coupled latch unit is used to amplify the differential voltage signal at the latch input node and generate the digital output signal; The two control terminals of the node reset transistor pair are connected one-to-one with the two output nodes of the differential input module, the two input terminals are connected one-to-one with the two latch input nodes, and the two output terminals are grounded, which is used to reset the latch input nodes to a preset level.
[0008] In some embodiments, the cross-coupled latch unit is a latch unit based on a complementary architecture of PMOS and NMOS transistors.
[0009] In some embodiments, the offset calibration module includes an N-bit capacitor array and a pre-charged transistor; The N-bit capacitor array is composed of multiple capacitors. Its signal output terminal is connected to the compensation terminal of the differential input module, its control terminal is connected to the output terminal of the logic control module, and its charging terminal is connected to the output terminal of the pre-charge tube. The control terminal of the pre-charge tube is controlled by a calibration clock signal, the input terminal is connected to a fixed reference voltage, and the output terminal is connected to the charging terminal of the N-bit capacitor array, pre-charging the N-bit capacitor array to the fixed reference voltage.
[0010] In some embodiments, when the comparator has an input offset voltage, the multiple capacitors in the N-bit capacitor array are turned on bit by bit.
[0011] In some embodiments, the logic control module includes a shift register and an N-bit AND gate array; The output of the shift register is sequentially connected to the N first inputs of the N-bit AND gate array to generate an N-bit serial shift high-level signal to activate the N-bit AND gate array bit by bit. The second input terminal of the N-bit AND gate array is connected to the digital signal output terminal of the lock storage module, and the N output terminals of the N-bit AND gate array are connected one-to-one with the N control terminals of the N-bit capacitor array in the offset calibration module.
[0012] In some embodiments, when the shift high-level signal output by the shift register is valid, the output signal of the corresponding AND gate in the N-bit AND gate array is determined by the digital output signal of the latch storage module, and is used to control the conduction or disconnection of the corresponding bit capacitor switch in the offset calibration module.
[0013] In some embodiments, the logic control module is a turn-off structure, and the logic control module is in a turn-off state after the comparator completes the offset calibration.
[0014] According to a second aspect of the present disclosure, a successive approximation register-type analog-to-digital converter is provided, including a low-noise offset calibration comparator as described in the first aspect.
[0015] The technical solutions provided in this disclosure may have the following beneficial effects: The low-noise offset calibration comparator provided in this embodiment includes: a differential input module, a latch storage module, an offset calibration module, and a logic control module. The differential input module receives a differential input signal and converts it into a differential voltage signal. The latch storage module, with its input connected to the output of the differential input module, amplifies the differential voltage signal and generates a digital output signal. The offset calibration module, with its output connected to the compensation terminal of the differential input module, dynamically adjusts the compensation current to compensate for the comparator's input offset voltage. The logic control module, with its input connected to the output of the latch storage module and its output connected to the control terminal of the offset calibration module, controls the operating state of the offset calibration module bit by bit according to the digital output signal.
[0016] The solution provided in this disclosure dynamically adjusts the compensation current through closed-loop coordination between the offset calibration module and the logic control module, effectively offsetting the comparator input offset voltage, improving the accuracy of signal decision, and meeting the accuracy requirements of medium- and high-precision SAR ADCs.
[0017] Furthermore, the solution provided in this disclosure does not require an additional preamplifier, and can achieve low-noise signal processing through module collaborative optimization. At the same time, the logic control module can operate on demand, avoiding continuous power consumption loss and adapting to the low power consumption requirements of portable devices. Attached Figure Description
[0018] Figure 1 A schematic diagram of the architecture of a low-noise offset calibration comparator is shown in an embodiment of this disclosure.
[0019] Figure 2 The circuit structure of a low-noise offset calibration comparator is shown in an embodiment of this disclosure.
[0020] Figure 3 A schematic diagram of the structure of a logic control module in an embodiment of this disclosure is shown.
[0021] Figure 4 A schematic diagram of the timing signals of the comparator in an embodiment of this disclosure is shown.
[0022] Figure 5 A schematic diagram of the simulation results of the comparator structure in the relevant technology is shown.
[0023] Figure 6 A schematic diagram showing the simulation results of the comparator structure in an embodiment of this disclosure is provided. Detailed Implementation
[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0025] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0026] With the increasing prevalence of portable medical devices (such as wearable health monitoring devices, portable blood glucose meters, and handheld ultrasound devices) and IoT terminals, the market demand for high precision and low power consumption in successive approximation register-type analog-to-digital converters (SAR ADCs) is becoming increasingly urgent. As a core component for analog-to-digital signal conversion, the conversion accuracy of SAR ADCs directly determines the reliability of scenarios such as physiological signal acquisition and environmental data monitoring, while power consumption affects the battery life of portable devices and is a key factor restricting the practicality of these devices.
[0027] In the signal conversion chain of a SAR ADC, the comparator is the core decision unit, and the two have an inseparable collaborative relationship: the SAR ADC generates a reference voltage through a Capacitive Digital-to-Analog Converter (CDAC), and the comparator is responsible for comparing the input analog signal bit by bit with the reference voltage output by the CDAC, and outputting a digital decision result. This result is fed back to the logic control unit of the SAR ADC to guide the next round of reference voltage adjustment until full-precision conversion is completed. It can be said that the noise level, offset voltage magnitude, and power consumption of the comparator directly determine the conversion accuracy, response speed, and endurance of the SAR ADC.
[0028] However, existing comparators have significant drawbacks and are difficult to adapt to the low-power requirements of medium- and high-precision SAR ADCs: although traditional latch-structure comparators have high-speed decision characteristics, their noise levels are as high as millivolts (mV), which cannot meet the low-noise requirements of 12-bit and higher precision SAR ADCs; to reduce noise, existing solutions usually add a preamplifier, but this will significantly increase static power consumption, which violates the original intention of low-power design for portable devices; at the same time, due to process deviations and differences in device parameter matching, comparators are prone to generating inherent input offset voltages, resulting in signal decision deviations, and existing offset calibration solutions often have problems such as high power consumption, high implementation complexity, or additional power loss after calibration.
[0029] Therefore, please refer to Figure 1 , Figure 1 A schematic diagram of the architecture of a low-noise offset calibration comparator according to an embodiment of this disclosure is shown. Figure 1 As shown, the low-noise offset calibration comparator in this embodiment includes: a differential input module 100, a latch storage module 200, an offset calibration module 300, and a logic control module 400.
[0030] The differential input module 100 is used to receive differential input signals and convert them into differential voltage signals.
[0031] The lock storage module 200 has its input terminal connected to the output terminal of the differential input module 100, and is used to amplify the differential voltage signal and generate a digital output signal.
[0032] Offset calibration module 300, whose output is connected to the compensation terminal of differential input module 100, is used to dynamically adjust the compensation current to offset the input offset voltage of the comparator.
[0033] The logic control module 400 has its input terminal connected to the output terminal of the lock storage module 200 and its output terminal connected to the control terminal of the offset calibration module 300. It is used to control the working state of the offset calibration module 300 bit by bit according to the digital output signal.
[0034] Specifically, the differential input module 100 receives the differential input signal and converts it into a stable differential voltage signal, providing a basis for subsequent amplification and decision-making. The output of the differential input module 100 is directly connected to the input of the latch storage module 200 to ensure distortion-free transmission of the differential voltage signal.
[0035] The input terminal of the latch storage module 200 is connected to the output terminal of the differential input module 100. After receiving the differential voltage signal, it amplifies the weak differential signal at high speed through the internal positive feedback mechanism and converts it into a digital output signal, thus completing the core conversion from analog signal to digital signal.
[0036] The output of the offset calibration module 300 is connected to the compensation terminal of the differential input module 100, and is used to dynamically adjust the compensation current output to the differential input module 100 to cancel the input offset voltage of the comparator through current compensation. The control terminal of the offset calibration module 300 is connected to the output of the logic control module 400, and receives the bit-by-bit control signals from the logic control module 400 to achieve precise control of the calibration process.
[0037] The input terminal of the logic control module 400 is connected to the output terminal of the lock storage module 200. It receives digital output signals and generates bit-by-bit control signals according to the logic state of the signals. The signals are then output to the control terminal of the offset calibration module 300 to achieve orderly control of the calibration process.
[0038] Through the coordinated operation of the above modules, the comparator provided in this disclosure has the ability to perform offset calibration and signal conversion simultaneously, ensuring low noise and high accuracy in signal conversion while achieving accurate compensation of offset voltage.
[0039] Specifically, during the signal conversion stage, the differential input module 100 receives the differential input signal transmitted by the SAR ADC and converts the analog signal into a differential voltage signal through the signal conversion function of the internal differential input transistor pair. The differential voltage signal is transmitted to the latching module 200, which rapidly amplifies the weak differential signal through the positive feedback of the cross-coupled latch structure, converting it into a clear high and low level digital output signal.
[0040] During the offset calibration phase, the logic control module 400 receives the digital output signal from the latch storage module 200 and determines whether the current comparator has an input offset voltage through the logic operation of the internal shift register and the N-bit AND gate array. If the digital output signal has a fixed deviation (such as outputting a fixed level when there is no input signal), it is determined that there is an offset voltage and the calibration process is started.
[0041] The calibration process is as follows: The logic control module 400 generates bit-by-bit control signals and outputs them to the control terminal of the offset calibration module 300, which controls the offset calibration module 300 to adjust the compensation current output to the differential input module 100 bit by bit. In the initial state, the calibration module outputs a reference compensation current. The logic control module 400 adjusts the magnitude and direction of the current step by step according to the feedback signal from the latch storage module 200 until the deviation of the digital output signal is eliminated.
[0042] After calibration, the logic control module 400 stops outputting control signals, and the offset calibration module 300 maintains the current compensation current output state, or shuts down unnecessary working units according to design requirements to avoid additional power consumption.
[0043] Next, we will combine Figure 2 This document details the circuit structure of the low-noise offset calibration comparator provided in this disclosure. Please refer to [link / reference]. Figure 2 , Figure 2 A schematic diagram of the circuit structure of a low-noise offset calibration comparator according to an embodiment of the present disclosure is shown.
[0044] like Figure 2 As shown, in some embodiments, the differential input module includes a differential input transistor pair (M1, M2), a tail current source (M5), a clock reset transistor pair (M3, M4), and a compensation current transistor pair (Mc1, Mc2).
[0045] Among them, the two control terminals of the differential input transistor pair (M1, M2) are the differential input signal receiving terminals of the comparator. The two input terminals are respectively connected to the two output nodes of the differential input module, and the two output terminals are connected to the tail current source.
[0046] The control terminal of the tail current source (M5) is controlled by a clock signal. Its input terminal is connected to the output terminal of the differential input transistor pair (M1, M2), and its output terminal is grounded. It is used to provide bias current for the differential input transistor pair (M1, M2).
[0047] The two control terminals of the clock reset transistor pair (M3, M4) are controlled by the clock signal (CLK), the two input terminals are connected to the power supply, and the two output terminals are connected to the two output nodes of the differential input module (i.e., Figure 2 The intermediate differential input module is used to connect the Di+ and Di- nodes one-to-one, and is used to reset the two output nodes to the power supply voltage (VDD).
[0048] The two input terminals of the compensation current transistor pair (Mc1, Mc2) are connected one-to-one with the two input terminals (M1, M2) of the differential input transistor pair. The two output terminals are respectively connected to the common node of the differential input transistor pair (M1, M2) and the tail current source (M5) to inject compensation current into the differential input module. The control terminal of one of the transistors in the compensation current transistor pair (Mc1, Mc2) is connected to the fixed reference voltage, and the control terminal of the other transistor serves as the compensation terminal of the differential input module and is connected to the output terminal of the offset calibration module.
[0049] The fixed reference voltage refers to the voltage that remains unchanged throughout the entire operation of the comparator, regardless of the external environment or operating state. It is used to provide a fixed gate bias for the compensation transistor Mc1 and to set the reference compensation current.
[0050] For example, the differential input transistor pair (M1, M2) can be NMOS transistors, with their gates connected to the differential input signals Vin- and Vin+ respectively, serving as the differential input signal receiving terminals of the comparator; their drains are connected to the output nodes Di- and Di+ of the differential input module, and their sources are connected to the input terminal of the tail current source (M5), forming a current convergence node. As an NMOS differential pair, after receiving the differential analog signals Vin+ and Vin-, M1 and M2 convert the analog signals into voltage signals (i.e., differential voltage signals) at the Di+ and Di- nodes through current changes. Their symmetrical matching design can effectively suppress common-mode noise and ensure the linearity of signal conversion.
[0051] For example, the tail current source (M5) can be an NMOS transistor whose gate is controlled by the clock signal CLK to achieve timing synchronization control; the drain is connected to the source of M1 and M2 to provide a stable bias current for the differential input transistor pair (M1, M2); the source is grounded (VSS) to form a complete current loop.
[0052] The clock reset transistor pair (M3, M4) can be PMOS transistors, with their gates connected to the clock signal CLK for synchronous reset. Their sources are both connected to the power supply voltage VDD to obtain a high-potential power supply. The output terminals (drains) are connected to the Di- and Di+ nodes respectively. When the clock signal CLK is low, M3 and M4 are turned on, quickly charging the parasitic capacitance at the Di+ and Di- nodes to VDD, completing the level reset of the output nodes. When CLK is high, they are turned off, not interfering with the signal conversion process. The reset function ensures that before each signal conversion, the Di+ and Di- nodes are at a unified reference level, avoiding decision deviations caused by residual voltage.
[0053] The compensation current transistor pair (Mc1, Mc2) can be NMOS transistors, with their drains connected to the drains of M1 (Di-) and M2 (Di+) respectively, and their sources connected to the common node of M1, M2, and M5 respectively, precisely injecting compensation current into the differential input module. The gate of Mc1 is connected to a fixed reference voltage Vb to set the common-mode compensation reference, and the gate of Mc2 serves as the compensation terminal of the differential input module, connected to the output terminal of the offset calibration module to receive the calibration voltage signal. During operation, Mc1 provides a fixed reference compensation current, and Mc2 dynamically adjusts its conduction level by adjusting the gate voltage Vc, thereby flexibly adjusting the magnitude of the output compensation current. When the comparator has an input offset voltage, the change in Vc voltage causes the compensation current injected by Mc2 to form a difference with the fixed current of Mc1. This difference current can accurately cancel the offset current of the differential input transistor pair (M1, M2), ultimately achieving efficient compensation of the input offset voltage.
[0054] The differential input module operates in strict synchronization with the clock signal CLK and the calibration clock signal CLK_CAL. During the reset phase, CLK is low, the clock reset transistor pair (M3, M4) is turned on, the Di+ and Di- nodes are reset to VDD, the tail current source (M5) is turned off, the differential input transistor pair (M1, M2) has no bias current, and the compensation current transistor pair (Mc1, Mc2) is in standby mode. During the signal conversion phase, CLK goes high, M3 and M4 are turned off, M5 is turned on, and M1 and M2 acquire stable bias current to convert Vin+ and Vin- into differential voltage signals Di+ and Di-. These signals are transmitted to the latching module in real time.
[0055] In some embodiments, the latch storage module includes cross-coupled latch units (M6, M7, M8, M9, M10, M11), dynamic input transistor pairs (M14, M15), and node reset transistor pairs (M12, M13).
[0056] Among them, the two control terminals of the dynamic input transistor pair (M14, M15) are connected one-to-one with the two output nodes (Di+, Di-) of the differential input module. Both input terminals are connected to the power supply, and the two output terminals are connected one-to-one with the two latching input nodes (Xi+, Xi-) of the cross-coupled latching unit (M6, M7, M8, M9, M10, M11) to provide dynamic bias current for the cross-coupled latching unit (M6, M7, M8, M9, M10, M11).
[0057] The cross-coupled latch units (M6, M7, M8, M9, M10, M11) are used to amplify the differential voltage signals at the latch input nodes (Xi+, Xi-) and generate digital output signals.
[0058] The two control terminals of the node reset transistor pair (M12, M13) are connected one-to-one with the two output nodes (Di+, Di-) of the differential input module, and the two input terminals are connected one-to-one with the two latch input nodes (Xi+, Xi-). The two output terminals are grounded to reset the latch input nodes (Xi+, Xi-) to the preset level.
[0059] For example, the dynamic input transistor pair (M14, M15) can be PMOS transistors. The two gates are connected one-to-one with the two output nodes (Di+, Di-) of the differential input module to receive the differential voltage signal in real time. Both sources are connected to the power supply voltage VDD to obtain a stable power supply. The two drains are connected one-to-one with the two latching input nodes (Xi+, Xi-) of the cross-coupled latch unit, forming a transmission path for the signal and bias current. When there is a difference in the differential voltage signal output by the differential input module, the conduction current of the dynamic input transistor pair (M14, M15) will differ, thereby injecting dynamic bias current into the Xi+ and Xi- nodes.
[0060] The cross-coupled latch unit can adopt a complementary architecture based on PMOS and NMOS transistors, including PMOS transistors M10 and M11 and NMOS transistors M6, M7, M8, and M9. Specifically, the source of M10 is connected to the latch input node Xi+, the drain is connected to the drains of both M6 and M8, and the gate is connected to both the gate of M6 and the digital signal output terminal CMP_OUT+. The source of M11 is connected to the latch input node Xi-, the drain is connected to the drains of both M7 and M9, and the gate is connected to both the gate of M7 and the digital signal output terminal CMP_OUT-. CMP_OUT+ is located between the drains of M11 and M7, and CMP_OUT- is located between the drains of M10 and M6, forming a cross-coupled signal feedback path. The sources of M6 and M8 are connected to ground (VSS). The gate of M6 is connected to the gate of M10 and CMP_OUT+. The gate of M8 is directly connected to the output node Di+ of the differential input module. The sources of M7 and M9 are connected to ground (VSS). The gate of M7 is connected to the gate of M11 and CMP_OUT-. The gate of M9 is directly connected to the output node Di- of the differential input module.
[0061] The node reset transistor pair (M12, M13) can be NMOS transistors. Their two gates are connected one-to-one with the two output nodes (Di+, Di-) of the differential input module to receive synchronization control signals. Their two drains are connected one-to-one with the two latch input nodes (Xi+, Xi-) of the cross-coupled latch unit, and their two sources are grounded, forming a reset discharge path. The core function of the node reset transistor pair (M12, M13) is to eliminate residual voltage deviations at the Xi+ and Xi- nodes: when the differential input module is in the reset phase (Di+ and Di- nodes are high), the gates of M12 and M13 are turned on by the high level, and the Xi+ and Xi- nodes quickly discharge to a low potential through their sources. This ensures that the latch input nodes are at a uniform reference before each round of signal amplification, avoiding comparator offset caused by residual voltage and improving the consistency of the comparator's decision results.
[0062] During operation, the timing of the latching large-scale module and the differential input module is strictly synchronized. During the reset phase, nodes Di+ and Di- are at a high level, the node reset transistor pair (M12, M13) is turned on, and nodes Xi+ and Xi- discharge to VSS, putting the cross-coupled latch unit in standby mode. During the signal amplification phase, nodes Di+ and Di- output differential voltage signals, and the dynamic input transistor pair (M14, M15) injects dynamic bias current according to the signal difference, forming a differential potential between nodes Xi+ and Xi-, triggering positive feedback amplification of the cross-coupled latch unit. During the latching phase, the cross-coupled structure quickly completes signal decision, outputs a stable digital signal, and maintains this state until the next reset signal arrives, ensuring the stability of the digital output.
[0063] In some embodiments, the offset calibration module includes an N-bit capacitor array and a pre-charged tube.
[0064] The N-bit capacitor array consists of multiple capacitors. Its signal output terminal is connected to the compensation terminal of the differential input module, its control terminal is connected to the output terminal of the logic control module, and its charging terminal is connected to the output terminal of the pre-charge tube. N is a positive integer, corresponding to the number of columns in the capacitor array.
[0065] The control terminal of the precharge tube is controlled by the calibration clock signal, the input terminal is connected to a fixed reference voltage, and the output terminal is connected to the charging terminal of the N-bit capacitor array, precharging the N-bit capacitor array to the fixed reference voltage.
[0066] Specifically, the pre-charge transistor can be a PMOS transistor, whose gate is controlled by the calibration clock signal CLK_CAL; its source is connected to a fixed reference voltage to obtain a stable reference potential; and its drain is directly connected to the charging terminal of the N-bit capacitor array to form a pre-charge path. When CLK_CAL is low, M16 is turned on, and the entire capacitor array is quickly pre-charged to the fixed reference voltage, providing a unified reference potential for subsequent calibration; when CLK_CAL is high, M16 is turned off, cutting off the pre-charge path, and the capacitor array locks its current charge state.
[0067] An N-bit capacitor array can include multiple capacitors whose capacitance values are arranged according to binary weights, meaning that the capacitance values of the multiple capacitors are 2 from the most significant bit to the least significant bit. N C0, 2 N-1 C0, ... 2C0, C0. The signal output terminals are directly connected to the compensation terminals of the differential input module (i.e., the gate of the compensation current transistor Mc2) to output dynamically adjusted calibration voltages. The control terminals are divided into N paths, each corresponding to one of the N output terminals of the logic control module, receiving bit-by-bit control signals. The charging terminal is a common port, connected to the output terminal of the pre-charge transistor M16, receiving the pre-charge voltage. One end of each capacitor is connected to the charging terminal, and the other end is grounded (VSS) through an independent switching transistor (C0 to CN). The control terminal of the switching transistor is the corresponding bit control terminal of the capacitor array, controlled by the bit-by-bit control signals of the logic control module. When the control signal is valid, the corresponding branch capacitor is connected to ground and participates in the adjustment of the total capacitance value; when the control signal is invalid, the corresponding branch capacitor only maintains the pre-charge charge and does not participate in the adjustment.
[0068] It is understood that the capacitance value in an N-bit capacitor array can be arbitrary. For example, the capacitance values of multiple capacitors can decrease sequentially from the most significant bit to the least significant bit, or they can be set to be the same; this disclosure does not limit this. When the capacitance values of multiple capacitors are arranged according to binary weights, the adjustment accuracy of the offset calibration module can be effectively improved.
[0069] During the pre-charging phase, CLK_CAL is low, M16 is on, and the N-bit capacitor array is pre-charged to a fixed reference voltage. Except for the highest-order capacitor, the switching transistors of all other capacitors in the N-bit array are off, and the Vc node potential equals the fixed reference voltage. During the calibration and adjustment phase, CLK_CAL goes high, M16 is off, and the logic control module outputs control signals bit by bit based on the digital signal (reflecting the offset voltage state) from the latched large module, sequentially controlling the switching transistors of each capacitor in the N-bit capacitor array to turn on or off. Each time a capacitor is turned on, the total capacitance of the capacitor array changes. According to the principle of charge conservation, this change in total capacitance will cause a change in the Vc voltage. For example, increasing the total capacitance will cause a decrease in the Vc voltage at the signal output terminal. By adjusting the total capacitance of the capacitor array bit by bit, the magnitude of the Vc voltage can be precisely controlled, thereby controlling the conduction level of Mc2 and the compensation current.
[0070] In other words, when the comparator has an input offset voltage, multiple capacitors in the N-bit capacitor array can be turned on bit by bit, thereby achieving dynamic cancellation of the comparator's input offset voltage.
[0071] Please refer to the following. Figure 3 , Figure 3 A schematic diagram of the structure of a logic control module according to an embodiment of this disclosure is shown. Figure 3 As shown, the logic control module includes a shift register and an N-bit AND gate array.
[0072] The output of the shift register is connected sequentially to the N first inputs of the N-bit AND gate array to generate an N-bit serial shift high-level signal to activate the N-bit AND gate array bit by bit.
[0073] The second input of the N-bit AND gate array is connected to the digital signal output of the latch storage module, and the N outputs of the N-bit AND gate array are connected one-to-one with the N control terminals of the N-bit capacitor array in the offset calibration module.
[0074] For example, the output of the shift register can be divided into N paths, which are sequentially connected to the N first inputs of the N-bit AND gate array to form a transmission path for serial control signals; the second input of the N-bit AND gate array is a common port, which is connected to the digital signal output (CMP_OUT+) of the latch storage module to receive offset state feedback signals in real time; the N outputs of the N-bit AND gate array are connected to the N control terminals of the N-bit capacitor array in the offset calibration module (i.e., the gates of the switching transistors corresponding to each capacitor) to directly output calibration control signals.
[0075] In this embodiment, the shift register can serially shift its output, thereby generating an N-bit serial shift high-level signal. Initially, all outputs of the shift register are low, and the N-bit AND gate array is inactive. When the calibration process begins, driven by the system clock signal, the shift register sequentially sets one output bit to high from the most significant bit to the least significant bit, while keeping the remaining bits low, forming an activation signal. The duration of this shift high-level signal is consistent with the system clock cycle, ensuring that each bit of the AND gate array has sufficient time to complete logical judgments and output control signals.
[0076] The first input of the N-bit AND gate array receives the bit-by-bit high-level activation signal from the shift register, and the second input receives the digital output signal from the latched storage module. If the comparator still has an input offset voltage, CMP_OUT+ remains high; if the offset voltage has been compensated to the preset range, CMP_OUT+ goes low. When the high-level signal of the shift register is shifted to the first input of a bit AND gate, that bit AND gate is activated, and its output state is determined by the CMP_OUT+ signal at the second input.
[0077] For example, when the shift high-level signal output by the shift register is valid, the output signal of the corresponding AND gate in the N-bit AND gate array is determined by the digital output signal of the latch storage module, and is used to control the conduction or disconnection of the corresponding bit capacitor switch in the offset calibration module.
[0078] Specifically, if CMP_OUT+ is high (offset exists), the AND gate outputs a high level, driving the corresponding switching transistor in the N-bit capacitor array to turn on, and the corresponding branch capacitor is connected to the total capacitor circuit; if CMP_OUT+ is low (offset has been eliminated), the AND gate outputs a low level, the corresponding switching transistor is turned off, and the corresponding branch capacitor is no longer connected to the total capacitor circuit.
[0079] In some embodiments, the logic control module is a turn-off structure, and the logic control module is in a turn-off state after the comparator completes the offset calibration.
[0080] This design avoids the logic control module from continuously generating static power consumption when it is idle, and can significantly optimize the overall power consumption performance of the comparator.
[0081] Please refer to the following. Figure 4 , Figure 4 A schematic diagram of the timing signals of the comparator in an embodiment of this disclosure is shown. For example... Figure 4As shown, before calibration begins, the calibration clock signal CLK_CAL, used to control M16, outputs a low level, putting M16 on. Simultaneously, the switching transistor CN corresponding to the highest-order capacitor is turned on, charging the highest-order capacitor to a fixed reference voltage Vb. Subsequently, CLK_CAL outputs a high level, turning off M16 and initiating calibration. During calibration, the switching transistors CN through C0 corresponding to the N capacitors can be sequentially turned on with a high level to change the total capacitance in the capacitor array. This changes the value of Vc according to the principle of charge conservation, thus adjusting the bias current output by Mc2. The final state of which capacitors are on during calibration is determined by the control signal output by the logic control module. Figure 4 The timing sequence of C0 to CN-1 is merely illustrative, and multiple capacitors may be conducting simultaneously at the same time; this disclosure does not limit this. The clock signal CLK is used to control the operation of the comparator, switching back and forth between high and low levels according to a fixed working cycle to reset the comparator and output the comparator result.
[0082] Please compare below. Figure 5 and Figure 6 ,in, Figure 5 The diagram shows a simulation result of the comparator structure in the related technology. Figure 6 A schematic diagram of the simulation results of the comparator structure in this disclosure is shown. Here, Vos is the bias voltage of the set input. The Vos of the conventional comparator structure is set to 3.8mV. The statistical transient simulation results with noise are as follows: Figure 5 As shown, the correct comparison results account for 82.5%. With the comparator structure of this disclosure set to Vos of 0.16mV, the statistical transient simulation results with noise are as follows... Figure 6 As shown, the correct comparison result accounts for 84.5%. In mathematical statistics, we know that 84% is the probability of 1σ. Therefore, the Vos that achieves an accuracy of 84% can be roughly regarded as the equivalent noise of the comparator's output. It can be seen that the comparator provided in this disclosure has high output accuracy.
[0083] Based on the same inventive concept, this disclosure provides a successive approximation register-type analog-to-digital converter, including a low-noise offset calibration comparator as described in the foregoing embodiments.
[0084] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0085] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A low-noise offset calibration comparator, characterized in that, The comparator, applied to a successive approximation register-type analog-to-digital converter, includes: The differential input module is used to receive differential input signals and convert them into differential voltage signals; The lock storage module has its input terminal connected to the output terminal of the differential input module, which is used to amplify the differential voltage signal and generate a digital output signal; An offset calibration module, the output of which is connected to the compensation terminal of the differential input module, is used to dynamically adjust the compensation current to offset the input offset voltage of the comparator; The logic control module has its input terminal connected to the output terminal of the lock storage module and its output terminal connected to the control terminal of the offset calibration module. It is used to control the working state of the offset calibration module bit by bit according to the digital output signal.
2. The comparator according to claim 1, characterized in that, The differential input module includes a differential input transistor pair, a tail current source, a clock reset transistor pair, and a compensation current transistor pair; The two control terminals of the differential input transistor pair are the differential input signal receiving terminals of the comparator. The two input terminals are respectively connected to the two output nodes of the differential input module, and the two output terminals are connected to the tail current source. The control terminal of the tail current source is controlled by a clock signal. Its input terminal is connected to the output terminal of the differential input transistor pair, and its output terminal is grounded. It is used to provide bias current for the differential input transistor pair. The two control terminals of the clock reset transistor pair are controlled by the clock signal, the two input terminals are connected to the power supply, and the two output terminals are connected one-to-one with the two output nodes of the differential input module, which are used to reset the two output nodes to the power supply voltage of the power supply respectively. The two input terminals of the compensation current transistor pair are connected one-to-one with the two input terminals of the differential input transistor pair, and the two output terminals are respectively connected to the common connection node of the differential input transistor pair and the tail current source to inject compensation current into the differential input module; the control terminal of one transistor in the compensation current transistor pair is connected to a fixed reference voltage, and the control terminal of the other transistor serves as the compensation terminal of the differential input module and is connected to the output terminal of the offset calibration module.
3. The comparator according to claim 1, characterized in that, The latch storage module includes a cross-coupled latch unit, a dynamic input transistor pair, and a node reset transistor pair; The two control terminals of the dynamic input transistor pair are connected one-to-one with the two output nodes of the differential input module. Both input terminals are connected to the power supply. The two output terminals are connected one-to-one with the two latch input nodes of the cross-coupled latch unit, which are used to provide dynamic bias current for the cross-coupled latch unit. The cross-coupled latch unit is used to amplify the differential voltage signal at the latch input node and generate the digital output signal; The two control terminals of the node reset transistor pair are connected one-to-one with the two output nodes of the differential input module, the two input terminals are connected one-to-one with the two latch input nodes, and the two output terminals are grounded, which is used to reset the latch input nodes to a preset level.
4. The comparator according to claim 3, characterized in that, The cross-coupled latch unit is a latch unit based on a complementary architecture of PMOS and NMOS transistors.
5. The comparator according to claim 1, characterized in that, The offset calibration module includes an N-bit capacitor array and a pre-charge tube; The N-bit capacitor array is composed of multiple capacitors. Its signal output terminal is connected to the compensation terminal of the differential input module, its control terminal is connected to the output terminal of the logic control module, and its charging terminal is connected to the output terminal of the pre-charge tube. The control terminal of the pre-charge tube is controlled by a calibration clock signal, the input terminal is connected to a fixed reference voltage, and the output terminal is connected to the charging terminal of the N-bit capacitor array, pre-charging the N-bit capacitor array to the fixed reference voltage.
6. The comparator according to claim 5, characterized in that, When the comparator has an input offset voltage, the multiple capacitors in the N-bit capacitor array turn on bit by bit.
7. The comparator according to claim 1, characterized in that, The logic control module includes a shift register and an N-bit AND gate array; The output of the shift register is sequentially connected to the N first inputs of the N-bit AND gate array to generate an N-bit serial shift high-level signal to activate the N-bit AND gate array bit by bit. The second input terminal of the N-bit AND gate array is connected to the digital signal output terminal of the lock storage module, and the N output terminals of the N-bit AND gate array are connected one-to-one with the N control terminals of the N-bit capacitor array in the offset calibration module.
8. The comparator according to claim 7, characterized in that, When the shift high-level signal output by the shift register is valid, the output signal of the corresponding AND gate in the N-bit AND gate array is determined by the digital output signal of the latch storage module, and is used to control the conduction or disconnection of the corresponding bit capacitor switch in the offset calibration module.
9. The comparator according to claim 1, characterized in that, The logic control module is a turn-off structure. After the comparator completes the offset calibration, the logic control module is in a turn-off state.
10. A successive approximation register-type analog-to-digital converter, characterized in that, It includes a low-noise offset calibration comparator as described in any one of claims 1 to 9.