Heterojunction transistor and method of manufacturing the same
By forming convex trenches during the fabrication of heterojunction transistors, the contact area between the collector material layer and the substrate is increased, and the contact resistance and capacitance are reduced. This solves the problem of large parasitic capacitance and resistance, and achieves low parasitic parameters and high power gain at high frequencies.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-23
AI Technical Summary
Existing heterojunction bipolar transistor devices face significant parasitic capacitance and resistance in high-frequency applications, leading to performance bottlenecks and failing to meet the needs of high-frequency communication, sensing, and computing fields.
By using a wet etching process to form a convex second trench in the fabrication method, the contact area between the collector material layer and the substrate is increased, while the contact area between the collector material layer and the base material layer is reduced, thereby reducing the contact resistance and collector junction capacitance.
It achieves low parasitic parameters and high power gain at high frequencies, meeting the needs of high-frequency communication, sensing and computing fields.
Smart Images
Figure CN122269725A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a heterojunction transistor and its fabrication method. Background Technology
[0002] With the rapid development of fifth-generation and future sixth-generation mobile communications, millimeter-wave radar, high-speed optical communications, and other fields, higher requirements are being placed on the frequency characteristics of semiconductor devices. Heterojunction bipolar transistors (HBTs) have become one of the core devices in high-frequency applications due to their advantages such as high current drive capability, high cutoff frequency (fT), and maximum oscillation frequency (fmax).
[0003] Traditional homojunction bipolar transistors (BJTs) are limited in high-frequency applications due to high base resistance and insufficient carrier injection efficiency. In contrast, heterojunction structures, by using different bandgap materials (such as InGaP / GaAs, InP / InGaAs, or SiGe / Si) to form emitter junctions, effectively improve electron injection efficiency and reduce base resistance, thereby significantly improving the frequency characteristics of the device.
[0004] However, as operating frequencies advance towards the hundreds of GHz and even terahertz range, existing HBT devices still face a series of challenges. Parasitic capacitances (such as base-collector capacitance CBC) and parasitic resistances (such as contact resistance and base resistance) have an increasingly significant impact on the maximum oscillation frequency (fmax), becoming a performance bottleneck, especially in high-frequency oscillation and amplification applications. Therefore, there is an urgent need to develop a new type of HBT device that can simultaneously achieve low parasitic parameters and high power gain at high frequencies to meet the needs of future high-frequency communication, sensing, and computing fields. Summary of the Invention
[0005] The purpose of this invention is to provide a heterojunction transistor and its fabrication method to solve the problem that existing HBT devices have large parasitic capacitances (such as base-collector capacitance CBC) and parasitic resistances (such as contact resistance and base resistance), which prevent existing HBT devices from meeting the needs of high-frequency communication, sensing and computing fields.
[0006] To address the aforementioned technical problems, this application provides a method for fabricating a heterojunction transistor, comprising:
[0007] A substrate is provided on which a first dielectric layer, a second dielectric layer and a hard mask layer are sequentially formed;
[0008] The hard mask layer, the second dielectric layer, and the first dielectric layer are etched and stopped on the substrate surface to form a first trench;
[0009] A wet etching process is used to continue to etch laterally the first dielectric layer of a first width and the second dielectric layer of a second width on the sidewall of the first trench to form a second trench, wherein the first width is greater than the second width.
[0010] A current collector material layer is formed, and the current collector material layer fills the second trench;
[0011] After removing the hard mask layer and the collector material layer that extend beyond the surface of the second dielectric layer, the second trench becomes convex in shape; and
[0012] A base material layer is formed, which covers the current collector material layer at the top of the second trench and partially covers the second dielectric layer.
[0013] Optionally, in the method for fabricating the heterojunction transistor, the first dielectric layer is a TEOS layer.
[0014] Optionally, in the method for fabricating the heterojunction transistor, the first dielectric layer is formed using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).
[0015] Optionally, in the fabrication method of the heterojunction transistor, the second dielectric layer is a high-temperature oxide layer.
[0016] Optionally, in the method for fabricating the heterojunction transistor, the second dielectric layer is formed by low-pressure chemical vapor deposition or by thermal oxidation.
[0017] Optionally, in the method for fabricating the heterojunction transistor, during the process of using a wet etching process to continue laterally etching the first dielectric layer of a first width and the second dielectric layer of a second width on the sidewall of the first trench to form a second trench, the wet etching reagent is diluted hydrofluoric acid.
[0018] Optionally, in the method for fabricating the heterojunction transistor, the collector material layer is made of monocrystalline silicon or polycrystalline silicon.
[0019] Optionally, in the fabrication method of the heterojunction transistor, the base material layer is made of silicon germanide.
[0020] Optionally, in the method for fabricating the heterojunction transistor, after forming the base material layer, the method further includes:
[0021] An emitter material layer is formed, the emitter material layer covering a first portion of the surface of the base material layer;
[0022] An outer base region is formed, which covers a second portion of the surface of the base material layer on both sides of the emitter material layer;
[0023] An interlayer dielectric layer is formed, which covers the outer base region, the emitter material layer, the exposed second dielectric layer, and the exposed substrate;
[0024] Multiple conductive plugs are formed, each of which penetrates the interlayer dielectric layer and contacts the emitter material layer and the outer base region, respectively.
[0025] Optionally, in the method for fabricating the heterojunction transistor, a chemical mechanical polishing process is used to remove the hard mask layer and the collector material layer that extend beyond the surface of the second dielectric layer.
[0026] On the other hand, this application also provides a heterojunction transistor, comprising:
[0027] A substrate, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the substrate;
[0028] The second trench is located in the second dielectric layer and the first dielectric layer, wherein the second trench is convex in shape, and the width of the second trench in the first dielectric layer is greater than the width of the second trench in the second dielectric layer.
[0029] A current collector material layer, wherein the current collector material layer fills the second trench;
[0030] A base material layer that covers the current collector material layer at the top of the second trench and partially covers the second dielectric layer.
[0031] In summary, this application provides a heterojunction transistor and its fabrication method. In the fabrication method, during the wet etching process of laterally etching the first and second dielectric layers on the sidewalls of the first trench, the different etching rates of the wet etching reagent on the first and second dielectric layers are utilized. The etching rate of the first dielectric layer is greater than that of the second dielectric layer, resulting in the removal of more of the first dielectric layer than the second dielectric layer. This forms a convex second trench, thereby increasing the contact area between the subsequently formed collector material layer and the substrate to reduce contact resistance. Simultaneously, it reduces the contact area between the subsequently formed collector material layer and the base material layer to reduce the collector junction capacitance, thus jointly increasing the frequency of the heterojunction transistor. This enables the transistor to simultaneously achieve low parasitic parameters and high power gain at high frequencies, meeting the needs of high-frequency communication, sensing, and computing fields. Attached Figure Description
[0032] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0033] Figure 1 This is a flowchart of a method for fabricating a heterojunction transistor according to an embodiment of the present invention.
[0034] Figures 2-8 This is a schematic diagram of the semiconductor structure in each process step of fabricating a heterojunction transistor according to an embodiment of the present invention.
[0035] The reference numerals in the attached figures are explained as follows:
[0036] 10-Substrate, 11-Collector lead-out region, 20-First dielectric layer, 30-Second dielectric layer, 40-Hard mask layer, 51-First trench, 52-Second trench, 60-Collector material layer, 70-Base material layer, 71-Outer base region, 80-Emitter material layer, 90-Interlayer dielectric layer, 91-First conductive plug, 92-Second conductive plug, 93-Third conductive plug. Detailed Implementation
[0037] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may have different focuses and may sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0038] This application provides a method for fabricating a heterojunction transistor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a heterojunction transistor according to an embodiment of the present invention. The method for fabricating the heterojunction transistor includes:
[0039] Step S1: Provide a substrate on which a first dielectric layer, a second dielectric layer and a hard mask layer are sequentially formed;
[0040] Step S2: Etch the hard mask layer, the second dielectric layer and the first dielectric layer and stop at the substrate surface to form a first trench;
[0041] Step S3: Using a wet etching process, continue to etch the first dielectric layer of the first width and the second dielectric layer of the second width on the sidewall of the first trench laterally to form a second trench, wherein the first width is greater than the second width;
[0042] Step S4: Form a current collector material layer, the current collector material layer filling the second trench;
[0043] Step S5: Remove the hard mask layer and the current collector material layer extending beyond the surface of the second dielectric layer. At this point, the second trench is convex in shape; and
[0044] Step S6: Form a base material layer, which covers the current collector material layer at the top of the second trench and partially covers the second dielectric layer.
[0045] For details, please refer to Figures 2-8 , Figures 2-8 This is a schematic diagram of the semiconductor structure in each process step of fabricating a heterojunction transistor according to an embodiment of the present invention.
[0046] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the hard mask layer according to an embodiment of this application. A substrate 10 is provided, on which a first dielectric layer 20, a second dielectric layer 30 and a hard mask layer 40 are sequentially formed.
[0047] Preferably, the first dielectric layer 20 is a TEOS layer.
[0048] Furthermore, the first dielectric layer 20 is formed using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).
[0049] In this embodiment, the thickness of the first dielectric layer 20 is 200 angstroms to 600 angstroms.
[0050] Preferably, the second dielectric layer 30 is a high-temperature oxide layer (HTO).
[0051] In this embodiment, the second dielectric layer 30 is formed by thermal oxidation process at a temperature of 800°C to 1200°C.
[0052] In this embodiment, the thickness of the second dielectric layer 30 is 200 angstroms to 600 angstroms.
[0053] In another embodiment, the second dielectric layer 30 is formed using a low-pressure chemical vapor deposition process.
[0054] It is worth noting that the density of the second dielectric layer 30 is greater than that of the first dielectric layer 20.
[0055] Furthermore, a collector lead-out region 11 is also formed in the substrate 10, wherein the collector lead-out region 11 is located in the substrate away from the subsequent second trench, and the collector lead-out region 11 is located in a region close to the substrate surface.
[0056] In this embodiment, the hard mask layer 40 is a silicon nitride layer.
[0057] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first trench according to an embodiment of this application. The hard mask layer 40, the second dielectric layer 30 and the first dielectric layer 20 are etched and stopped on the surface of the substrate 10 to form the first trench 52.
[0058] Specifically, a photoresist layer (not shown) is first coated on the hard mask layer 40. Then, a first trench pattern is formed on the photoresist layer by photolithography. Next, the patterned photoresist layer is used as a mask to etch the hard mask layer 40, the second dielectric layer 30 and the first dielectric layer 20 and stop at the surface of the substrate 10 to form the first trench 52. Finally, the patterned photoresist layer is removed by ashing.
[0059] Preferably, a dry etching process is used to etch the hard mask layer 40, the second dielectric layer 30 and the first dielectric layer 20 and stop at the surface of the substrate 10 to form the first trench 52.
[0060] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the second trench in an embodiment of this application. A wet etching process is used to continue to etch the first dielectric layer 20 of the first width and the second dielectric layer 30 of the second width on the sidewall of the first trench 51 to form the second trench 52, wherein the first width is greater than the second width.
[0061] Preferably, in the process of using a wet etching process to continue to laterally etch the first dielectric layer 20 of the first width and the second dielectric layer 30 of the second width on the sidewall of the first trench 51 to form the second trench 52, the wet etching reagent is diluted hydrofluoric acid (DHF).
[0062] The diluted hydrofluoric acid has different etching rates for the second dielectric layer 30 (high-temperature oxide layer) and the first dielectric layer 20 (TEOS layer). Specifically, the etching rate for the first dielectric layer 20 (TEOS layer) is greater than the etching rate for the second dielectric layer 30 (high-temperature oxide layer).
[0063] Preferably, the etching rate of the first dielectric layer 20 (TEOS layer) is 5 times the etching rate of the second dielectric layer 30 (high temperature oxide layer), that is, the ratio of the first width etched by the first dielectric layer 20 to the second width etched away by the second dielectric layer 30 is 5:1.
[0064] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the collector material layer according to an embodiment of this application. The collector material layer 60 is formed, and the collector material layer 60 fills the second trench 52.
[0065] Preferably, the current collector material layer 60 is made of monocrystalline silicon or polycrystalline silicon.
[0066] Preferably, the thickness of the current collector material layer 60 is 400 angstroms to 1200 angstroms.
[0067] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after removing the hard mask layer and collector material layer that extend beyond the surface of the second dielectric layer according to an embodiment of this application. After removing the hard mask layer 40 and the collector material layer 60 that extend beyond the surface of the second dielectric layer 30, the second trench 52 is convex in shape.
[0068] Preferably, the hard mask layer 40 and the current collector material layer 60 extending beyond the surface of the second dielectric layer 30 are removed by chemical mechanical polishing.
[0069] Finally, proceed to step S6: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the base material layer according to an embodiment of this application. The base material layer 70 is formed, which covers the collector material layer 60 at the top of the second trench 52 and a portion of the second dielectric layer 30.
[0070] In this embodiment, the base material layer 70 is made of silicon germanide.
[0071] Preferably, the thickness of the base material layer 70 is 100 angstroms to 500 angstroms.
[0072] Further reference Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the first to third conductive plugs according to an embodiment of this application. After forming the base material layer 70, the method for fabricating the heterojunction transistor may further include:
[0073] Step S7: Form an emitter material layer 80, which covers a first portion of the surface of the base material layer 70;
[0074] Step S8: Form an outer base region 71, which covers the second portion of the surface of the base material layer 70 on both sides of the emitter material layer 80;
[0075] Step S9: Form an interlayer dielectric layer 90, which covers the outer base region 71, the emitter material layer 80, the exposed second dielectric layer 30, and the exposed substrate 10;
[0076] Step S10: Form a first conductive plug 91, a second conductive plug 92, and a third conductive plug 93. The first conductive plug 91 penetrates the interlayer dielectric layer 90 and contacts the emitter material layer 80; the second conductive plug 92 penetrates the interlayer dielectric layer 90 and contacts the outer base region 71; the third conductive plug 93 penetrates the interlayer dielectric layer 90, the second dielectric layer 30, and the first dielectric layer 20 and contacts the collector lead-out region 11.
[0077] In this application, during the wet etching process of laterally etching the first dielectric layer and the second dielectric layer on the sidewall of the first trench, the different etching rates of the first dielectric layer and the second dielectric layer by the wet etching reagent are utilized. The etching rate of the first dielectric layer is greater than that of the second dielectric layer, resulting in more of the first dielectric layer being etched away than the second dielectric layer. This forms a convex-shaped second trench, thereby increasing the contact area between the subsequently formed collector material layer and the substrate to reduce the contact resistance. At the same time, it reduces the contact area between the subsequently formed collector material layer and the base material layer to reduce the collector junction capacitance. This together increases the frequency of the heterojunction transistor, enabling low parasitic parameters and high power gain at high frequencies, meeting the needs of fields such as high-frequency communication, sensing, and computing.
[0078] Based on the same inventive concept, this application also provides a heterojunction transistor, see reference. Figure 7 The heterojunction transistor includes:
[0079] Substrate 10, on which a first dielectric layer 20 and a second dielectric layer 30 are sequentially formed;
[0080] The second trench 52 is located in the second dielectric layer 30 and the first dielectric layer 20. The second trench 52 is convex in shape, and the width of the second trench 52 in the first dielectric layer 20 is greater than the width of the second trench 52 in the second dielectric layer 30.
[0081] Collector material layer 60, wherein the collector material layer 60 fills the second trench 52;
[0082] A base material layer 70 covers the collector material layer 60 at the top of the second trench 52 and partially covers the second dielectric layer 30.
[0083] Preferred, Reference Figure 8 The heterojunction transistor further includes:
[0084] An emitter material layer 80 covers a first portion of the surface of the base material layer 70;
[0085] The outer base region 71 covers the second portion of the surface of the base material layer 70 on both sides of the emitter material layer 80;
[0086] Interlayer dielectric layer 90, which covers the outer base region 71, the emitter material layer 80, the exposed second dielectric layer 30, and the exposed substrate 10;
[0087] The system comprises a first conductive plug 91, a second conductive plug 92, and a third conductive plug 93. The first conductive plug 91 penetrates the interlayer dielectric layer 90 and contacts the emitter material layer 80. The second conductive plug 92 penetrates the interlayer dielectric layer 90 and contacts the outer base region 71. The third conductive plug 93 penetrates the interlayer dielectric layer 90, the second dielectric layer 30, and the first dielectric layer 20 and contacts the collector lead-out region 11.
[0088] In this application, a convex second trench is formed in the first dielectric layer and the second dielectric layer, and a collector material layer is filled in the second trench. A base material layer is formed on the collector material layer at the top of the second trench, thereby increasing the contact area between the collector material layer and the substrate to reduce the contact resistance. At the same time, the contact area between the collector material layer and the base material layer is reduced to reduce the collector junction capacitance, thereby jointly increasing the frequency of the heterojunction transistor. This enables the transistor to achieve low parasitic parameters and high power gain at high frequencies, meeting the needs of fields such as high-frequency communication, sensing, and computing.
[0089] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for fabricating a heterojunction transistor, characterized in that, include: A substrate is provided on which a first dielectric layer, a second dielectric layer and a hard mask layer are sequentially formed; The hard mask layer, the second dielectric layer, and the first dielectric layer are etched and stopped on the substrate surface to form a first trench; A wet etching process is used to continue to etch laterally the first dielectric layer of a first width and the second dielectric layer of a second width on the sidewall of the first trench to form a second trench, wherein the first width is greater than the second width. A current collector material layer is formed, and the current collector material layer fills the second trench; After removing the hard mask layer and the collector material layer that extend beyond the surface of the second dielectric layer, the second trench becomes convex in shape; and A base material layer is formed, which covers the current collector material layer at the top of the second trench and partially covers the second dielectric layer.
2. The method for fabricating a heterojunction transistor according to claim 1, characterized in that, The first dielectric layer is a TEOS layer.
3. The method for fabricating a heterojunction transistor according to claim 2, characterized in that, The first dielectric layer is formed using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).
4. The method for fabricating a heterojunction transistor according to claim 2, characterized in that, The second dielectric layer is a high-temperature oxide layer.
5. The method for fabricating a heterojunction transistor according to claim 4, characterized in that, The second dielectric layer is formed using a low-pressure chemical vapor deposition process or a thermal oxidation process.
6. The method for fabricating a heterojunction transistor according to claim 4, characterized in that, In the process of using a wet etching process to continue laterally etching the first dielectric layer of a first width and the second dielectric layer of a second width on the sidewall of the first trench to form the second trench, the wet etching reagent is diluted hydrofluoric acid.
7. The method for fabricating a heterojunction transistor according to claim 1, characterized in that, The current collector material layer is made of monocrystalline silicon or polycrystalline silicon.
8. The method for fabricating a heterojunction transistor according to claim 1, characterized in that, The base material layer is made of silicon germanide.
9. The method for fabricating a heterojunction transistor according to claim 1, characterized in that, After forming the base material layer, the method for fabricating the heterojunction transistor further includes: An emitter material layer is formed, the emitter material layer covering a first portion of the surface of the base material layer; An outer base region is formed, which covers a second portion of the surface of the base material layer on both sides of the emitter material layer; An interlayer dielectric layer is formed, which covers the outer base region, the emitter material layer, the exposed second dielectric layer, and the exposed substrate; Multiple conductive plugs are formed, each of which penetrates the interlayer dielectric layer and contacts the emitter material layer and the outer base region, respectively.
10. A heterojunction transistor, characterized in that, include: A substrate, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the substrate; The second trench is located in the second dielectric layer and the first dielectric layer, wherein the second trench is convex in shape, and the width of the second trench in the first dielectric layer is greater than the width of the second trench in the second dielectric layer. A current collector material layer, wherein the current collector material layer fills the second trench; A base material layer that covers the current collector material layer at the top of the second trench and partially covers the second dielectric layer.