4h-sic trench insulated gate bipolar transistors and methods of manufacturing the same

Abstract

The application provides a 4H-SiC trench type insulated gate bipolar transistor and a manufacturing method thereof. A first trench is formed in an N-type buffer layer, a P-type trench collector and an N-type trench collector are formed in the first trench, the P-type trench collector covers a surface of the first trench, the N-type trench collector is located in the P-type trench collector, a P-type collector is formed on a second surface of the N-type buffer layer, and a collector electrode covers the P-type collector, the P-type trench collector and the N-type trench collector. Contact between the collector electrode and the P-type trench collector is conducive to improving the on-current of the 4H-SiC trench type insulated gate bipolar transistor. The P-type trench collector and the N-type trench collector are formed in the first trench, so that an extraction channel of excess electrons is formed in the device in the off transient state, the recombination component of electrons and holes is reduced, the electric field on the reverse-biased PN junction can accelerate the extraction of electrons, and the off speed is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a 4H-SiC trench insulated gate bipolar transistor and its manufacturing method. Background Technology

[0002] An Insulated-Gate Bipolar Transistor (IGBT) is a device composed of an insulated-gate field-effect transistor (MOSFET) and a bipolar transistor. It combines the low drive power and high input impedance of a MOSFET with the low saturation voltage drop and high current density of a bipolar transistor. Its frequency characteristics fall between those of a MOSFET and a power transistor, allowing it to operate normally in the tens of kHz frequency range. It is the dominant device in high-power power electronic equipment and is widely used in frequency converters, lighting circuits, and switching power supplies. 4H-SiC, as a typical third-generation semiconductor material, possesses excellent material properties such as high saturated electron drift velocity, wide bandgap, strong Si-C bond energy, and high thermal conductivity. This allows the application of 4H-SiC-based IGBT devices to expand to higher frequencies, higher power, and more complex environments with radiation and temperature / humidity variations.

[0003] The existing 4H-SiC insulated gate bipolar transistor has a slow turn-off speed, which cannot fully utilize the material characteristics of wide bandgap semiconductors, and the turn-off loss increases sharply under high frequency operation. Summary of the Invention

[0004] The purpose of this invention is to provide a 4H-SiC trench insulated gate bipolar transistor and its manufacturing method, so as to solve the problem that the turn-off speed of the existing 4H-SiC insulated gate bipolar transistor is slow, resulting in a sharp increase in turn-off loss.

[0005] To address the aforementioned technical problems, this invention provides a 4H-SiC trench-type insulated-gate bipolar transistor, wherein the 4H-SiC trench-type insulated-gate bipolar transistor comprises:

[0006] An N-type buffer layer having opposing first and second surfaces, wherein a first trench is formed in the N-type buffer layer, the first trench extending from the second surface into the N-type buffer layer;

[0007] An N-type drift layer is located on the first surface of the N-type buffer layer, and a second trench is formed in the N-type drift layer;

[0008] The P-type shielding area is located in the N-type drift layer beneath the second trench;

[0009] The N-type drift layer located on the second trench side comprises an N-type carrier storage layer, a P-type body region, a P-type injection region, and an N-type injection region. The P-type body region is located on the N-type carrier storage layer, and the P-type injection region and the N-type injection region are juxtaposed and located on the P-type body region.

[0010] The gate structure located in the second trench;

[0011] Emitter electrodes located on the P-type injection region and the N-type injection region;

[0012] A P-type trench collector and an N-type trench collector are located in the first trench, wherein the P-type trench collector covers the surface of the first trench, and the N-type trench collector is located in the P-type trench collector;

[0013] The P-type collector located on the second surface of the N-type buffer layer; and,

[0014] Collector electrode covering the P-type collector, the P-type trench collector, and the N-type trench collector.

[0015] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the 4H-SiC trench insulated gate bipolar transistor further includes a collector dielectric layer, which is spaced between the N-type buffer layer and the collector electrode.

[0016] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the collector dielectric layer is located on the second surface of the N-type buffer layer and covers the sidewall of the P-type collector.

[0017] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the ratio of the width of the P-type collector to the width of the first trench is greater than 3:1.

[0018] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the ratio of the depth of the first trench to the thickness of the N-type buffer layer is between 1 / 5 and 4 / 5.

[0019] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the gate structure includes a gate dielectric layer and a gate electrode, the gate dielectric layer covers the surface of the second trench, the gate electrode is located in the gate dielectric layer, and the gate dielectric layer also covers the surface of the gate electrode.

[0020] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the gate dielectric layer further covers a portion of the surface of the N-type implantation region.

[0021] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the surface of the gate dielectric layer is flush with the surface of the emitter electrode.

[0022] Optionally, in the 4H-SiC trench insulated gate bipolar transistor, the surface of the gate electrode is flush with the surface of the N-type injection region.

[0023] The present invention also provides a method for manufacturing a 4H-SiC trench-type insulated-gate bipolar transistor, the method comprising:

[0024] A semiconductor substrate is provided, and an N-type buffer layer is formed in the semiconductor substrate, the N-type buffer layer having opposing first and second surfaces;

[0025] An N-type drift layer is formed on the first surface of the N-type buffer layer, and a second trench is formed in the N-type drift layer. A P-type shielding region is formed in the N-type drift layer below the second trench. An N-type carrier storage layer, a P-type body region, a P-type injection region, and an N-type injection region are formed in the N-type drift layer on the side of the second trench. The P-type body region is located on the N-type carrier storage layer. The P-type injection region and the N-type injection region are juxtaposed and located on the P-type body region. A gate structure is formed in the second trench. Emitter electrodes are formed on the P-type injection region and the N-type injection region.

[0026] A first trench is formed in the N-type buffer layer, extending from the second surface into the N-type buffer layer. A P-type trench collector and an N-type trench collector are formed in the first trench. The P-type trench collector covers the surface of the first trench, and the N-type trench collector is located in the P-type trench collector. A P-type collector is formed on the second surface of the N-type buffer layer. Collector electrodes are formed on the P-type collector, the P-type trench collector, and the N-type trench collector.

[0027] In the 4H-SiC trench-type insulated-gate bipolar transistor and its manufacturing method provided by the present invention, a first trench is formed in an N-type buffer layer, and a P-type trench collector and an N-type trench collector are formed in the first trench. The P-type trench collector covers the surface of the first trench, and the N-type trench collector is located in the P-type trench collector. A P-type collector is formed on the second surface of the N-type buffer layer, and collector electrodes are covered on the P-type collector, the P-type trench collector, and the N-type trench collector. The contact between the collector electrode and the P-type trench collector helps to suppress the problem of reduced hole injection efficiency caused by the reduction of the planar P-type collector area, and improves the conduction current of the 4H-SiC trench-type insulated-gate bipolar transistor. The first trench has a P-type trench collector and an N-type trench collector, which enables the 4H-SiC trench insulated gate bipolar transistor to form an excess electron extraction channel during the turn-off transient, reducing the recombination component of electrons and holes. At the same time, the electric field on the reverse-biased PN junction accelerates the extraction of electrons, greatly improving the turn-off speed of the 4H-SiC trench insulated gate bipolar transistor. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a 4H-SiC trench insulated gate bipolar transistor according to an embodiment of the present invention.

[0029] The reference numerals in the attached figures are explained as follows:

[0030] 1-4H-SiC trench insulated gate bipolar transistor; 100-N-type buffer layer; 101-first surface; 102-second surface; 110-first trench; 120-N-type drift layer; 130-second trench; 140-P-type shielding region; 150-N-type carrier storage layer; 160-P-type body region; 170-P-type injection region; 180-N-type injection region; 190-gate structure; 191-gate dielectric layer; 192-gate electrode; 200-emitter electrode; 210-P-type trench collector; 220-N-type trench collector; 230-P-type collector; 240-collector electrode; 250-collector dielectric layer. Detailed Implementation

[0031] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the 4H-SiC trench-type insulated-gate bipolar transistor and its manufacturing method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0032] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "upper / upper layer," "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including" and its equivalents, and does not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0033] Please refer to Figure 1 This is a schematic diagram of the structure of a 4H-SiC trench-type insulated-gate bipolar transistor according to an embodiment of the present invention. Figure 1As shown in this embodiment, the 4H-SiC trench-type insulated gate bipolar transistor 1 includes: an N-type buffer layer 100, the N-type buffer layer 100 having opposing first surfaces 101 and second surfaces 102, a first trench 110 formed in the N-type buffer layer 100, the first trench 110 extending from the second surface 102 into the N-type buffer layer 100; an N-type drift layer 120 located on the first surface 101 of the N-type buffer layer 100, the N-type drift layer 120 having a second trench 130 formed therein; a P-type shielding region 140 located in the N-type drift layer 120 below the second trench 130; an N-type carrier storage layer 150, a P-type body region 160, a P-type injection region 170, and an N-type injection region 180 located in the N-type drift layer 120 on the side of the second trench 130, the P-type body region 160, the P-type body region 170, and the P-type body region 180 being the N-type carrier storage layer 150, the P-type body region 160, the P-type body region 170, and the P-type body region 180 being the N-type body region 180. The P-type body region 160 is located on the N-type carrier storage layer 150, and the P-type injection region 170 and the N-type injection region 180 are juxtaposed and located on the P-type body region 160; a gate structure 190 is located in the second trench 130; an emitter electrode 200 is located on the P-type injection region 170 and the N-type injection region 180; a P-type trench collector 210 and an N-type trench collector 220 are located in the first trench 110, the P-type trench collector 210 covers the surface of the first trench 110, and the N-type trench collector 220 is located in the P-type trench collector 210; a P-type collector 230 is located on the second surface 102 of the N-type buffer layer 180; and a collector electrode 240 covering the P-type collector 230, the P-type trench collector 210, and the N-type trench collector 220.

[0034] The 4H-SiC trench insulated gate bipolar transistor 1 is preferably formed using an inverted-growth process. Specifically, the N-type buffer layer 100, the N-type drift layer 120, and the P-type collector 230 can be formed by epitaxial growth on a 4H-SiC substrate, followed by wafer inversion and removal of the substrate portion through chemical mechanical polishing, thinning, and other processes. The N-type trench collector 220 can be formed using an N-type doping (N) process; the N-type carrier storage layer 150 can be formed using an N-type doping (N) process or an epitaxial growth process; the N-type implantation region 180 can be formed using an N-type heavy doping (N+) process; the P-type shielding region 140 can be formed using a P-type doping (P) process; the P-type body region 160 can be formed using a P-type doping (P) process or an epitaxial growth process; and the P-type implantation region 170 and the P-type trench collector 210 can be formed using a P-type heavy doping (P+) process.

[0035] like Figure 1As shown, the gate structure 190 includes a gate dielectric layer 191 and a gate electrode 192. The gate dielectric layer 191 covers the surface of the second trench 130, and the gate electrode 192 is located in the gate dielectric layer 191. The gate dielectric layer 191 also covers the surface of the gate electrode 192. In this embodiment, the gate electrode 192 may be made of polysilicon, and the gate dielectric layer 191 may be made of oxide.

[0036] In this embodiment, a P-type shielding region 140 is formed in the N-type drift layer 120 under the second trench 130, and a gate structure 190 is formed in the second trench 130. The gate structure 190 can be protected by the P-type shielding region 140. According to Gauss's law, the electric field strength in the gate oxide layer of a SiC device is about three times that of the bulk SiC electric field strength. Long-term operation in a high-field environment will cause device performance degradation and even burn-out of the gate oxide layer. In this embodiment, the P-type shielding region 140 formed below the trench gate structure 190 can effectively terminate the high-voltage electric field lines and shield the high electric field of the gate dielectric layer 191. Therefore, the maximum electric field in the gate dielectric layer 191 of the 4H-SiC trench insulated gate bipolar transistor 1 is maintained below the safe threshold of 4MV / cm under ultra-high voltage blocking.

[0037] Furthermore, with the increase in power density, large JFET (Junction Field-Effect Transistor) region resistances will form between the P-type shielding regions and between the P-type shielding region and the P-type body region in small-sized devices, affecting the conduction characteristics of the devices. In this embodiment, the introduction of a highly doped N-type carrier storage layer (NCSL) 150 helps to avoid this JFET effect. At the same time, the N-type carrier storage layer 150 is equivalent to a high-resistance layer for holes, which can accumulate holes and induce more electrons to be injected into the N-type injection region 180, thus exhibiting a carrier injection enhancement effect.

[0038] In the traditional IGBT turn-off transient, holes stored in the on-state are mainly extracted by the emitter through the P-type body region and P-type injection region, while electrons undergo a long recombination elimination process, resulting in a large tail current and severely slowing down the device's turn-off speed. In this embodiment, structural optimization changes the turn-off mechanism. Under the influence of the electric field, a significant voltage drop exists at the junction of the reverse-biased P-type trench collector 210 and the N-type trench collector 220, reducing the recombination component of excess electrons and creating an accelerated electron extraction channel within the device. Simultaneously, the trench collector extending into the N-type buffer layer 100 also shortens the electron elimination path. The contact between the collector electrode 240 and the P-type trench collector 210 helps to increase the on-current of the 4H-SiC trench insulated gate bipolar transistor 1.

[0039] Please continue to refer to this. Figure 1In this embodiment, the 4H-SiC trench insulated gate bipolar transistor 1 further includes a collector dielectric layer 250, which is spaced between the N-type buffer layer 100 and the collector electrode 240. This provides better electrical isolation between the N-type buffer layer 100 and the collector electrode 240. The collector dielectric layer 250 is located on the second surface 102 of the N-type buffer layer 100 and covers the sidewall of the P-type collector electrode 230. Furthermore, the collector dielectric layer 250 may extend to cover a portion of the surface of the P-type trench collector electrode 210. The surface of the collector dielectric layer 250 is flush with the surface of the P-type collector electrode 230.

[0040] In this embodiment, the ratio of the width of the P-type collector 230 to the width of the first trench 110 is greater than 3:1. For example, the ratio of the width of the P-type collector 230 to the width of the first trench 110 can be 4:1, 5:1, 8:1, etc. This allows for better control of the electrical performance of the 4H-SiC trench-type insulated-gate bipolar transistor 1.

[0041] The ratio of the depth of the first trench 110 to the thickness of the N-type buffer layer 100 is between 1 / 5 and 4 / 5. That is, the depth of the first trench 110 is less than the thickness of the N-type buffer layer 100, and is between 1 / 5 and 4 / 5 of the thickness of the N-type buffer layer 100. This allows for better control of the depth of the first trench 110, facilitating its formation.

[0042] like Figure 1 As shown in this embodiment, the gate dielectric layer 191 further covers a portion of the surface of the N-type implantation region 180. Furthermore, the surface of the gate dielectric layer 191 is flush with the surface of the emitter electrode 200. The surface of the gate electrode 192 is flush with the surface of the N-type implantation region 180.

[0043] Furthermore, this application embodiment also provides a method for manufacturing the above-mentioned 4H-SiC trench insulated gate bipolar transistor. In this application embodiment, the 4H-SiC trench insulated gate bipolar transistor 1 is mainly formed by existing semiconductor processes such as ion implantation, etching, and epitaxial growth. This application embodiment does not limit the order or process of forming the various structures in the 4H-SiC trench insulated gate bipolar transistor 1, as long as the 4H-SiC trench insulated gate bipolar transistor 1 can be formed. During the turn-off transient, the formed 4H-SiC trench insulated gate bipolar transistor 1 forms an excess electron extraction channel through the P-type trench collector 210 and the N-type trench collector 220, reducing the recombination component of electrons and holes. Simultaneously, the electric field on the reverse-biased PN junction accelerates electron extraction, greatly improving the turn-off speed of the 4H-SiC trench insulated gate bipolar transistor 1.

[0044] Please continue to refer to this. Figure 1 Specifically, the manufacturing method of the 4H-SiC trench insulated gate bipolar transistor includes:

[0045] A semiconductor substrate (not shown) is provided, in which an N-type buffer layer 100 is formed, the N-type buffer layer 100 having opposing first surfaces 101 and second surfaces 102;

[0046] An N-type drift layer 120 is formed on the first surface 101 of the N-type buffer layer 100, and a second trench 130 is formed in the N-type drift layer 120. A P-type shielding region 140 is formed in the N-type drift layer 120 below the second trench 130. An N-type carrier storage layer 150, a P-type body region 160, a P-type injection region 170, and an N-type injection region 180 are formed in the N-type drift layer 120 on the side of the second trench 130. The P-type body region 160 is located on the N-type carrier storage layer 150. The P-type injection region 170 and the N-type injection region 180 are juxtaposed and located on the P-type body region 160. A gate structure 190 is formed in the second trench 130. Emitter electrodes 200 are formed on the P-type injection region 170 and the N-type injection region 180.

[0047] A first trench 110 is formed in the N-type buffer layer 100, extending from the second surface 102 into the N-type buffer layer 100. A P-type trench collector 210 and an N-type trench collector 220 are formed in the first trench 110. The P-type trench collector 210 covers the surface of the first trench 110, and the N-type trench collector 220 is located in the P-type trench collector 210. A P-type collector 230 is formed on the second surface 102 of the N-type buffer layer 100. A collector electrode 240 is formed on the P-type collector 230, the P-type trench collector 210, and the N-type trench collector 220.

[0048] In this application, the structure on the first surface 101 of the N-type buffer layer 100 can be formed first, followed by the structure on the second surface 102 of the N-type buffer layer 100; alternatively, the structure on the second surface 102 of the N-type buffer layer 100 can be formed first, followed by the structure on the first surface 101 of the N-type buffer layer 100. Furthermore, a portion of the structure on the first surface 101 of the N-type buffer layer 100 can be formed first, followed by a portion of the structure on the second surface 102 of the N-type buffer layer 100, and so on. This application does not limit the specific method used.

[0049] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0050] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A 4H-SiC trench-type insulated-gate bipolar transistor, characterized in that, The 4H-SiC trench insulated gate bipolar transistor includes: An N-type buffer layer having opposing first and second surfaces, wherein a first trench is formed in the N-type buffer layer, the first trench extending from the second surface into the N-type buffer layer; An N-type drift layer is located on the first surface of the N-type buffer layer, and a second trench is formed in the N-type drift layer; The P-type shielding area is located in the N-type drift layer beneath the second trench; The N-type drift layer located on the second trench side comprises an N-type carrier storage layer, a P-type body region, a P-type injection region, and an N-type injection region. The P-type body region is located on the N-type carrier storage layer, and the P-type injection region and the N-type injection region are juxtaposed and located on the P-type body region. The gate structure located in the second trench; Emitter electrodes located on the P-type injection region and the N-type injection region; A P-type trench collector and an N-type trench collector are located in the first trench, wherein the P-type trench collector covers the surface of the first trench, and the N-type trench collector is located in the P-type trench collector; The P-type collector located on the second surface of the N-type buffer layer; and, Collector electrode covering the P-type collector, the P-type trench collector, and the N-type trench collector.

2. The 4H-SiC trench insulated gate bipolar transistor as described in claim 1, characterized in that, The 4H-SiC trench insulated gate bipolar transistor further includes a collector dielectric layer, which is spaced between the N-type buffer layer and the collector electrode.

3. The 4H-SiC trench insulated gate bipolar transistor as described in claim 2, characterized in that, The collector dielectric layer is located on the second surface of the N-type buffer layer and covers the sidewall of the P-type collector.

4. The 4H-SiC trench insulated gate bipolar transistor as described in claim 1, characterized in that, The ratio of the width of the P-type collector to the width of the first trench is greater than 3:

1.

5. The 4H-SiC trench insulated gate bipolar transistor as described in claim 1, characterized in that, The ratio of the depth of the first trench to the thickness of the N-type buffer layer is between 1 / 5 and 4 / 5.

6. The 4H-SiC trench insulated gate bipolar transistor as described in any one of claims 1 to 5, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer covers the surface of the second trench, and the gate electrode is located in the gate dielectric layer. The gate dielectric layer also covers the surface of the gate electrode.

7. The 4H-SiC trench insulated gate bipolar transistor as described in claim 6, characterized in that, The gate dielectric layer also covers a portion of the surface of the N-type implantation region.

8. The 4H-SiC trench insulated gate bipolar transistor as described in claim 7, characterized in that, The surface of the gate dielectric layer is flush with the surface of the emitter electrode.

9. The 4H-SiC trench insulated gate bipolar transistor as described in claim 6, characterized in that, The surface of the gate electrode is flush with the surface of the N-type injection region.

10. A method for manufacturing a 4H-SiC trench-type insulated-gate bipolar transistor, characterized in that, The manufacturing method of the 4H-SiC trench insulated gate bipolar transistor includes: A semiconductor substrate is provided, and an N-type buffer layer is formed in the semiconductor substrate, the N-type buffer layer having opposing first and second surfaces; An N-type drift layer is formed on the first surface of the N-type buffer layer, and a second trench is formed in the N-type drift layer. A P-type shielding region is formed in the N-type drift layer below the second trench. An N-type carrier storage layer, a P-type body region, a P-type injection region, and an N-type injection region are formed in the N-type drift layer on the side of the second trench. The P-type body region is located on the N-type carrier storage layer. The P-type injection region and the N-type injection region are juxtaposed and located on the P-type body region. A gate structure is formed in the second trench. Emitter electrodes are formed on the P-type injection region and the N-type injection region. A first trench is formed in the N-type buffer layer, extending from the second surface into the N-type buffer layer. A P-type trench collector and an N-type trench collector are formed in the first trench. The P-type trench collector covers the surface of the first trench, and the N-type trench collector is located in the P-type trench collector. A P-type collector is formed on the second surface of the N-type buffer layer. Collector electrodes are formed on the P-type collector, the P-type trench collector, and the N-type trench collector.

Images