High speed switching shield gate trench power semiconductor device
By introducing multiple pickup trenches into shielded gate trench power semiconductor devices, the problems of reduced gate and drain capacitance and increased costs caused by different component layouts are solved, achieving efficient manufacturing and design flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPWELL TECH CORP
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-23
AI Technical Summary
Existing trench-type high-power semiconductor devices have technical limitations in reducing gate and drain capacitance, and the different device structure layouts for different needs lead to increased costs and design and manufacturing inconveniences.
A shielded gate trench structure is adopted, and multiple pickup trenches are introduced in the gate trench to realize the shared process of semiconductor devices of different specifications. The wiring design of the pickup trench increases the wiring flexibility and reduces the process complexity and cost.
This enables shielded gate trench power semiconductor devices of various specifications to be manufactured without increasing process complexity and cost, thereby improving production efficiency and design flexibility.
Smart Images
Figure CN122269727A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor element, and more particularly to a high-speed switching shielded gate trench power semiconductor device. Background Technology
[0002] In high-speed applications of semiconductor devices, higher figures of merit (FoM) are required. Traditional trench high-power semiconductors, such as MOSFET devices, require improvements to wafer fabrication processes and device layout to achieve a higher FoM. However, reducing the gate-drain capacitance (C) in trench DMOS devices... gd In terms of gate and drain capacitance (C), technical limitations and difficulties still exist. gd A shielded-gate trench (SGT) structure is introduced at the bottom of the trench gate to shield the influence between the trench gate and the drain.
[0003] Insulated-gate bipolar transistor (IGBT) technology is also crucial in high-power applications. In existing technologies, when the blocking voltage exceeds 600 V, high-speed switching can reduce the power loss of IGBT modules during turn-on switching. However, this also generates high reverse recovery dv / dt, leading to electromagnetic interference (EMI) and increasing the stress on motor insulation. To address this issue, the SGT structure has been introduced into IGBTs.
[0004] As shown above, the SGT structure can effectively improve and enhance performance in trench power semiconductor devices. However, with the increasingly widespread application of power semiconductor devices, devices with the same architecture have different structural layouts to meet different needs. For example, common power semiconductor devices have standard (STD) and high-frequency (HF) versions, and these two versions require different masks due to differences in layout. This leads to increased costs and inconveniences in design and manufacturing. Summary of the Invention
[0005] In view of this, the object of the present invention is to improve existing power semiconductor devices.
[0006] According to one aspect of the present invention, a high-speed switching shielded gate trench power semiconductor device includes a semiconductor substrate, a drift layer, a first doped region, a second doped region, a plurality of gate trenches, a plurality of gates, a plurality of shielding regions, an intermediate layer, a first pickup trench, a second pickup trench, and a third pickup trench. The drift layer has a first conductivity type, is disposed on the semiconductor substrate, and has a main surface. A first doped region has a second conductivity type opposite to the first conductivity type and is disposed on the drift layer. The first doped region extends laterally and is adjacent to the main surface. A second doped region has the first conductivity type and is disposed within the first doped region. The second doped region extends laterally and is adjacent to the main surface. A gate trench passes through the first and second doped regions along a depth direction substantially perpendicular to the main surface. The gate trenches extend laterally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each gate trench includes a first segment and a second segment in the first direction. A gate is disposed in the first segment of the gate trench, and the gate includes a portion located within the gate trench. The device comprises a gate portion, a first shielding portion located in and below the gate portion, and a first insulating portion located in the gate trench and electrically isolating the gate portion from the first shielding portion. A shielding region is disposed in a second segment of the gate trench, including a second shielding portion located in the gate trench and a second insulating portion located in the gate trench and electrically isolating the second shielding portion. An intermediate layer is disposed on the main surface. A first pickup trench extends through the intermediate layer to the first segment of the gate trench and is provided with a first conductive material connected to the gate portion. A second pickup trench extends through the intermediate layer to the second segment of the gate trench and is provided with a second conductive material connected to the second shielding portion. A third pickup trench extends through the intermediate layer to the gate trench and is provided with a third conductive material. The third pickup trench is selectively disposed above either the first or second segment of the gate trench according to the blocking voltage required by the power semiconductor device.
[0007] In one embodiment, a gate metal layer and a source metal layer are further included. The gate metal layer is disposed on a gate region of the intermediate layer and is connected to the first conductive material in the first pickup trench. The source metal layer is disposed on a source region of the intermediate layer and is connected to the second conductive material in the second pickup trench and the third conductive material in the third pickup trench.
[0008] In one embodiment, the system further includes a gate metal layer and a source metal layer. The gate metal layer is disposed on a gate region of the intermediate layer and connects the first conductive material in the first pickup trench and the third conductive material in the third pickup trench. The source metal layer is disposed on a source region of the intermediate layer and connects the second conductive material in the second pickup trench.
[0009] In one embodiment, a drain metal layer is further included, disposed on a bottom surface of the semiconductor substrate.
[0010] In one embodiment, a fourth pickup trench is further included, extending through the intermediate layer into the first doped region, the fourth pickup trench being provided with a fourth conductive material connected to the first doped region.
[0011] In one embodiment, a gate metal layer and an emitter metal layer are further included. The gate metal layer is disposed on a gate region of the intermediate layer and is connected to the first conductive material in the first pickup trench. The emitter metal layer is disposed on an emitter region of the intermediate layer and is connected to the second conductive material in the second pickup trench and the third conductive material in the third pickup trench.
[0012] In one embodiment, the system further includes a gate metal layer and an emitter metal layer. The gate metal layer is disposed on a gate region of the intermediate layer and connects the first conductive material in the first pickup trench and the third conductive material in the third pickup trench. The emitter metal layer is disposed on an emitter region of the intermediate layer and connects the second conductive material in the second pickup trench.
[0013] In one embodiment, the power semiconductor device is a transistor, which is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).
[0014] According to another aspect of the present invention, a high-speed switching shielded gate trench power semiconductor device includes: a semiconductor substrate, a drift layer, a first doped region, a second doped region, a plurality of gate trenches, a plurality of gates, a plurality of shielding regions, an intermediate layer, a first contact, and a second contact. The drift layer has a first conductivity type and is disposed on the semiconductor substrate and has a main surface. The first doped region has a second conductivity type opposite to the first conductivity type and is disposed in the drift layer. The first doped region extends laterally and is adjacent to the main surface. The second doped region has the first conductivity type and is disposed in the first doped region. The second doped region extends laterally and is adjacent to the main surface. The gate trenches pass through the first doped region and the second doped region along a depth direction substantially perpendicular to the main surface. The gate trenches extend laterally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each gate trench includes a first segment and a second segment in the first direction. Viewed from a planar perspective of the main surface, the gate trench includes a first group and a second group, with each first group located between adjacent second groups. The gate is disposed in the first segment of the gate trench. The gate includes a gate portion located in the gate trench, a first shielding portion located in the gate trench and below the gate portion, and a first insulating portion located in the gate trench and electrically isolating the gate portion from the first shielding portion. The shielding region is disposed in the second segment of the gate trench, and the shielding region includes a portion located on the gate... The gate trench includes a second shielding portion and a second insulating portion electrically isolating the second shielding portion. An intermediate layer is disposed on the main surface. A first contact is disposed on the gate trench in the first group, extending through the intermediate layer to the first segment of the gate trench and electrically connected to the gate portion. A second contact is disposed on the gate trench in the second group, extending through the intermediate layer to the second segment of the gate trench and electrically connected to the second shielding portion. Viewed from a plan view of the main surface, the first and second contacts are arranged side-by-side with respect to the gate trench configuration. The first and second contacts are respectively disposed along a first horizontal imaginary line and a second horizontal imaginary line in a second direction, separated by a distance.
[0015] In one embodiment, the power semiconductor device is a transistor, which is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). Attached Figure Description
[0016] Figure 1 This is a plan view of a semiconductor device according to some aspects of the present disclosure.
[0017] Figure 2 for Figure 1 A partially enlarged planar schematic diagram.
[0018] Figure 3A For along Figure 2 A schematic diagram of the cross section AA.
[0019] Figure 3B For along Figure 2 A cross-sectional diagram of the section line BB.
[0020] Figure 3C For along Figure 2 A cross-sectional diagram of the secant line CC.
[0021] Figure 3D For along Figure 2 A cross-sectional diagram of the secant line DD.
[0022] Figure 4 This is a partially enlarged planar schematic diagram of another semiconductor device according to some aspects of this disclosure.
[0023] Figure 5 This is a partially enlarged planar schematic diagram of another semiconductor device according to some aspects of this disclosure.
[0024] Figure 6 This is a partially enlarged planar schematic diagram of another semiconductor device according to some aspects of this disclosure.
[0025] Figure 7 This is a partially enlarged planar schematic diagram of another semiconductor device according to some aspects of this disclosure. Detailed Implementation
[0026] The semiconductor device of this disclosure is described below with reference to the accompanying drawings. It should be understood that other examples may also be used without departing from this disclosure, and structural or logical modifications may be made. For example, features in the drawings or description of one example may be combined with other examples to form another example, and this disclosure is intended to include such modifications and variations. On the other hand, specific terminology is used in the illustrative descriptions, but this should not be construed as limiting the scope of the claims.
[0027] In this disclosure, when an element such as a layer, portion, region, or substrate is referred to as "on top of," "over," or "above" another element, it may be directly on top of, directly covering, or directly above the element; or there may be other elements in between. Conversely, when an element is referred to as "directly on top of," "directly covering," or "directly above" another element, there are no intermediate elements.
[0028] This disclosure uses spatially relative terms to describe the relationship between one element, layer, portion, or region in the figures and another element, layer, portion, or region, such as "above," "on top," "above," "below," "below," "under," and other similar terms, but only for convenience in describing the relationship between one element or feature and another element or feature in the figures. The spatially relative terms cover not only the orientation depicted in the figures but also other orientations of the device during use or operation. The device may be oriented in other orientations, and the spatially relative descriptions used in this disclosure can be interpreted accordingly. Furthermore, the term "lateral" or "lateral direction" as used in this disclosure should be understood to mean a direction or extent substantially (generally) parallel to the lateral extent of the semiconductor device, which is therefore substantially parallel to its surface or extends from its side. Conversely, the terms "depth direction" or "thickness direction" are understood to mean a direction substantially perpendicular to its surface and therefore perpendicular to the lateral direction.
[0029] In this disclosure, the terminology used in the description of various examples is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context specifically indicates or intentionally limits the number of elements, the singular forms “a” and “the” used in this disclosure also include the plural forms. On the other hand, the terms “comprising,” “including,” and “containing” used in this disclosure indicate the presence of the stated feature, element, and / or component, without excluding the addition or presence of one or more other features, elements, components, and / or groups thereof. Unless the contrary is clearly apparent from the context or specifically indicated or intentionally limited, indefinite and definite articles shall include both plural and singular forms.
[0030] In this disclosure, n-type doping is referred to as the first conductivity type, and p-type doping is referred to as the second conductivity type; or, the opposite doping relationship can be used to form a semiconductor device, that is, the first conductivity type can be p-type doping, and the second conductivity type can be n-type doping.
[0031] In the diagram, the thickness of each layer, part, and area has been enlarged for clarity. Figure 1 The diagram shows a top view of an example of a high-speed switching shielded gate trench power semiconductor device 1, using a MOSFET as an example. The semiconductor device 1 includes a gate pad region 1a, a gate runner region 1b, an active region 1c, and a termination region 1d. The gate runner region 1b is disposed around the active region 1c and is used to connect the gate pad region 1a to the gate in the trench of the active region 1c.
[0032] Figure 2 Showing Figure 1A partially enlarged planar schematic diagram. Figure 2 For the standard version (STD) MOSFET, the enlarged planar schematic diagram here, for illustrative purposes, shows the arrangement of the terminal region 1d, the gate channel region 1b, and the active region 1c of the power semiconductor device 1 with the trench and electrode pickup structure, and their cooperation... Figures 3A to 3D , respectively along Figure 2 The diagram shows cross-sectional views of the MOSFET element along the cut lines AA, BB, CC, and DD. It should be understood that, for simplicity, only a portion of the MOSFET element is shown here, and those skilled in the art will understand that other areas will also be included.
[0033] Viewed from the side, the semiconductor device 1 includes a semiconductor substrate 10, a drift layer 11, a first doped region 12, a second doped region 13, a plurality of gate trenches 14, an intermediate layer 15, a gate, a gate metal 17a, a source metal 17b, and a drain metal 18.
[0034] In this document, for convenience, the direction perpendicular to a main surface 11a of the drift layer 11, i.e., the direction parallel to the normal of the main surface 11a, is referred to as a normal direction Z of the semiconductor substrate 10, and the view from this normal direction Z is called a planar view. The semiconductor substrate 10 has a first conductivity type (e.g., N-type) and in one example may be a silicon carbide (SiC) substrate. The semiconductor substrate 10 may also contain other semiconductors such as silicon, germanium, silicon-germanium, or diamond. The semiconductor substrate 10 may also be modified to contain semiconductor compounds and / or semiconductor alloys, depending on the final application.
[0035] The drift layer 11 is disposed on the semiconductor substrate 10 and has the first conductivity type. The drift layer 11 can be disposed in or on the semiconductor substrate 10, depending on the manufacturing process. The drift layer 11 can be formed by epitaxial growth on the semiconductor substrate 10 or by implantation on the semiconductor substrate 10. The first doped region 12 can be disposed in the drift layer 11 and adjacent to a main surface 11a of the drift layer 11. The first doped region 12 has a second conductivity type (e.g., P-type) opposite to the first conductivity type. The first doped region 12 can be formed by implanting a P-type dopant (e.g., boron ions or aluminum ions) into the N-type drift layer 11 to form an anti-doped P-type region near the main surface 11a; and the second doped region 13 can be formed by implanting an N-type dopant (e.g., nitrogen ions, phosphorus ions or arsenic ions) into the P-type first doped region 12 to form a heavily doped N-type region.
[0036] from Figures 3A to 3DThe gate trench 14 extends from the main surface 11a along a depth direction, passing through the first doped region 12 and the second doped region 13, and extends to the drift layer 11. A gate oxide 141, such as an insulating layer, is formed on an inner wall of the gate trench 14. The gate oxide 141 is filled with a gate portion 142 and a shielding portion 143. The gate portion 142 can be conductive doped polysilicon, and the shielding portion 143 is a field electrode material, which in one example can also be conductive doped polysilicon. Figure 2 The gate trench 14 extends along a first transverse direction Y and spans the terminal region 1d, the gate channel region 1b, and the active region 1c, with each gate trench 14 arranged side by side. Depending on the location of the gate trench 14 in different regions, each gate trench 14 may include a first segment and a second segment. The first segment serves as the gate region and therefore has the gate portion 142 and the shielding portion 143. The second segment serves as the shielding region and therefore has the shielding portion 143, but no gate portion 142. It is understood that the shielding portion 143 located in the first segment can be considered a first shielding portion, and the shielding portion 143 located in the second segment can be considered a second shielding portion.
[0037] In other words, the shielding portion 143 is located below the gate portion 142 and extends continuously along the first transverse direction Y with the gate trench 14, while the gate portion 142 extends discontinuously along the first transverse direction Y with the gate trench 14. The intermediate layer 15 is disposed on the main surface 11a and the gate trench 14. The intermediate layer 15 can be a dielectric metal insulating layer, such as borosilicate glass (BPSG). A metal layer is disposed on the intermediate layer 15. In the active region 1c and the terminal region 1d, the metal layer is the source metal 17b. In the gate channel region 1b and the gate pad region 1a, the metal layer is the gate metal 17a. The drain metal 18 is disposed on a bottom surface of the semiconductor substrate 10.
[0038] The semiconductor device 1 further includes a plurality of first pickup trenches 18a, a plurality of second pickup trenches 18b, a plurality of third pickup trenches 18c, and a plurality of fourth pickup trenches 18d, which are respectively used to fill conductive materials, such as metal or polysilicon. The first pickup trenches 18a are used to connect the gate portion 142, the second pickup trenches 18b are used to connect the shield portion 143, the third pickup trenches 18c can be used to connect the gate portion 142 or the shield portion 143, depending on whether the third pickup trenches 18c are used to be disposed in the gate channel region 1b or the active region 1c, and the fourth pickup trenches 18d are used to connect the first doped region 12 and the second doped region 13. Figure 3A This shows the configuration of the first pickup groove 18a. Figure 3B This shows the configuration of the second pickup groove 18b. Figure 3C This displays the configuration of the fourth pickup groove 18d. Understandably, Figure 2 The configuration of the third pickup groove 18c in the example can be referred to. Figure 3A The configuration of the first pickup groove 18a.
[0039] The first pickup trench 18a, the second pickup trench 18b, and the third pickup trench 18c are all disposed above the gate trench 14 and penetrate the intermediate layer 15; the fourth pickup trench 18d is disposed above the first doped region 12. From the perspective of the wiring structure, the first pickup trench 18a is located in the gate channel region 1b, the second pickup trench 18b and the fourth pickup trench 18d are located in the termination region 1d, and the third pickup trench 18c may be located in the gate channel region 1b or the termination region 1d.
[0040] The present invention utilizes the design of the first pickup trench 18a and the third pickup trench 18c to increase the flexibility of wiring. The first pickup trench 18a and the third pickup trench 18c are located above the gate trench 14, but can be located below the gate metal 17a or the source metal 17b relative to the metal layer. See also... Figure 2 The first pickup trench 18a is disposed above a portion of the gate trench 14a, while the third pickup trench 18c is disposed above another portion of the gate trench 14b. That is, viewed from a second lateral direction X, the first pickup trench 18a and the third pickup trench 18c are disposed on adjacent gate trenches 14. Furthermore, the first pickup trench 18a above the gate trench 14a is aligned with a first horizontal imaginary line 20a, while the third pickup trench 18c above the gate trench 14b is aligned with a second horizontal imaginary line 20b. The first horizontal imaginary line 20a and the second horizontal imaginary line 20b are separated by a distance D, which is defined as the furthest distance between the first pickup trench 18a and the third pickup trench 18c in the first lateral direction Y. In one example, this distance D is greater than 0 and may be greater than a minimum threshold. The distance D is within a range whose upper and lower limits are designed based on a width W of the gate channel region 1b.
[0041] In terms of the electrical connection path, the first pickup trench 18a is used to connect to (or pick up) a top electrode of the gate trench 14 (such as the gate metal 17a), the second pickup trench 18b is used to connect to (or pick up) a dummy shield electrode of the gate trench 14 (such as the shield 143), and the third pickup trench 18c is used to connect to (or pick up) a dummy top electrode of the gate trench 14. Figure 2 and Figure 4(All examples are), the fourth pickup trench 18d is used to connect (or pick up) a source region (the source metal 17b).
[0042] Figure 2 For a standard version (STD) MOSFET, the width W is greater than the distance D; while Figure 4 For a high-frequency (HF) MOSFET, the width W is smaller than the distance D, but larger than the length of the first pickup trench 18a in the first lateral direction Y. Figure 2 and Figure 4 In this configuration, the wiring arrangement formed by the gate trench 14, the first pickup trench 18a, the second pickup trench 18b, the third pickup trench 18c, and the fourth pickup trench 18d is identical, differing only in the width W of the gate channel region 1b. Therefore, for the production of semiconductor devices using multi-stage lithography processes, only a single mask needs to be changed, allowing two or more different specifications of semiconductor devices to share other masks and processes. Furthermore, the changed mask differs only in geometric dimensions. In other words, this significantly reduces process complexity and cost, and improves production efficiency. Figure 4 The configuration of the third pickup groove 18c in the example can be referred to. Figure 3B The configuration of the second pickup groove 18b.
[0043] Figure 5 This shows the wiring of another possible high-frequency (HF) MOSFET, and it can be seen that the wiring configuration is also the same as... Figure 2 and Figure 4 The difference lies in the example. Figure 5 The first pickup groove 18a is placed in the active area 1c.
[0044] The wiring configuration disclosed herein is not limited to application to MOSFETs. Figure 6 and Figure 7 This wiring configuration is shown for an insulated gate bipolar transistor (IGBT), including an emitter region 3a and a gate region 3b, the gate region 3b being disposed around the emitter region 3a. It should be understood that, for simplicity, only the emitter and gate regions of the IGBT element are shown here; those skilled in the art will understand that other regions, such as the collector, may also be included.
[0045] The insulated gate bipolar transistor includes a plurality of gate trenches 44, a plurality of first pickup trenches 48a, a plurality of second pickup trenches 48b, a plurality of third pickup trenches 48c and a plurality of fourth pickup trenches 48d, which are respectively used to fill conductive materials, such as metal or polysilicon.
[0046] From the perspective of wiring structure, the first pickup trench 48a is disposed in the gate region 3b and penetrates the intermediate layer; the second pickup trench 48b is disposed in the emitter region 3a; and the third pickup trench 48c may be located in the emitter region 3a (e.g., Figure 6 ) or the gate region 3b (e.g. Figure 7 The fourth pickup groove 48d is located in the emitter region 3a.
[0047] In terms of the electrical connection path, the first pickup trench 48a is used to connect to (or pick up) a top electrode of the gate trench 44, the second pickup trench 48b is used to connect to (or pick up) a dummy top electrode of the gate trench 44, and the third pickup trench 48c is used to connect to (or pick up) a dummy shield electrode of the gate trench 44. Figure 6 and Figure 7 (All examples are), the fourth pickup groove 48d is used to connect (or pick up) the emitter region 3a.
[0048] Figure 6 For a standard version (STD) IGBT, the width W is less than the distance D, but greater than the length of the first pickup groove 48a in the first lateral direction Y; and Figure 7 For high-frequency (HF) IGBTs, the width W is greater than the distance D. And... Figure 6 and Figure 7 In this configuration, the wiring configuration formed by the gate trench 44, the first pickup trench 48a, the second pickup trench 48b, the third pickup trench 48c, and the fourth pickup trench 48d is the same, with the only difference being the width W of the gate region 3b.
[0049] The first pickup trench 48a is aligned with a first horizontal imaginary line 50a, while the third pickup trench 48c is aligned with a second horizontal imaginary line 50b. The first horizontal imaginary line 50a and the second horizontal imaginary line 50b are separated by a distance D, which is defined as the furthest distance between the first pickup trench 48a and the third pickup trench 48c in the first lateral direction Y. In one example, the distance D is greater than 0 and may be greater than a minimum threshold. The distance D is within a range, the upper and lower limits of which are designed based on the width W of the gate region 3b.
[0050] In summary, the pick-up trench (or metal contact) wiring structure disclosed herein can be applied to various specifications of the same type of trench power semiconductor devices, particularly suitable for shielded gate trench power semiconductor devices, by changing only one masking layer. Furthermore, since the modified masking layer is used to form the metal contact, the precision requirements are slightly lower, and the differences between different specifications of the masking layer (or metal contact wiring structure) are only in geometric dimensions. Therefore, process complexity and cost can be significantly reduced, production efficiency improved, and design flexibility achieved.
[0051] [Symbol Explanation]
[0052] 1: Semiconductor devices
[0053] 1a: Gate pad area
[0054] 1b: Gate channel region
[0055] 1c: Active Zone
[0056] 1d: Terminal area
[0057] 10: Semiconductor substrate
[0058] 11: Drift Layer
[0059] 11a: Main surface
[0060] 12: First doped region
[0061] 13: Second doped region
[0062] 14, 14a, 14b: Gate trenches
[0063] 141: Gate oxide
[0064] 142: Gate section
[0065] 143: Shielding section
[0066] 15: Intermediate layer
[0067] 17a: Gate metal
[0068] 17b: Source metal
[0069] 18: Drain Metal
[0070] 18a: First pickup groove
[0071] 18b: Second Pickup Groove
[0072] 18c: Third Pickup Groove
[0073] 18d: Fourth Pickup Groove
[0074] 20a: First horizontal imaginary line
[0075] 20b: Second level imaginary line
[0076] 3a: Emitter region
[0077] 3b: Gate region
[0078] 44: Gate trench
[0079] 48a: First pickup groove
[0080] 48b: Second pickup groove
[0081] 48c: Third Pickup Groove
[0082] 48d: Fourth Pickup Groove
[0083] 50a: First horizontal imaginary line
[0084] 50b: Second level imaginary line
[0085] Z: Normal direction
[0086] Y: first horizontal direction
[0087] X: Second horizontal direction
[0088] Z: Normal direction
[0089] D: Distance
[0090] W: Width.
Claims
1. A high-speed switching shielded gate trench power semiconductor device, characterized in that, include: A semiconductor substrate; A drift layer having a first conductivity type is disposed on the semiconductor substrate and having a main surface; A first doped region having a second conductivity type opposite to the first conductivity type and disposed in the drift layer, the first doped region extending laterally and adjacent to the main surface; A second doped region having the first conductivity type and disposed in the first doped region, the second doped region extending laterally and adjacent to the main surface; Multiple gate trenches pass through the first doped region and the second doped region along a depth direction perpendicular to the main surface. The gate trenches extend laterally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each gate trench includes a first segment and a second segment in the first direction. Multiple gates are disposed in the first section of the gate trench. Each gate includes a gate portion located in the gate trench, a first shield portion located in the gate trench and below the gate portion, and a first insulating portion located in the gate trench and electrically isolating the gate portion from the first shield portion. Multiple shielding regions are disposed in the second section of the gate trench. Each shielding region includes a second shielding portion located in the gate trench and a second insulating portion located in the gate trench and electrically isolating the second shielding portion. An intermediate layer is disposed on the main surface; A first pickup trench extends through the intermediate layer to the first segment of the gate trench, and the first pickup trench is provided with a first conductive material connected to the gate segment; A second pickup trench extends through the intermediate layer to the second section of the gate trench, and the second pickup trench is provided with a second conductive material connected to the second shielding portion; as well as A third pickup trench extends through the intermediate layer to the gate trench and is provided with a third conductive material; The third pickup trench is selectively disposed above one of the first segment and the second segment of the gate trench, depending on the blocking voltage required by the power semiconductor device.
2. The power semiconductor device according to claim 1, characterized in that, Also includes: A gate metal layer is disposed on a gate region of the intermediate layer, and the gate metal layer is connected to the first conductive material in the first pickup trench. as well as A source metal layer is disposed on a source region of the intermediate layer, and the source metal layer connects the second conductive material in the second pickup trench and the third conductive material in the third pickup trench.
3. The power semiconductor device according to claim 1, characterized in that, Also includes: A gate metal layer is disposed on a gate region of the intermediate layer, and the gate metal layer connects the first conductive material in the first pickup trench and the third conductive material in the third pickup trench. as well as A source metal layer is disposed on a source region of the intermediate layer, and the source metal layer is connected to the second conductive material in the second pickup trench.
4. The power semiconductor device according to claim 1, characterized in that, Also includes: A drain metal layer is disposed on a bottom surface of the semiconductor substrate.
5. The power semiconductor device according to claim 1, characterized in that, It also includes a fourth pickup trench that extends through the intermediate layer into the first doped region, the fourth pickup trench being provided with a fourth conductive material connected to the first doped region.
6. The power semiconductor device according to claim 1, characterized in that, Also includes: A gate metal layer is disposed on a gate region of the intermediate layer, and the gate metal layer is connected to the first conductive material in the first pickup trench. as well as An emitter metal layer is disposed on an emitter region of the intermediate layer, and the emitter metal layer connects the second conductive material in the second pickup trench and the third conductive material in the third pickup trench.
7. The power semiconductor device according to claim 1, characterized in that, Also includes: A gate metal layer is disposed on a gate region of the intermediate layer, and the gate metal layer connects the first conductive material in the first pickup trench and the third conductive material in the third pickup trench. as well as An emitter metal layer is disposed on an emitter region of the intermediate layer, and the emitter metal layer is connected to the second conductive material in the second pickup trench.
8. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device is a transistor, which is a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.
9. A high-speed switching shielded gate trench power semiconductor device, characterized in that, include: A semiconductor substrate; A drift layer having a first conductivity type is disposed on the semiconductor substrate and having a main surface; A first doped region having a second conductivity type opposite to the first conductivity type and disposed in the drift layer, the first doped region extending laterally and adjacent to the main surface; A second doped region having the first conductivity type and disposed in the first doped region, the second doped region extending laterally and adjacent to the main surface; Multiple gate trenches extend through the first doped region and the second doped region along a depth direction perpendicular to the main surface. The gate trenches extend laterally along a first direction and are spaced apart from each other in a second direction orthogonal to the first direction. Each gate trench includes a first segment and a second segment in the first direction. Viewed from a plan view of the main surface, the gate trenches include a first group and a second group, with each first group located between adjacent second groups. Multiple gates are disposed in the first section of the gate trench. Each gate includes a gate portion located in the gate trench, a first shield portion located in the gate trench and below the gate portion, and a first insulating portion located in the gate trench and electrically isolating the gate portion from the first shield portion. Multiple shielding regions are disposed in the second section of the gate trench. Each shielding region includes a second shielding portion located in the gate trench and a second insulating portion located in the gate trench and electrically isolating the second shielding portion. An intermediate layer is disposed on the main surface; A first contact is disposed on the gate trench in the first group, the first contact extends through the intermediate layer to the first segment of the gate trench, and the first contact is electrically connected to the gate segment; and A second contact is disposed on the gate trench in the second group, the second contact passes through the intermediate layer to the second segment of the gate trench, and the second contact is electrically connected to the second shielding portion; Viewed from the plan view of the main surface, the first contact and the second contact are arranged side by side with the gate trench. The first contact and the second contact are respectively arranged along a first horizontal imaginary line and a second horizontal imaginary line in the second direction, and the first horizontal imaginary line and the second horizontal imaginary line are separated by a distance.
10. The power semiconductor device according to claim 9, characterized in that, The power semiconductor device is a transistor, which is a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.