MOS device and method of manufacturing the same

Abstract

The application relates to a MOS device and a manufacturing method thereof, which comprises the following steps: obtaining a substrate with an insulating isolation structure and a gate material layer; performing photoetching to form a target photoresist on the gate material layer; performing ion implantation on the substrate with the target photoresist as an implantation barrier layer to form a source-drain region between the target photoresist and the insulating isolation structure; performing trimming on the target photoresist through a trimming process to shorten the length of the target photoresist in the direction of the device channel length to the target length of the gate; etching the gate material layer to form a gate with the trimmed target photoresist as an etching barrier layer; and forming an LDD region in the substrate. The application can obtain a required and controllable long channel length, thereby improving the HCI reliability of the device. Meanwhile, the size of the gate can also be small enough to ensure the current capacity of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a MOS device, and also to a method for manufacturing a MOS device. Background Technology

[0002] 5V MOS (Metal-O-Semiconductor Field-Effect Transistor) devices are widely used in semiconductor I / O (input / output) circuits. With the continuous miniaturization of core device feature sizes, various secondary effects are causing increasingly prominent reliability issues for 5V MOS devices. Among these, the HCI (Hot Carrier Injection) reliability of 5V MOS devices is particularly evident. As the size shrinks, the risk of HCI increases dramatically. Summary of the Invention

[0003] Therefore, it is necessary to provide a MOS device and its manufacturing method that can improve the HCI reliability of the device.

[0004] A method for manufacturing a MOS device includes: obtaining a substrate having an insulating isolation structure and a gate material layer; performing photolithography to form a target photoresist on the gate material layer; using the target photoresist as an implantation barrier layer, performing ion implantation into the substrate to form a source / drain region between the target photoresist and the insulating isolation structure; trimming the target photoresist using a trimming process to shorten the length of the target photoresist in the device channel length direction to a target gate length; using the trimmed target photoresist as an etch barrier layer to etch the gate material layer to form a gate; and forming an LDD region in the substrate.

[0005] The aforementioned method for manufacturing MOS devices involves forming a target photoresist before gate etching to define the size of the source / drain regions. After the source / drain regions are formed, a trimming process is used to shorten the target photoresist to the target gate size, thereby obtaining the desired gate size. Because a target photoresist larger than the gate size is used as the injection barrier layer for the source / drain regions, a required and controllable long channel length can be obtained, thus improving the device's high-current integration (HCI) reliability. Simultaneously, the gate size can be adjusted to a sufficiently small size through trimming, ensuring the device's current capability. The formation of the source / drain regions and the gate requires only one photolithography plate, avoiding any increase in manufacturing costs due to additional photolithography plates.

[0006] In one embodiment, after the step of forming the LDD region in the substrate, the step of forming sidewalls on both sides of the gate is further included.

[0007] In one embodiment, the step of forming the target photoresist on the gate material layer is wherein the length of the formed target photoresist in the device channel length direction is greater than the distance between the outer edge of the sidewall on one side of the gate and the outer edge of the sidewall on the other side of the gate.

[0008] In one embodiment, the step of trimming the target photoresist includes dry etching the target photoresist.

[0009] In one embodiment, the MOS device is a CMOS device, or the MOS device is an NMOS device, or the MOS device is a PMOS device.

[0010] In one embodiment, the step of obtaining a substrate having an insulating isolation structure and a gate material layer further includes the formation of a well region in the obtained substrate; the step of forming a source / drain region between the target photoresist and the insulating isolation structure involves forming the source / drain region in the well region, wherein the conductivity type of the well region is opposite to that of the source / drain region.

[0011] In one embodiment, the step of forming the target photoresist on the gate material layer is wherein the formed target photoresist is 0.1 to 0.3 micrometers longer than the gate in the device channel length direction.

[0012] In one embodiment, in the step of forming the target photoresist on the gate material layer, the formed target photoresist has a length of 0.682 micrometers in the device channel length direction, and the gate has a length of 0.5 micrometers in the device channel length direction.

[0013] In one embodiment, the insulating isolation structure is a shallow trench isolation structure.

[0014] In one embodiment, the gate material layer is a polycrystalline silicon layer.

[0015] In one embodiment, the LDD region has the same conductivity type as the source / drain region, and the doping concentration of the LDD region is lower than that of the source / drain region.

[0016] A MOS device is manufactured by the manufacturing method of a MOS device described in any of the foregoing embodiments.

[0017] In one embodiment, the MOS device includes: a substrate; a gate located on the substrate; sidewalls located on both sides of the gate; an insulating isolation structure located in the substrate; a source / drain region located in the substrate and between the insulating isolation structure and the sidewalls; and an LDD region located below the sidewalls, extending on one side below the gate and on the other side to the source / drain region; the LDD region and the source / drain region have a first conductivity type, and the doping concentration of the LDD region is less than the doping concentration of the source / drain region.

[0018] The aforementioned MOS devices are manufactured using the MOS device manufacturing method described in any of the foregoing embodiments, thus achieving the required and controllable long channel length, thereby improving the HCI reliability of the device. Simultaneously, the gate size can be sufficiently small to ensure the device's current capability.

[0019] In one embodiment, the insulating isolation structure is a shallow trench isolation structure.

[0020] In one embodiment, the gate is a polysilicon gate.

[0021] In one embodiment, the MOS device further includes a well region located in the substrate, wherein the source / drain region and the LDD region are located in the well region. The well region has a second conductivity type, and the first and second conductivity types are opposite conductivity types.

[0022] In one embodiment, the spacing between adjacent source and drain regions is 0.682 micrometers, and the gate has a length of 0.5 micrometers in the device channel length direction. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 This is a flowchart of a method for manufacturing a MOS device according to an embodiment of this application.

[0025] Figures 2a to 2f According to one embodiment of this application Figure 1 The diagram shows a cross-sectional view of the MOS device during the manufacturing process using the method shown. Detailed Implementation

[0026] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0033] In an exemplary MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) device, the device channel length is determined by both the gate length and the spacer width. Since spacer etching is photoresist-free, the spacer width is determined by the thickness of the spacer material layer and the gate (e.g., a polysilicon gate) thickness. As the linewidth decreases, the thickness of the spacer material layer decreases accordingly (to ensure spacer filling performance), while the thickness of the polysilicon gate decreases (to improve gate etching capability), which leads to a further reduction in spacer width. Table 1 shows the relevant parameters for the channel length of exemplary 5V CMOS devices at certain process nodes. The gate length remains constant at 0.5 micrometers for each process node (not shown in Table 1), but the spacer width decreases in smaller linewidth processes, resulting in a shorter channel length and consequently, decreased HCI (Hot carrier injection) reliability.

[0034] Table 1

[0035]

[0036] To improve the high-frequency induction (HCI) reliability and lifespan of 5V MOS devices using small linewidth processes, one exemplary approach is to add a compensating sidewall (offset spacer). This involves adding an offset spacer step before the normal spacer, followed by LDD implantation. The introduction of the offset spacer structure increases the source / drain implantation range (~70 nm), compensating for the shrinking spacer size caused by the small linewidth, thereby improving short-channel effect (SCE) and hot carrier injection effect (HCI). Another exemplary approach is to directly increase the gate size.

[0037] The first approach described above involves a complex process for forming the offset spacer. The offset spacer etching is photoresist-free, requiring precise morphology control and carrying the risk of trench breakage (due to the absence of LDD implantation beneath the offset spacer, resulting in no overlap between the source / drain and the LDD, leading to trench breakage). Furthermore, the increase in offset spacer width is very limited; increasing the thickness of the offset spacer material layer has little impact on its width. The second approach, however, sacrifices the device's current-carrying capacity.

[0038] This application proposes a method for manufacturing a MOS device that compensates for the impact of reduced spacer width on channel length by changing the process flow, ensuring the HCI reliability of the device, and without sacrificing the device's current capability.

[0039] Figure 1 This is a flowchart of a method for manufacturing a MOS device according to an embodiment of this application, including the following steps:

[0040] S110, Obtain a substrate with an insulating isolation structure and a gate material layer formed thereon.

[0041] See Figure 2a An insulating isolation structure 240 is formed in the substrate 210, and a gate material layer 23 is formed on the substrate 210. In one embodiment of this application, a well region 212 is formed in the substrate 210 obtained in step S110. The well region 212 has a second conductivity type. Figure 2a The device shown is an NMOS, with the first conductivity type being N-type and the second conductivity type being P-type. For a PMOS device, the first conductivity type is P-type and the second conductivity type is N-type.

[0042] In one embodiment of this application, the substrate 210 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 2a In the embodiment shown, the substrate 210 is made of monocrystalline silicon.

[0043] In one embodiment of this application, a gate dielectric layer is further formed below the gate material layer 23. Figure 2a (Not shown in the text). The gate dielectric layer may include conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may include dielectric materials with generally higher dielectric constants having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0044] In one embodiment of this application, the gate material layer 23 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate material layer 23.

[0045] In one embodiment of this application, the insulating isolation structure 240 is a shallow trench isolation structure (STI).

[0046] S120, perform photolithography to form the target photoresist on the gate material layer.

[0047] The photolithography used for source / drain injection forms a target photoresist 292 that serves as a barrier layer for source / drain injection. (See [link to documentation]). Figure 2b The formed target photoresist 292 is positioned along the length of the device channel (i.e., Figure 2b The ADI (After Develop Inspection) CD on the left and right sides of the device—that is, the critical dimension after development—is set as the design channel length of the MOS device.

[0048] S130, using the target photoresist as an implantation barrier layer, performs ion implantation to form source / drain regions.

[0049] Using the target photoresist 292 as an implantation barrier layer, ion implantation (implanting ions of the first conductivity type) is performed into the substrate 210, forming source / drain regions 224 in the substrate 210 between the target photoresist 292 and the insulating isolation structure 240. See [link / reference] Figure 2c .

[0050] S140, trim the target photoresist to shorten it to the gate target length.

[0051] The target photoresist 292 is trimmed by a trimming process, so that the length of the target photoresist 292 in the device channel length direction is shortened to the gate target length, thus obtaining the gate photolithography pattern 294. Figure 2d The distance between the two dashed lines represents the length of the target photoresist 292 before trimming, and it is also the distance between the adjacent source / drain regions 224 on both sides of the gate 234. Photoresist (PR) trimming is often used to precisely control the AEI (After Etching Inspection) CD of a product, i.e., the critical dimensions after etching. The principle of the photoresist trimming process is to use etching gas to dry-etch the photolithographic pattern (photoresist), thereby further correcting the photolithographic pattern to precisely control its accuracy and achieve the purpose of controlling the AEI CD.

[0052] S150 uses the trimmed target photoresist as an etch barrier layer to etch the gate material layer to form the gate.

[0053] The trimmed target photoresist, i.e., the gate photolithography pattern 294, is etched to obtain the gate 234. See [link / reference]. Figure 2d .

[0054] S160 forms an LDD region in the substrate.

[0055] LDD (lightly doped drain) implantation (implanting ions of the first conductivity type) is performed to form LDD region 222. The implantation dose of LDD is less than the source / drain implantation dose in step S130, and the formed LDD region 222 has the first conductivity type and the doping concentration is less than the doping concentration of the source / drain region 224.

[0056] The above-described method for manufacturing a MOS device involves forming a target photoresist 292 before gate etching (step S150) to define the size of the source / drain regions 224. After the source / drain regions 224 are formed, a trimming process is used to shorten the target photoresist 292 to the target gate size, thereby obtaining the desired gate size. Since a target photoresist 292, which is larger than the gate size, is used as the injection barrier layer for the source / drain regions 224, a required and controllable long channel length can be obtained, thereby improving the device's HCI reliability. Simultaneously, the gate size can be adjusted to a sufficiently small size through trimming, ensuring the device's current capability. The formation of the source / drain regions 224 and the gate 234 requires only one photomask, without increasing manufacturing costs due to the addition of a photomask.

[0057] Figures 2a to 2f This demonstrates an example of improving HCI reliability by increasing the channel length of an NMOS device. Figures 2a to 2f In the illustrated embodiment, well region 212 is a P-well, source / drain region 224 is an N+ region, LDD region 222 is an N-type region, and substrate 210 is a P-type substrate. The scheme of this embodiment can also be applied to the fabrication of PMOS devices or CMOS devices. For PMOS devices, and... Figures 2a to 2f The difference in the illustrated embodiment is that the first conductivity type is P-type and the second conductivity type is N-type. Accordingly, the well region 212 is an N-well, the source / drain region 224 is a P+ region, and the LDD region 222 is a P-type region. For CMOS devices, NMOS and PMOS need to be fabricated separately.

[0058] In one embodiment of this application, after step S160, a step of forming sidewalls 252 on both sides of the gate 234 is further included. Specifically, sidewall material can be deposited on the front side of the wafer to form a sidewall material layer covering the substrate 210 and the gate 234, and then the sidewall material can be etched (without photoresist etching) to form the sidewalls 252.

[0059] In one embodiment of this application, the length of the target photoresist 292 in the device channel length direction is greater than the distance between the outer edge of the sidewall 252 on one side of the gate 234 and the outer edge of the sidewall 252 on the other side of the gate 234, that is, the source / drain regions 224 are spaced a certain distance from the adjacent sidewalls 252 to obtain sufficient channel length. In one embodiment of this application, the length of the target photoresist 292 in the device channel length direction is 0.1 to 0.3 micrometers larger than the length of the gate 234 in the device channel length direction (affected by the manufacturing process). Table 2 shows the channel length related parameters of an NMOS device with a critical size of 0.11 micrometers in one embodiment of the present invention, and compares them with those with critical sizes of 0.18 micrometers, 0.13 micrometers, and 0.11 micrometers. In the embodiment of the present invention corresponding to Table 2, the length of the target photoresist 292 in the device channel length direction (i.e., Poly ADI CD) is 0.682 micrometers, and the length of the gate 234 in the device channel length direction (i.e., Poly AEI CD) is 0.5 micrometers. Among them, Poly ADI CD can be the smallest size allowed by the current process. The size of Poly ADI CD should meet the HCI reliability requirements. The size in Table 2 is only an example. Poly ADI CD can be any size that meets the HCI reliability requirements by increasing the channel length.

[0060] Table 2

[0061]

[0062] This application provides a MOS device manufactured using the MOS device manufacturing method described in any of the foregoing embodiments. Please refer to... Figures 2a to 2f In one embodiment of this application, the MOS device includes:

[0063] 210 substrate;

[0064] Gate 234 is located on substrate 210;

[0065] Sidewalls 252 are located on both sides of gate 234;

[0066] An insulating isolation structure 240 is located in the substrate 210;

[0067] The source / drain region 224 is located in the substrate 210 and between the insulating isolation structure 240 and the sidewall 252;

[0068] LDD region 222 is located below sidewall 252, and extends to the area below gate 234 on one side and to source / drain region 224 on the other side; LDD region 222 and source / drain region 224 have a first conductivity type, and the doping concentration of LDD region 222 is less than that of source / drain region 224.

[0069] In the aforementioned MOS device, the spacing between adjacent source and drain regions 224 is greater than the spacing between the outer edge of the sidewall 252 on one side of the gate 234 and the outer edge of the sidewall 252 on the other side of the gate 234. Therefore, the channel length of the device is long enough to improve the HCI reliability of the device.

[0070] In one embodiment of this application, the insulating isolation structure 240 is a shallow trench isolation structure.

[0071] In one embodiment of this application, the gate 234 is a polysilicon gate.

[0072] In one embodiment of this application, the MOS device further includes a well region 212 located in a substrate 210. A source / drain region 224 and an LDD region 222 are located in the well region 212, which has a second conductivity type.

[0073] In one embodiment of this application, the spacing between adjacent source / drain regions 224 (i.e. Figure 2d The distance between the two arrows in the image is 0.682 micrometers – that is, the channel length is 0.682 micrometers, and the length of the gate 234 in the device channel length direction is 0.5 micrometers.

[0074] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0075] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a MOS device, characterized in that, include: Obtain a substrate with an insulating isolation structure and a gate material layer formed thereon; Photolithography is performed to form the target photoresist on the gate material layer; Using the target photoresist as an injection barrier layer, ion implantation is performed into the substrate to form a source / drain region between the target photoresist and the insulating isolation structure; The target photoresist is trimmed using a trimming process, so that the length of the target photoresist in the device channel length direction is shortened to the gate target length; Using the trimmed target photoresist as an etch barrier layer, the gate material layer is etched to form a gate; An LDD region is formed in the substrate.

2. The method for manufacturing a MOS device according to claim 1, characterized in that, Following the step of forming the LDD region in the substrate, the method further includes the step of forming sidewalls on both sides of the gate.

3. The method for manufacturing a MOS device according to claim 2, characterized in that, In the step of forming the target photoresist on the gate material layer, the length of the formed target photoresist in the device channel length direction is greater than the distance between the outer edge of the sidewall on one side of the gate and the outer edge of the sidewall on the other side of the gate.

4. The method for manufacturing a MOS device according to claim 1, characterized in that, The step of trimming the target photoresist includes dry etching the target photoresist.

5. The method for manufacturing a MOS device according to claim 1, characterized in that, The MOS device is a CMOS device, or the MOS device is an NMOS device, or the MOS device is a PMOS device.

6. The method for manufacturing a MOS device according to claim 1, characterized in that, The step of obtaining a substrate having an insulating isolation structure and a gate material layer includes the formation of a well region in the obtained substrate; the step of forming a source / drain region between the target photoresist and the insulating isolation structure involves forming the source / drain region in the well region, wherein the conductivity type of the well region is opposite to that of the source / drain region.

7. The method for manufacturing a MOS device according to claim 1, characterized in that, In the step of forming the target photoresist on the gate material layer, the formed target photoresist is 0.1 to 0.3 micrometers longer than the gate in the length direction of the device channel.

8. The method for manufacturing a MOS device according to claim 1, characterized in that, The insulating isolation structure is a shallow trench isolation structure; and / or the gate material layer is a polysilicon layer.

9. The method for manufacturing a MOS device according to claim 1, characterized in that, The LDD region has the same conductivity type as the source / drain region, and the doping concentration of the LDD region is lower than that of the source / drain region.

10. A MOS device, characterized in that, It is manufactured by the manufacturing method of the MOS device according to any one of claims 1-9.

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