Semiconductor device, method of manufacture, power module, conversion circuit and vehicle

Abstract

This invention discloses a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body comprising a well region and a first region; the first region being configured with a first conductivity type and located on a first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the first surface having at least two trenches arranged at intervals; and at least one third region and at least one fourth region, both of the second conductivity type, and respectively located on the side of different trenches near the second surface; the distance from the third region to its corresponding trench is greater than the distance from the fourth region to its corresponding trench, and the distance between the third region and the fourth region is greater than zero; a gate located in a trench; a source located on the first surface; and a drain located on the second surface. The technical solution provided by this invention maintains low on-resistance and high cell density while suppressing electric field concentration at the bottom of the trench and reducing Miller capacitance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) possesses excellent physical and electrical properties. Compared to silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices fabricated using SiC can not only operate stably at higher temperatures but are also suitable for high-voltage and high-frequency applications.

[0003] SiC MOSFETs have evolved from planar to trench types. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. Trench semiconductor devices have advantages such as small cell size and high current density; however, in trench semiconductor devices, the high electric field at the bottom and corners of the trench increases the electric field on the gate insulating layer, which in turn makes the gate insulating layer more susceptible to breakdown. Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art, for reference. Figure 1 Ion implantation can be used to form a semi-enclosed P+ region 01 on one sidewall and part of the bottom of the gate trench as an electric field shielding structure. However, in existing trench structures, the overlap area between the gate and source, and between the gate and drain, as well as the structural layout, result in high parasitic capacitance, especially Miller capacitance (Cgd), which severely limits the performance and efficiency improvement of the device in high-frequency applications. Moreover, under high-voltage blocking conditions, electric field lines tend to accumulate in the gate oxide layer 02 in the trench corner region, forming extremely high electric field peaks, which still poses a risk of breakdown. If the bottom of each trench is completely covered with the P+ region 01 to enhance the shielding effect, the spacing between the P+ regions 01 of adjacent trenches will be reduced, resulting in a narrower current conduction path and increased on-resistance. If the trench spacing is increased to widen the current path, the cell density will be sacrificed, which is not conducive to the miniaturization and integration improvement of the device.

[0004] Therefore, how to effectively suppress electric field concentration at the bottom of the trench and reduce Miller capacitance while maintaining low on-resistance and high cell density has become a key problem that needs to be solved in the current trench semiconductor device structure design. Summary of the Invention

[0005] This invention provides a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle, which effectively suppress electric field concentration at the bottom of the trench and reduce Miller capacitance while maintaining low on-resistance and high cell density.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is configured with the first conductivity type and located on the first surface, and the well region is configured with the second conductivity type and located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different, and the first surface is provided with at least two trenches arranged at intervals; the semiconductor body further includes at least one third region and at least one fourth region, both configured with the second conductivity type, and respectively located on the side of different trenches near the second surface; wherein, the distance from the third region to the corresponding trench is greater than the distance from the fourth region to the corresponding trench, and in the direction from the first surface to the second surface, the distance between the third region and the fourth region is greater than zero; The gate is located in the trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0007] Optionally, the at least two spaced-apart trenches include a plurality of first trenches and second trenches that extend along a first direction and are alternately arranged along a second direction; the first direction and the second direction intersect each other; Each first trench has a third region on the side near the second surface, and each third region extends along the first direction; each second trench has a fourth region on the side near the second surface, and each fourth region extends along the first direction.

[0008] Optionally, the semiconductor body further includes a plurality of columnar regions configured as a second conductivity type; each columnar region is located between two adjacent trenches and extends from the first surface to the second surface; The columnar region is in contact with the well region, and the columnar region is also in contact with at least one of the third region and the fourth region; the length of the columnar region in the first direction is less than the length of the trench in the first direction.

[0009] Optionally, the orthographic projection of the third region on the second surface overlaps with the orthographic projection of the adjacent fourth region on the second surface. And / or, the orthographic projection of the first groove onto the second surface lies within the orthographic projection of the third region onto the second surface; And / or, the orthographic projection of the second groove onto the second surface lies within the orthographic projection of the fourth region onto the second surface.

[0010] Optionally, the distance from the fourth region to the corresponding second trench is zero.

[0011] Optionally, the semiconductor body further includes a current spreading region and a drift region; The current extension region is configured with a first conductivity type and is located on the side of the well region away from the first surface; the drift region is configured with a first conductivity type and is located on the side of the current extension region away from the first surface; the ion doping concentration of the current extension region is greater than the ion doping concentration of the drift region; The trench extends from the first surface to the second surface into the current extension region.

[0012] Optionally, the semiconductor body further includes: The sixth region is located between the third region and the trench corresponding to the third region; the sixth region is configured with a first conductivity type, and the ion doping concentration of the sixth region is greater than the ion doping concentration of the current extension region; And / or, a seventh region, located between the fourth region and the drift region, wherein the seventh region is configured with a first conductivity type and the ion doping concentration of the seventh region is greater than the ion doping concentration of the current extension region.

[0013] Optionally, the semiconductor body further includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer. The third epitaxial layer, configured as a first semiconductor type, is located on the side of the second epitaxial layer away from the substrate; the ion doping concentration of the third epitaxial layer is greater than that of the second epitaxial layer. The drift region is disposed in the first epitaxial layer; the current extension region includes a first current extension sub-region and a second current extension sub-region; the first current extension sub-region, at least a portion of the third region, the fourth region, the sixth region and the seventh region are disposed in the second epitaxial layer; the second current extension sub-region, the well region and the first region are disposed in the third epitaxial layer.

[0014] Optionally, along the direction from the first surface to the second surface, the sixth region is composed of multiple consecutive sixth sub-regions, and the concentration of the multiple sixth sub-regions gradually increases; And / or, along the direction from the first surface to the second surface, the seventh region is composed of a plurality of consecutive seventh sub-regions, and the concentration of the plurality of seventh sub-regions gradually increases.

[0015] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device described in any embodiment of the present invention; comprising, A semiconductor body is formed, and at least two trenches spaced apart are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with the first conductivity type and is located on the first surface, and the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The semiconductor body also includes at least one third region and at least one fourth region, both configured with the second conductivity type, and respectively located on the side of different trenches near the second surface. The distance from the third region to the corresponding trench is greater than the distance from the fourth region to the corresponding trench, and the distance between the third region and the fourth region is greater than zero in the direction from the first surface to the second surface. A gate is formed in the trench; A source electrode is formed on the first surface; The second surface forms the drain electrode.

[0016] Optionally, forming a semiconductor body and forming at least two spaced trenches on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; the first epitaxial layer is used to form the drift region of the semiconductor device; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; A third region and a fourth region are formed in the second epitaxial layer; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a first conductivity type; A first region and a well region are formed in the third epitaxial layer; the region outside the first region and the well region in the third epitaxial layer is used to form a second current-extending sub-region; At least two spaced trenches are formed on the surface of the third epitaxial layer on the side away from the substrate.

[0017] Optionally, a third region is formed in the second epitaxial layer, including: A first mask layer is formed on the side of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a plurality of first openings extending along a first direction and arranged along a second direction, the first openings exposing the surface of the second epitaxial layer; Based on the patterned first mask layer, a plurality of third regions extending along the first direction and arranged along the second direction are formed in the region of the second epitaxial layer adjacent to the first epitaxial layer. The semiconductor body further includes a sixth region located between the third region and the trench corresponding to the third region; the sixth region is composed of a plurality of consecutive sixth sub-regions along the direction from the first surface to the second surface; the first mask layer based on the patterned layer, after forming a plurality of third regions extending in the first direction and arranged in the second direction in the region of the second epitaxial layer adjacent to the first epitaxial layer, further includes: Using the patterned first mask layer as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer to form multiple consecutive sixth sub-regions; wherein, before each implantation of first conductivity type doped ions, a first sidewall is formed on the existing first opening sidewall to define a new implantation region.

[0018] Optionally, a fourth region is formed in the second epitaxial layer, including: The first mask layer is removed, and a second mask layer is formed on the side of the second epitaxial layer away from the substrate. The second mask layer is then patterned. The patterned second mask layer includes a plurality of second openings extending along a first direction and arranged along a second direction. The second openings expose the surface of the second epitaxial layer. The first openings and the second openings are offset from each other. Based on the patterned second mask layer, a plurality of fourth regions extending in the first direction and arranged in the second direction are formed on the surface of the second epitaxial layer away from the first epitaxial layer; The semiconductor body further includes a seventh region located between the fourth region and the drift region; the seventh region is composed of a plurality of consecutive seventh sub-regions along the direction from the first surface to the second surface; the second mask layer based on the patterned layer, after forming a plurality of fourth regions extending in the first direction and arranged in the second direction on the surface of the second epitaxial layer away from the first epitaxial layer, further includes: Using the patterned second mask layer as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer to form multiple consecutive seventh sub-regions; wherein, before each implantation of first conductivity type doped ions, a second sidewall is formed on the existing second opening sidewall to define a new implantation region; in the second epitaxial layer, the regions other than the third region, the fourth region, the sixth region, and the seventh region are used to form the first current extension sub-region.

[0019] Optionally, after forming the first region and the well region in the third epitaxial layer, the method further includes: A plurality of columnar regions are formed in the third semiconductor layer and the second semiconductor layer; the columnar regions are configured with a second conductivity type; each columnar region is located between two adjacent trench preset positions and extends from the first surface to the second surface; the columnar region is in contact with the well region, and the columnar region is also in contact with at least one of the third region and the fourth region; the length of the columnar region in the first direction is less than the length of the trench in the first direction.

[0020] According to another aspect of the present invention, a power module is provided, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0021] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0022] According to another aspect of the present invention, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the power to the load.

[0023] The technical solution provided by this invention involves setting a third region of a second conductivity type on the side of some trenches near the second surface. This third region forms a PN junction with an adjacent first conductivity type region. The capacitance generated by this PN junction is connected in series with the inherent parasitic capacitance of the gate insulating layer, thereby reducing the total gate-drain capacitance between the gate and the drain, i.e., reducing the Miller capacitance. Moreover, the third region can serve as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Simultaneously, a fourth region of the second conductivity type is set on the side of other trenches near the second surface. This fourth region forms a PN junction with an adjacent first conductivity type region. The capacitance generated by the PN junction is connected in series with the inherent parasitic capacitance of the gate insulating layer, thereby reducing the total gate-drain capacitance between the gate and drain, i.e., reducing Miller capacitance. Furthermore, the fourth region can act as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Based on this, by setting the distance from the third region to the corresponding trench to be greater than the distance from the fourth region to the corresponding trench, and the distance between the third and fourth regions to be greater than zero, the third and fourth regions can be staggered in the direction from the first surface to the second surface. That is, the third and fourth regions are located at different heights relative to the second surface. This staggered structure allows the electric field shielding structure at the bottom of the trench to maintain its shielding effect while also mitigating the problem of encroaching on the width of the lateral conduction path, maintaining sufficient current flow area between adjacent trenches. Thus, effective electric field management and capacitance reduction are achieved while avoiding the problem of forced trench spacing increases due to excessive expansion of the shielding area. This ensures both device withstand voltage and switching performance while balancing low on-resistance and high cell density, which is beneficial for device miniaturization and increased integration.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art; Figure 2 This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present invention; Figure 3This is a top view of a portion of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 4 yes Figure 3 A schematic diagram of a cross-sectional structure along line BB1 ​​in the structure shown; Figure 5 This is a cross-sectional structural schematic diagram of another semiconductor device provided in an embodiment of the present invention; Figure 6 yes Figure 3 A schematic diagram of another cross-sectional structure along line BB1 ​​in the structure shown; Figure 7 This is a cross-sectional structural schematic diagram of another semiconductor device provided in an embodiment of the present invention; Figure 8 This is a cross-sectional structural schematic diagram of another semiconductor device provided in an embodiment of the present invention; Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 10 This is a schematic cross-sectional view of step S120 in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 11 This is a schematic cross-sectional view of step S130 in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 12 This is a schematic cross-sectional view of step S1420 in a semiconductor device fabrication method provided in an embodiment of the present invention. Figures 13-14 This is a schematic cross-sectional view of step S1430 in a semiconductor device fabrication method provided in an embodiment of the present invention. Figure 15 This is a schematic cross-sectional view of step S1440 in a semiconductor device fabrication method provided in an embodiment of the present invention. Figure 16 This is a schematic cross-sectional view of step S1450 in a semiconductor device fabrication method provided in an embodiment of the present invention. Figures 17-18 This is a cross-sectional structural diagram corresponding to step S1460 in a semiconductor device fabrication method provided in an embodiment of the present invention; Figure 19 This is a schematic cross-sectional view of step S150 in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 20 This is a schematic cross-sectional view of step S160 in a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 21This is a schematic cross-sectional view of the structure after forming a columnar region in a semiconductor device fabrication method provided in an embodiment of the present invention; Figure 22 This is a top view of a portion of the structure after the columnar region is formed in a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 23 This is a cross-sectional structural diagram corresponding to step S170 in a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] This invention provides a semiconductor device. Figure 2 This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 2 Semiconductor devices include: The semiconductor body 1 is configured with a first conductivity type and includes a first surface 11 and a second surface 12 disposed opposite to each other. The semiconductor body 1 also includes a well region QJ and a first region Q1. The first region Q1 is configured with the first conductivity type and is located on the first surface 11, while the well region QJ is configured with the second conductivity type and is located on the side of the first region Q1 away from the first surface 11. The first conductivity type and the second conductivity type are different, and the first surface 11 is provided with at least two trenches arranged at intervals. The semiconductor body 1 also includes at least one third region Q3 and at least one fourth region Q4, both configured with the second conductivity type, and located on the side of different trenches close to the second surface 12. The distance from the third region Q3 to the corresponding trench is greater than the distance from the fourth region Q4 to the corresponding trench, and the distance between the third region Q3 and the fourth region Q4 is greater than zero in the direction Z from the first surface to the second surface. The gate G is located in the trench; The source electrode S is located on the first surface 11; The drain electrode D is located on the second surface 12.

[0030] The technical solution provided by this invention involves setting a third region Q3 of a second conductivity type on the side of some trenches near the second surface 12. This third region Q3 forms a PN junction with an adjacent first conductivity type region. The capacitance generated by this PN junction is connected in series with the inherent parasitic capacitance of the gate G insulating layer, thereby reducing the total gate-drain capacitance between the gate G and the drain D, i.e., reducing the Miller capacitance. Moreover, the third region Q3 can serve as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Simultaneously, a fourth region Q4 of the second conductivity type is set on the side of some other trenches near the second surface 12. This fourth region Q4 forms a PN junction with an adjacent first conductivity type region. The capacitance generated by the PN junction is connected in series with the inherent parasitic capacitance of the gate G insulating layer, thereby reducing the total gate-drain capacitance between the gate G and the drain D, i.e., reducing the Miller capacitance. Moreover, the fourth region Q4 can serve as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Based on this, by setting the distance from the third region Q3 to the corresponding trench to be greater than the distance from the fourth region Q4 to the corresponding trench, and the distance between the third region Q3 and the fourth region Q4 to be greater than zero, the third region Q3 and the fourth region Q4 can be staggered in the direction from the first surface 11 to the second surface 12, i.e., the third region Q3 and the fourth region Q4 are located at different heights relative to the second surface 12. This staggered structure allows the electric field shielding structure at the bottom of the trench to not only ensure the shielding effect but also improve the problem of encroaching on the width of the lateral conduction path, maintaining sufficient current flow area between adjacent trenches. This achieves effective electric field management and capacitance reduction while avoiding the problem of increasing trench spacing due to excessive expansion of the shielding area. Thus, while ensuring the device's withstand voltage and switching performance, it also takes into account low on-resistance and high cell density, which is conducive to the miniaturization and integration of the device.

[0031] The above are the core inventive points of this invention. The structure of the semiconductor device will be described in detail below with reference to the accompanying drawings.

[0032] The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer formed on one side of the substrate 10.

[0033] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer. In a specific embodiment of this application, both the material of the semiconductor epitaxial layer and the material of the substrate 10 can be SiC. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0034] The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. When the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer, the second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and the first surface 11 is the surface of the semiconductor epitaxial layer that is furthest from the substrate 10 away from the substrate 10. Figure 2 The semiconductor body 1 in the structure shown includes: a substrate 10; a first epitaxial layer 20, configured as a first conductivity type, located on one side of the substrate 10; a second epitaxial layer 30, configured as a first semiconductor type, located on the side of the first epitaxial layer 20 away from the substrate 10; and a third epitaxial layer 40, configured as a first semiconductor type, located on the side of the second epitaxial layer 30 away from the substrate 10. A first region Q1 and a well region QJ are disposed on the third epitaxial layer 40; a fourth region Q4 and at least a portion of the third region Q3 are disposed on the second epitaxial layer 30. A second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and a first surface 11 is the surface of the third epitaxial layer 40 away from the substrate 10. By setting three epitaxial layers and utilizing the second epitaxial layer 30 to form the third region Q3 and the fourth region Q4, the present invention allows the positions of the third region Q3 and the fourth region Q4 to be not limited by the ion implantation depth, thereby reducing the fabrication difficulty of the third region Q3 and the fourth region Q4.

[0035] Furthermore, the doping concentration of the first conductivity type doped ions in the second epitaxial layer 30 is greater than that in the first epitaxial layer 20; the doping concentration of the first conductivity type doped ions in the third epitaxial layer 40 is greater than that in the second epitaxial layer 30. By setting the doping concentration of the first conductivity type ions to increase layer by layer, the on-resistance of the device can be further reduced.

[0036] Based on this, the semiconductor body 1 in this embodiment of the invention further includes a drift region 21 and a current spreading region QK; the current spreading region QK is configured with a first conductivity type and is located on the side of the well region QJ away from the first surface 11; the drift region 21 is configured with a first conductivity type and is located on the side of the current spreading region QK away from the first surface 11; the ion doping concentration of the current spreading region QK is greater than that of the drift region 21. A trench extends from the first surface 11 to the second surface 12 into the current spreading region QK. The drift region 21 is disposed in the first epitaxial layer 20. The current spreading region QK includes a first current spreading sub-region QK1 and a second current spreading sub-region QK2, the first current spreading sub-region QK1 being disposed in the second epitaxial layer 30, and the second current spreading sub-region QK2 being disposed in the third epitaxial layer 40. The current spreading effect of the second current spreading sub-region QK2 is higher than that of the first current spreading sub-region QK1.

[0037] Based on the above embodiments, optionally, the first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0038] Figure 2 In the structure shown, the semiconductor body 1 has an N-type conductivity. Therefore, the first region Q1 has an N-type conductivity and is located on the first surface 11; the first region Q1 is a heavily doped region. The well region QJ has a P-type conductivity and is located on the side of the first region Q1 away from the first surface 11. The current extension region QK has an N-type conductivity and is located on the side of the well region QJ away from the first surface 11; the current extension region QK can also be a heavily doped region. The drift region 21 has an N-type conductivity and is located on the side of the current extension region QK away from the first surface 11; the drift region 21 can be a lightly doped region. The third region Q3 has a P-type conductivity and is located on the side of the first trench away from the first surface 11. The fourth region Q4 has a P-type conductivity and is located on the side of the second trench away from the first surface 11.

[0039] The first epitaxial layer 20 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The second epitaxial layer 30 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The third epitaxial layer 40 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The third region Q3 and the fourth region Q4 are formed by implanting P-type dopant ions into the second epitaxial layer 30, and the well region QJ is formed by implanting P-type dopant ions into the third epitaxial layer 40. The first region Q1 is formed by implanting N-type dopant ions into the third epitaxial layer 40.

[0040] In semiconductors, when N-type dopant ions (donor dopant ions, such as phosphorus) and P-type dopant ions (acceptor dopant ions, such as boron) are simultaneously doped in the same region, their effects interact through a "compensation effect." Specifically, the charge carriers (electrons and holes) of the N-type and P-type dopant ions cancel each other out. Free electrons provided by N-type dopant ions fill the holes generated by P-type dopant ions, and the final conductivity type of the material depends on the dopant concentration. If the donor concentration (N-type dopant concentration) is greater than the acceptor concentration (P-type dopant concentration), the material behaves as an N-type semiconductor, with the remaining electrons being the majority carriers; if the acceptor concentration (P-type dopant concentration) is greater than the donor concentration (N-type dopant concentration), the material behaves as a P-type semiconductor, with the remaining holes being the majority carriers; if the concentrations of both dopant ions are equal (complete compensation), the material approaches an intrinsic semiconductor with extremely low conductivity.

[0041] Based on the above embodiments, optionally, the orthographic projection of the groove on the second surface 12 extends along the first direction X. At least two spaced-apart grooves include a plurality of first and second grooves extending along the first direction X and alternately arranged along the second direction Y; the first direction X and the second direction Y intersect each other, and the first direction X and the second direction Y may be perpendicular to each other. Each first trench has a third region Q3 on the side near the second surface 12, and each third region Q3 extends along the first direction X; each second trench has a fourth region Q4 on the side near the second surface 12, and each fourth region Q4 extends along the first direction X. This allows the orthographic projections of the third region Q3 and the fourth region Q4 on the second surface 12 to alternate sequentially, meaning that the expansion of each third region Q3 in the second direction Y is not limited by the fourth region Q4, and the expansion of each fourth region Q4 in the second direction Y is not limited by the third region Q3. This further improves the electric field shielding range of the third region Q3 and the fourth region Q4 on the bottom of the gate G, and also maintains sufficient current flow area between adjacent trenches.

[0042] Optional, please continue to refer to Figure 2 The distance from the fourth region Q4 to the corresponding second trench can be zero, which allows the fourth region Q4 to cover the bottom of the corresponding second trench, further providing the electric field shielding effect of the fourth region Q4 on the second trench.

[0043] Based on the above embodiments, Figure 3 This is a top view of a portion of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 4 yes Figure 3 The diagram shows a cross-sectional structure along line BB1, wherein... Figure 3The cross-sectional structural diagram along line AA1 in the structure shown can be seen as follows: Figure 2 As shown, for reference Figures 2-4 Optionally, the semiconductor body 1 further includes a plurality of columnar regions Q2, configured as a second conductivity type; each columnar region Q2 is located between two adjacent trenches and extends from the first surface 11 to the second surface 12; the columnar region Q2 is in contact with the well region QJ, and the columnar region Q2 is also in contact with at least one of the third region Q3 and the fourth region Q4; the length of the columnar region Q2 in the first direction X is less than the length of the trench in the first direction X.

[0044] The technical solution provided by this invention, by setting the columnar region Q2 to contact the well region QJ and at least one of the third region Q3 and the fourth region Q4, allows at least one of the third region Q3 and the fourth region Q4 to be electrically connected to the source S through the columnar region Q2. Therefore, under reverse voltage, at least one of the third region Q3 and the fourth region Q4 can be grounded, thereby further enhancing the electric field shielding effect of at least one of the third region Q3 and the fourth region Q4 and alleviating the problem of electric field concentration at the bottom of the trench. Setting the length of the columnar region Q2 in the first direction X to be less than the length of the trench in the first direction X ensures that the first region Q1 and the well region QJ are provided on the sidewalls of a portion of the trench in the first direction X, thus ensuring the formation of the MOSFET structure.

[0045] Furthermore, each third region Q3 is electrically connected to the source S electrode through at least one columnar region Q2, and each fourth region Q4 is electrically connected to the source S electrode through at least one columnar region Q2, thereby further improving the overall withstand voltage of the semiconductor device.

[0046] Furthermore, each columnar region Q2 extends from the first surface 11 to the second surface 12 and contacts the well region QJ, the third region Q3, and the fourth region Q4. Thus, the source S can be electrically connected to the well region QJ, the third region Q3, and the fourth region Q4 through a single columnar region Q2. This can improve the utilization rate of the columnar region Q2 and reduce the number of columnar regions Q2, thereby further facilitating the miniaturization of the device.

[0047] Figure 3 and Figure 4 In the structure shown, columnar regions Q2 are provided on both sides of each trench; and at least two columnar regions Q2 are provided on the same side of the gate G trench, so that each third region Q3 and fourth region Q4 can be electrically connected to the source S electrode through at least two columnar regions Q2, thereby improving the uniformity of voltage on each third region Q3 and fourth region Q4.

[0048] Based on the above embodiments, refer to Figures 2-4Optionally, the orthographic projection of the first trench onto the second surface 12 is located within the orthographic projection of the third region Q3 onto the second surface 12, which can make the third region Q3 have an electric field shielding effect on the entire bottom and bottom corners of the first trench, further alleviating the problem of electric field concentration at the bottom of the first trench.

[0049] Based on the above embodiments, refer to Figures 2-4 Optionally, the orthographic projection of the second trench onto the second surface 12 is located within the orthographic projection of the fourth region Q4 onto the second surface 12, which can make the fourth region Q4 have an electric field shielding effect on the entire bottom and bottom corners of the second trench, further alleviating the problem of electric field concentration at the bottom of the second trench.

[0050] Based on the above embodiments, refer to Figure 2 Optionally, the orthographic projection of the third region Q3 on the second surface 12 partially overlaps with the orthographic projection of the adjacent fourth region Q4 on the second surface 12. That is, the orthographic projection of the third region Q3 on the second surface 12 and the orthographic projection of the adjacent fourth region Q4 on the second surface 12 can form a seamless and complete projection surface. This can further expand the electric field shielding area of ​​the third region Q3 and the fourth region Q4 while ensuring the current flow path, thus achieving the effect of shielding the electric field on the entire surface.

[0051] Based on the above embodiments, Figure 5 This is a cross-sectional structural schematic diagram of another semiconductor device provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, the semiconductor body 1 also includes: The sixth region Q6 is located between the third region Q3 and the corresponding trench of the third region Q3; the sixth region Q6 is set to the first conductivity type, and the ion doping concentration of the sixth region Q6 is greater than the ion doping concentration of the current extension region QK; the on-resistance of the semiconductor device can be further reduced through the sixth region Q6. And / or, the seventh region Q7 is located between the fourth region Q4 and the drift region 21. The seventh region Q7 is set to the first conductivity type, and the ion doping concentration of the seventh region Q7 is greater than the ion doping concentration of the current extension region QK. The on-resistance of the semiconductor device can be further reduced through the seventh region Q7.

[0052] Figure 5 In the structure shown, the semiconductor body 1 includes a sixth region Q6 located between the third region Q3 and the trench corresponding to the third region Q3, and a seventh region Q7 located between the fourth region Q4 and the drift region 21.

[0053] Further reference Figure 5Along the direction Z from the first surface 11 to the second surface 12, the sixth region Q6 is composed of multiple consecutive sixth sub-regions, and the ion concentration of the multiple sixth sub-regions gradually increases; And / or, along the direction Z from the first surface 11 to the second surface 12, the seventh region Q7 is composed of multiple consecutive seventh sub-regions, and the ion concentration of the multiple seventh sub-regions gradually increases.

[0054] For example, Figure 5 In the structure shown, the sixth region Q6 consists of two consecutive sixth sub-regions, namely sixth sub-region Q61 and sixth sub-region Q62, and the concentration of first conductivity type doped ions in sixth sub-region Q61 is greater than that in sixth sub-region Q62; the seventh region Q7 consists of two consecutive seventh sub-regions, namely seventh sub-region Q71 and seventh sub-region Q72, and the concentration of first conductivity type doped ions in seventh sub-region Q71 is greater than that in seventh sub-region Q72. Since the ion concentrations of the second current extension sub-region QK2, the first current extension sub-region QK1, and the drift region 21 gradually decrease in the Z direction from the first surface 11 to the second surface 12, setting the ion doping concentration of multiple sixth sub-regions to gradually increase in the Z direction from the first surface 11 to the second surface 12, and the ion doping concentration of multiple seventh sub-regions to gradually increase in the Z direction from the first surface 11 to the second surface 12, can improve the resistivity uniformity of the semiconductor device.

[0055] Figure 3 The cross-sectional structural diagram along line AA1 in the structure shown can be seen as follows: Figure 5 As shown, Figure 6 yes Figure 3 Another cross-sectional view of the structure along line BB1 ​​is shown in the diagram. (Refer to...) Figure 3 , Figure 5 and Figure 6 In this embodiment of the invention, the semiconductor body 1 may also include a columnar region Q2. The configuration of the columnar region Q2 is described above and will not be repeated here.

[0056] Based on the above embodiments, optionally, refer to... Figure 7 A third region Q3, comprising a portion of the thickness, is disposed within the first epitaxial layer 20, and the thickness of the third region Q3 within the first epitaxial layer 20 is close to or equal to half the thickness of the first epitaxial layer 20, thereby forming a semi-superjunction structure within the first epitaxial layer 20 through the third region Q3. Alternatively, refer to... Figure 8A third region Q3, comprising a portion of the thickness, is disposed within the first epitaxial layer 20, and the thickness of the third region Q3 within the first epitaxial layer 20 is equal to the thickness of the first epitaxial layer 20. This third region Q3 forms a superjunction structure within the first epitaxial layer 20. By forming a semi-superjunction or superjunction structure within the first epitaxial layer 20, the breakdown voltage of the semiconductor device can be further improved.

[0057] The third region Q3 located in the first epitaxial layer 20 can be formed by multiple ion implantations or by filling a second type of conductive material after deep trenching.

[0058] Based on the above embodiments, the semiconductor device may optionally include: The gate insulating layer 50 is located on the sidewall and bottom surface of the trench, that is, between the gate G and the trench wall. An interlayer insulating layer 60 is located on the side of the gate G away from the second surface 12, and is used to electrically isolate the gate G from the source S.

[0059] This invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any embodiment of this invention; Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, see reference. Figure 9 The methods for fabricating semiconductor devices include: S10. A semiconductor body is formed, and at least two trenches spaced apart are formed on the first surface of the semiconductor body; the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a first region; the first region is configured with the first conductivity type and is located on the first surface, and the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body also includes at least one third region and at least one fourth region, both configured with the second conductivity type, and respectively located on the side of different trenches near the second surface; wherein, the distance from the third region to the corresponding trench is greater than the distance from the fourth region to the corresponding trench, and in the direction from the first surface to the second surface, the distance between the third region and the fourth region is greater than zero.

[0060] S20, Forming a gate in the trench.

[0061] S30, a source electrode is formed on the first surface.

[0062] S40, a drain electrode is formed on the second surface.

[0063] The semiconductor device fabrication method provided in this invention involves forming a third region Q3 of a second conductivity type on the side of some gate G trenches near the second surface 12. This third region Q3 forms a PN junction with an adjacent first conductivity type region. The capacitance generated by this PN junction is connected in series with the inherent parasitic capacitance of the gate G insulating layer, thereby reducing the total gate-drain capacitance between the gate G and the drain D, i.e., reducing the Miller capacitance. Moreover, the third region Q3 can serve as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Simultaneously, a fourth region Q4 of the second conductivity type is provided on the side of some other gate G trenches near the second surface 12. This fourth region Q4 forms a PN junction with an adjacent first conductivity type region. The capacitance generated by the PN junction is connected in series with the inherent parasitic capacitance of the gate G insulating layer, thereby reducing the total gate-drain capacitance between the gate G and the drain D, i.e., reducing the Miller capacitance. Moreover, the fourth region Q4 can serve as an electric field shielding structure, improving the problem of electric field concentration at the bottom of the corresponding trench. Based on this, by setting the distance from the third region Q3 to the corresponding trench to be greater than the distance from the fourth region Q4 to the corresponding trench, and the distance between the third region Q3 and the fourth region Q4 to be greater than zero, the third region Q3 and the fourth region Q4 can be staggered in the direction from the first surface 11 to the second surface 12. That is, the third region Q3 and the fourth region Q4 are formed at different heights relative to the second surface 12. This staggered formation method can ensure the shielding effect of the electric field shielding structure at the bottom of the trench, while also improving the problem of the electric field shielding structure encroaching on the width of the lateral conduction path, maintaining sufficient current flow area between adjacent trenches. This achieves effective electric field management and capacitance reduction while avoiding the problem of increasing trench spacing due to excessive expansion of the shielding area. Thus, while ensuring the device's withstand voltage and switching performance, it also takes into account low on-resistance and high cell density, which is conducive to the miniaturization and integration of the device.

[0064] Optionally, step S10 forms the semiconductor body 1 and forms at least two spaced trenches on the first surface 11 of the semiconductor body 1, including: S110, providing substrate 10.

[0065] S120, A first epitaxial layer 20 is formed on one side of the substrate 10; the first epitaxial layer 20 is configured as a first conductivity type; the first epitaxial layer 20 is used to form the drift region 21 of the semiconductor device.

[0066] For details, please refer to Figure 10 The material of the substrate 10 may be the same as or different from the material of the first epitaxial layer 20. In the embodiments of the present invention, the material of the substrate 10 and the material of the first epitaxial layer 20 are the same, both of which can be SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the substrate 10, for example, both are N-type. The N-type first epitaxial layer 20 is used to form the drift region 21 of the device.

[0067] S130, a second epitaxial layer 30 is formed on the side of the first epitaxial layer 20 away from the substrate 10; the second epitaxial layer 30 is configured with a first conductivity type.

[0068] For details, please refer to Figure 11 The material of the second epitaxial layer 30 may be the same as or different from the material of the first epitaxial layer 20. In the embodiments of the present invention, the material of the second epitaxial layer 30 is the same as that of the first epitaxial layer 20, both being SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the second epitaxial layer 30. The N-type conductive ion doping concentration in the second epitaxial layer 30 is greater than that in the first epitaxial layer 20.

[0069] S140, a third region Q3 and a fourth region Q4 are formed in the second epitaxial layer 30.

[0070] Optionally, a third region Q3 is formed in the second epitaxial layer 30, including: S1410, a first mask layer 100 is formed on the side of the second epitaxial layer 30 away from the substrate 10, and the first mask layer 100 is patterned; the patterned first mask layer 100 includes a plurality of first openings K1 extending along the first direction X and arranged along the second direction Y, and the first openings K1 expose the surface of the second epitaxial layer 30.

[0071] S1420. Based on the patterned first mask layer 100, a plurality of third regions Q3 are formed in the region of the second epitaxial layer 30 adjacent to the first epitaxial layer 20, extending along the first direction X and arranged along the second direction Y.

[0072] For details, please refer to Figure 12 The material of the first mask layer 100 can be silicon dioxide. Multiple first openings K1 are formed in the first mask layer 100 through an etching process. A third region Q3 is formed by implanting P-type doped ions into the region adjacent to the first epitaxial layer 20 in the second epitaxial layer 30 through an ion implantation process.

[0073] Furthermore, regarding such Figure 4 The structure shown includes a sixth region Q6 located between the third region Q3 and the trench corresponding to the third region Q3; the sixth region Q6 is composed of multiple consecutive sixth sub-regions along the direction Z from the first surface 11 to the second surface 12; based on the patterned first mask layer 100, after forming multiple third regions Q3 extending along the first direction X and arranged along the second direction Y in the region of the second epitaxial layer 30 adjacent to the first epitaxial layer 20, the structure further includes: S1430. Using the patterned first mask layer 100 as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer 30 to form multiple consecutive sixth sub-regions; wherein, before each implantation of first conductivity type doped ions, a first sidewall T1 is formed on the existing first opening K1 sidewall to define a new implantation region.

[0074] For details, please refer to Figure 13 and Figure 14 An example is shown illustrating the formation of two consecutive sixth sub-regions. (See reference...) Figure 13 A first sidewall T1 is formed on the sidewall of the first opening K1, reducing the width of the first opening K1, thereby defining the implantation region of the sixth sub-region Q61; N-type doped ions are implanted to form the sixth sub-region. (Reference) Figure 14 A first sidewall T1 is formed again on the sidewall of the first opening K1 to thicken the first sidewall T1 and reduce the width of the first opening K1, thereby defining the implantation region of the sixth sub-region Q62; N-type doped ions are implanted to form the sixth sub-region. The material of the first sidewall T1 formed each time can be silicon nitride.

[0075] Optionally, a fourth region Q4 is formed in the second epitaxial layer 30, including: S1440, Remove the first mask layer 100, form a second mask layer 200 on the side of the second epitaxial layer 30 away from the substrate 10, and pattern the second mask layer 200; the patterned second mask layer 200 includes a plurality of second openings K2 extending along the first direction X and arranged along the second direction Y, the second openings K2 exposing the surface of the second epitaxial layer 30; the first openings K1 and the second openings K2 are staggered.

[0076] Specifically, after removing the first mask layer 100, a second mask layer 200 is formed on the side of the second epitaxial layer 30 away from the substrate 10. The material of the second mask layer 200 can be the same as or different from the material of the first mask layer 100. In other embodiments of the present invention, it is possible to... Figure 14 A first opening K1 forms a filling layer 201, the material of which can be, for example, polysilicon. After removing the first mask layer 100 and the first sidewall T1 formed by the sidewall of the first opening K1, silicon nitride material is deposited to form a second mask layer 200, which is then patterned to form a shape such as... Figure 15 The patterned second mask layer 200 includes a fill layer 201 and mask sidewalls 202 located on the sidewalls of the fill layer. The second mask layer 200 is patterned by an etching process to form a second opening K2.

[0077] S1450, Based on the patterned second mask layer 200, a plurality of fourth regions Q4 extending along the first direction X and arranged along the second direction Y are formed on the surface of the second epitaxial layer 30 away from the first epitaxial layer 20. (See reference) Figure 16 P-type doped ions are implanted into the surface of the second epitaxial layer 30 on the side away from the first epitaxial layer 20 through an ion implantation process to form a fourth region Q4.

[0078] Furthermore, regarding such Figure 4 The structure shown includes a seventh region Q7 located between the fourth region Q4 and the drift region 21. The seventh region Q7 is composed of multiple consecutive seventh sub-regions along the direction from the first surface 11 to the second surface 12. Based on the patterned second mask layer 200, after forming multiple fourth regions Q4 extending along the first direction X and arranged along the second direction Y on the surface of the second epitaxial layer 30 away from the first epitaxial layer 200, the structure further includes: S1460. Using the patterned second mask layer 200 as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer 30 to form multiple consecutive seventh sub-regions. Before each implantation of first conductivity type doped ions, a second sidewall T2 is formed on the existing second opening K2 sidewall to define a new implantation region. In the second epitaxial layer 30, the regions other than the third region Q3, the fourth region Q4, the sixth region Q6, and the seventh region Q7 are used to form the first current extension sub-region QK1.

[0079] For details, please refer to Figure 17 and Figure 18 An example is shown illustrating the formation of two consecutive seventh sub-regions. (See reference...) Figure 17 A second sidewall T2 is formed on the sidewall of the second opening K2, reducing the width of the second opening K2, thereby defining the implantation region of the seventh sub-region Q72; N-type doped ions are implanted to form the seventh sub-region Q72. (Reference) Figure 18 A second sidewall T2 is formed again on the sidewall of the second opening K2 to thicken the second sidewall T2 and reduce the width of the second opening K2, thereby defining the implantation region of the seventh sub-region Q71; N-type doped ions are implanted to form the seventh sub-region Q71. The material of the second sidewall T2 formed each time can be silicon nitride.

[0080] S150, a third epitaxial layer 40 is formed on the side of the second epitaxial layer 30 away from the substrate 10; the third epitaxial layer 40 is configured as a first conductivity type.

[0081] For details, please refer to Figure 19After removing the second mask layer 200, a third epitaxial layer 40 is formed on the side of the second epitaxial layer 30 away from the substrate 10. The material of the third epitaxial layer 40 may be the same as or different from the material of the second epitaxial layer 30. In the embodiments of the present invention, the material of the third epitaxial layer 40 is the same as that of the second epitaxial layer 30, both being SiC. The conductivity type of the third epitaxial layer 40 is the same as that of the second epitaxial layer 30. The N-type dopant concentration in the third epitaxial layer 40 is greater than that in the second epitaxial layer 30.

[0082] S160, A first region Q1 and a well region QJ are formed in the third epitaxial layer 40; the region outside the first region Q1 and the well region QJ in the third epitaxial layer 40 is used to form a second current-extended sub-region QK2. (Reference) Figure 20 ) Optional, see reference Figure 21 and Figure 22 ,in, Figure 21 for Figure 22 A schematic diagram of the cross-sectional structure along line DD1 shown. Figure 22 A schematic diagram of the cross-sectional structure along line CC1 in the structure shown can be found in [reference needed]. Figure 20 After forming the first region Q1 and the well region QJ in the third epitaxial layer 40, the following is also included: A plurality of columnar regions Q2 are formed in the third epitaxial layer 40 and the second epitaxial layer 30; the columnar regions Q2 are configured with a second conductivity type; each columnar region Q2 is located between two adjacent trench preset positions and extends from the first surface 11 to the second surface 12; the columnar region Q2 is in contact with the well region QJ, and the columnar region Q2 is also in contact with at least one of the third region Q3 and the fourth region Q4; the length of the columnar region Q2 in the first direction X is less than the length of the trench in the first direction X.

[0083] S170, at least two spaced trenches are formed on the surface of the third epitaxial layer 40 away from the substrate 10.

[0084] For details, please refer to Figure 23 At least two alternately arranged grooves 70 include a plurality of first grooves 71 and second grooves 72 that extend along a first direction X and alternately extend along a second direction Y; the first direction X and the second direction Y intersect each other, and the first direction X and the second direction Y can be perpendicular to each other; each first groove 71 is provided with a third region Q3 on the side near the second surface 12, and each third region Q3 extends along the first direction X; each second groove 72 is provided with a fourth region Q4 on the side near the second surface 12, and each fourth region Q4 extends along the first direction X.

[0085] Optionally, before forming the gate G in the trench, the method further includes forming a gate insulating layer 50 on the sidewalls and bottom surface of the trench 70.

[0086] After forming the gate G in the trench, the method further includes forming an interlayer insulating layer 60 on the side of the gate G away from the second surface 12 to electrically isolate the gate G from the source S.

[0087] Embodiments of the present invention also provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device. It has the same technical effects and will not be described again here.

[0088] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0089] According to another aspect of the present invention, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. It has the same technical effects and will not be described again here.

[0090] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is configured with the first conductivity type and located on the first surface, and the well region is configured with the second conductivity type and located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different, and the first surface is provided with at least two trenches arranged at intervals; the semiconductor body further includes at least one third region and at least one fourth region, both configured with the second conductivity type, and respectively located on the side of different trenches near the second surface; wherein, the distance from the third region to the corresponding trench is greater than the distance from the fourth region to the corresponding trench, and in the direction from the first surface to the second surface, the distance between the third region and the fourth region is greater than zero; The gate is located in the trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The at least two spaced-apart trenches include a plurality of first trenches and second trenches that extend along a first direction and are alternately arranged along a second direction; the first direction and the second direction intersect each other; Each first trench has a third region on the side near the second surface, and each third region extends along the first direction; each second trench has a fourth region on the side near the second surface, and each fourth region extends along the first direction.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor body further includes a plurality of columnar regions configured as a second conductivity type; each columnar region is located between two adjacent trenches and extends from the first surface to the second surface; The columnar region is in contact with the well region, and the columnar region is also in contact with at least one of the third region and the fourth region; The length of the columnar region in the first direction is less than the length of the groove in the first direction.

4. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the third region onto the second surface overlaps with the orthographic projection of the adjacent fourth region onto the second surface. And / or, the orthographic projection of the first groove onto the second surface lies within the orthographic projection of the third region onto the second surface; And / or, the orthographic projection of the second groove onto the second surface lies within the orthographic projection of the fourth region onto the second surface.

5. The semiconductor device according to claim 2, characterized in that, The distance from the fourth region to the corresponding second trench is zero.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The semiconductor body also includes a current spreading region and a drift region; The current extension region is configured with a first conductivity type and is located on the side of the well region away from the first surface; the drift region is configured with a first conductivity type and is located on the side of the current extension region away from the first surface; the ion doping concentration of the current extension region is greater than the ion doping concentration of the drift region. The trench extends from the first surface to the second surface into the current extension region.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor body also includes: The sixth region is located between the third region and the trench corresponding to the third region; the sixth region is configured with a first conductivity type, and the ion doping concentration of the sixth region is greater than the ion doping concentration of the current extension region; And / or, a seventh region, located between the fourth region and the drift region, wherein the seventh region is configured with a first conductivity type and the ion doping concentration of the seventh region is greater than the ion doping concentration of the current extension region.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor body also includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer. The third epitaxial layer, configured as a first semiconductor type, is located on the side of the second epitaxial layer away from the substrate; the ion doping concentration of the third epitaxial layer is greater than that of the second epitaxial layer. The drift region is disposed in the first epitaxial layer; the current extension region includes a first current extension sub-region and a second current extension sub-region; the first current extension sub-region, at least a portion of the third region, the fourth region, the sixth region and the seventh region are disposed in the second epitaxial layer; the second current extension sub-region, the well region and the first region are disposed in the third epitaxial layer.

9. The semiconductor device according to claim 7, characterized in that, Along the direction from the first surface to the second surface, the sixth region is composed of multiple consecutive sixth sub-regions, and the concentration of the multiple sixth sub-regions gradually increases; And / or, along the direction from the first surface to the second surface, the seventh region is composed of a plurality of consecutive seventh sub-regions, and the concentration of the plurality of seventh sub-regions gradually increases.

10. A method for fabricating a semiconductor device, characterized in that, For preparing the semiconductor device according to any one of claims 1 to 9; comprising: A semiconductor body is formed, and at least two trenches spaced apart are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with the first conductivity type and is located on the first surface, and the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The semiconductor body also includes at least one third region and at least one fourth region, both configured with the second conductivity type, and respectively located on the side of different trenches near the second surface. The distance from the third region to the corresponding trench is greater than the distance from the fourth region to the corresponding trench, and the distance between the third region and the fourth region is greater than zero in the direction from the first surface to the second surface. A gate is formed in the trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The process of forming a semiconductor body and forming at least two spaced trenches on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; the first epitaxial layer is used to form the drift region of the semiconductor device; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; A third region and a fourth region are formed in the second epitaxial layer; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a first conductivity type; A first region and a well region are formed in the third epitaxial layer; the region outside the first region and the well region in the third epitaxial layer is used to form a second current-extending sub-region; At least two spaced trenches are formed on the surface of the third epitaxial layer on the side away from the substrate.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, A third region is formed in the second epitaxial layer, including: A first mask layer is formed on the side of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a plurality of first openings extending along a first direction and arranged along a second direction, the first openings exposing the surface of the second epitaxial layer; Based on the patterned first mask layer, a plurality of third regions extending along the first direction and arranged along the second direction are formed in the region of the second epitaxial layer adjacent to the first epitaxial layer. The semiconductor body further includes a sixth region located between the third region and the trench corresponding to the third region; the sixth region is composed of a plurality of consecutive sixth sub-regions along the direction from the first surface to the second surface; the first mask layer based on the patterned layer, after forming a plurality of third regions extending in the first direction and arranged in the second direction in the region of the second epitaxial layer adjacent to the first epitaxial layer, further includes: Using the patterned first mask layer as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer to form multiple consecutive sixth sub-regions; wherein, before each implantation of first conductivity type doped ions, a first sidewall is formed on the existing first opening sidewall to define a new implantation region.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, A fourth region is formed in the second epitaxial layer, including: The first mask layer is removed, and a second mask layer is formed on the side of the second epitaxial layer away from the substrate. The second mask layer is then patterned. The patterned second mask layer includes a plurality of second openings extending along a first direction and arranged along a second direction. The second openings expose the surface of the second epitaxial layer. The first openings and the second openings are offset from each other. Based on the patterned second mask layer, a plurality of fourth regions extending in the first direction and arranged in the second direction are formed on the surface of the second epitaxial layer away from the first epitaxial layer; The semiconductor body further includes a seventh region located between the fourth region and the drift region; the seventh region is composed of a plurality of consecutive seventh sub-regions along the direction from the first surface to the second surface; the second mask layer based on the patterned layer, after forming a plurality of fourth regions extending in the first direction and arranged in the second direction on the surface of the second epitaxial layer away from the first epitaxial layer, further includes: Using the patterned second mask layer as a mask, multiple implantations of first conductivity type doped ions are performed sequentially within the second epitaxial layer to form multiple consecutive seventh sub-regions; wherein, before each implantation of first conductivity type doped ions, a second sidewall is formed on the existing second opening sidewall to define a new implantation region; in the second epitaxial layer, the regions other than the third region, the fourth region, the sixth region, and the seventh region are used to form the first current extension sub-region.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, After forming the first region and the well region in the third epitaxial layer, the method further includes: A plurality of columnar regions are formed in the third epitaxial layer and the second epitaxial layer; the columnar regions are configured with a second conductivity type; each columnar region is located between two adjacent trench preset positions and extends from the first surface to the second surface; the columnar region is in contact with the well region, and the columnar region is also in contact with at least one of the third region and the fourth region; the length of the columnar region in the first direction is less than the length of the trench in the first direction.

15. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1 to 9, wherein the substrate is used to support the semiconductor device.

16. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

17. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 16, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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